514 lines
13 KiB
C
514 lines
13 KiB
C
/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2010 Orex Computed Radiography
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/* based on rtc-mc13892.c */
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/*
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* This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
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* to implement a Linux RTC. Times and alarms are truncated to seconds.
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* Since the RTC framework performs API locking via rtc->ops_lock the
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* only simultaneous accesses we need to deal with is updating DryIce
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* registers while servicing an alarm.
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*
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* Note that reading the DSR (DryIce Status Register) automatically clears
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* the WCF (Write Complete Flag). All DryIce writes are synchronized to the
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* LP (Low Power) domain and set the WCF upon completion. Writes to the
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* DIER (DryIce Interrupt Enable Register) are the only exception. These
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* occur at normal bus speeds and do not set WCF. Periodic interrupts are
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* not supported by the hardware.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/of.h>
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/* DryIce Register Definitions */
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#define DTCMR 0x00 /* Time Counter MSB Reg */
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#define DTCLR 0x04 /* Time Counter LSB Reg */
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#define DCAMR 0x08 /* Clock Alarm MSB Reg */
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#define DCALR 0x0c /* Clock Alarm LSB Reg */
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#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
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#define DCR 0x10 /* Control Reg */
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#define DCR_TCE (1 << 3) /* Time Counter Enable */
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#define DSR 0x14 /* Status Reg */
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#define DSR_WBF (1 << 10) /* Write Busy Flag */
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#define DSR_WNF (1 << 9) /* Write Next Flag */
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#define DSR_WCF (1 << 8) /* Write Complete Flag */
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#define DSR_WEF (1 << 7) /* Write Error Flag */
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#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
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#define DSR_NVF (1 << 1) /* Non-Valid Flag */
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#define DSR_SVF (1 << 0) /* Security Violation Flag */
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#define DIER 0x18 /* Interrupt Enable Reg */
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#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
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#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
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#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
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#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
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/**
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* struct imxdi_dev - private imxdi rtc data
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* @pdev: pionter to platform dev
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* @rtc: pointer to rtc struct
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* @ioaddr: IO registers pointer
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* @irq: dryice normal interrupt
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* @clk: input reference clock
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* @dsr: copy of the DSR register
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* @irq_lock: interrupt enable register (DIER) lock
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* @write_wait: registers write complete queue
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* @write_mutex: serialize registers write
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* @work: schedule alarm work
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*/
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struct imxdi_dev {
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struct platform_device *pdev;
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struct rtc_device *rtc;
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void __iomem *ioaddr;
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int irq;
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struct clk *clk;
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u32 dsr;
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spinlock_t irq_lock;
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wait_queue_head_t write_wait;
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struct mutex write_mutex;
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struct work_struct work;
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};
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/*
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* enable a dryice interrupt
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*/
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static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
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{
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unsigned long flags;
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spin_lock_irqsave(&imxdi->irq_lock, flags);
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__raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
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imxdi->ioaddr + DIER);
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spin_unlock_irqrestore(&imxdi->irq_lock, flags);
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}
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/*
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* disable a dryice interrupt
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*/
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static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
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{
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unsigned long flags;
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spin_lock_irqsave(&imxdi->irq_lock, flags);
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__raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
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imxdi->ioaddr + DIER);
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spin_unlock_irqrestore(&imxdi->irq_lock, flags);
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}
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/*
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* This function attempts to clear the dryice write-error flag.
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*
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* A dryice write error is similar to a bus fault and should not occur in
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* normal operation. Clearing the flag requires another write, so the root
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* cause of the problem may need to be fixed before the flag can be cleared.
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*/
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static void clear_write_error(struct imxdi_dev *imxdi)
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{
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int cnt;
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dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
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/* clear the write error flag */
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__raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
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/* wait for it to take effect */
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for (cnt = 0; cnt < 1000; cnt++) {
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if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
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return;
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udelay(10);
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}
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dev_err(&imxdi->pdev->dev,
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"ERROR: Cannot clear write-error flag!\n");
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}
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/*
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* Write a dryice register and wait until it completes.
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*
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* This function uses interrupts to determine when the
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* write has completed.
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*/
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static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
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{
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int ret;
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int rc = 0;
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/* serialize register writes */
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mutex_lock(&imxdi->write_mutex);
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/* enable the write-complete interrupt */
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di_int_enable(imxdi, DIER_WCIE);
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imxdi->dsr = 0;
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/* do the register write */
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__raw_writel(val, imxdi->ioaddr + reg);
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/* wait for the write to finish */
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ret = wait_event_interruptible_timeout(imxdi->write_wait,
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imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
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if (ret < 0) {
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rc = ret;
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goto out;
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} else if (ret == 0) {
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dev_warn(&imxdi->pdev->dev,
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"Write-wait timeout "
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"val = 0x%08x reg = 0x%08x\n", val, reg);
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}
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/* check for write error */
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if (imxdi->dsr & DSR_WEF) {
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clear_write_error(imxdi);
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rc = -EIO;
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}
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out:
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mutex_unlock(&imxdi->write_mutex);
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return rc;
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}
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/*
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* read the seconds portion of the current time from the dryice time counter
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*/
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static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct imxdi_dev *imxdi = dev_get_drvdata(dev);
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unsigned long now;
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now = __raw_readl(imxdi->ioaddr + DTCMR);
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rtc_time_to_tm(now, tm);
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return 0;
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}
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/*
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* set the seconds portion of dryice time counter and clear the
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* fractional part.
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*/
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static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
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{
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struct imxdi_dev *imxdi = dev_get_drvdata(dev);
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int rc;
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/* zero the fractional part first */
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rc = di_write_wait(imxdi, 0, DTCLR);
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if (rc == 0)
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rc = di_write_wait(imxdi, secs, DTCMR);
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return rc;
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}
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static int dryice_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct imxdi_dev *imxdi = dev_get_drvdata(dev);
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if (enabled)
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di_int_enable(imxdi, DIER_CAIE);
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else
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di_int_disable(imxdi, DIER_CAIE);
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return 0;
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}
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/*
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* read the seconds portion of the alarm register.
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* the fractional part of the alarm register is always zero.
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*/
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static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct imxdi_dev *imxdi = dev_get_drvdata(dev);
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u32 dcamr;
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dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
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rtc_time_to_tm(dcamr, &alarm->time);
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/* alarm is enabled if the interrupt is enabled */
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alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
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/* don't allow the DSR read to mess up DSR_WCF */
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mutex_lock(&imxdi->write_mutex);
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/* alarm is pending if the alarm flag is set */
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alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
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mutex_unlock(&imxdi->write_mutex);
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return 0;
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}
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/*
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* set the seconds portion of dryice alarm register
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*/
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static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct imxdi_dev *imxdi = dev_get_drvdata(dev);
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unsigned long now;
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unsigned long alarm_time;
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int rc;
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rc = rtc_tm_to_time(&alarm->time, &alarm_time);
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if (rc)
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return rc;
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/* don't allow setting alarm in the past */
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now = __raw_readl(imxdi->ioaddr + DTCMR);
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if (alarm_time < now)
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return -EINVAL;
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/* write the new alarm time */
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rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
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if (rc)
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return rc;
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if (alarm->enabled)
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di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
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else
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di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
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return 0;
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}
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static struct rtc_class_ops dryice_rtc_ops = {
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.read_time = dryice_rtc_read_time,
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.set_mmss = dryice_rtc_set_mmss,
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.alarm_irq_enable = dryice_rtc_alarm_irq_enable,
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.read_alarm = dryice_rtc_read_alarm,
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.set_alarm = dryice_rtc_set_alarm,
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};
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/*
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* dryice "normal" interrupt handler
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*/
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static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
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{
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struct imxdi_dev *imxdi = dev_id;
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u32 dsr, dier;
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irqreturn_t rc = IRQ_NONE;
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dier = __raw_readl(imxdi->ioaddr + DIER);
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/* handle write complete and write error cases */
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if ((dier & DIER_WCIE)) {
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/*If the write wait queue is empty then there is no pending
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operations. It means the interrupt is for DryIce -Security.
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IRQ must be returned as none.*/
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if (list_empty_careful(&imxdi->write_wait.task_list))
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return rc;
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/* DSR_WCF clears itself on DSR read */
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dsr = __raw_readl(imxdi->ioaddr + DSR);
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if ((dsr & (DSR_WCF | DSR_WEF))) {
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/* mask the interrupt */
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di_int_disable(imxdi, DIER_WCIE);
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/* save the dsr value for the wait queue */
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imxdi->dsr |= dsr;
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wake_up_interruptible(&imxdi->write_wait);
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rc = IRQ_HANDLED;
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}
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}
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/* handle the alarm case */
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if ((dier & DIER_CAIE)) {
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/* DSR_WCF clears itself on DSR read */
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dsr = __raw_readl(imxdi->ioaddr + DSR);
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if (dsr & DSR_CAF) {
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/* mask the interrupt */
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di_int_disable(imxdi, DIER_CAIE);
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/* finish alarm in user context */
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schedule_work(&imxdi->work);
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rc = IRQ_HANDLED;
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}
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}
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return rc;
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}
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/*
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* post the alarm event from user context so it can sleep
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* on the write completion.
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*/
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static void dryice_work(struct work_struct *work)
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{
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struct imxdi_dev *imxdi = container_of(work,
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struct imxdi_dev, work);
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/* dismiss the interrupt (ignore error) */
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di_write_wait(imxdi, DSR_CAF, DSR);
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/* pass the alarm event to the rtc framework. */
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rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
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}
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/*
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* probe for dryice rtc device
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*/
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static int __init dryice_rtc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct imxdi_dev *imxdi;
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int rc;
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imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
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if (!imxdi)
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return -ENOMEM;
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imxdi->pdev = pdev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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imxdi->ioaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(imxdi->ioaddr))
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return PTR_ERR(imxdi->ioaddr);
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spin_lock_init(&imxdi->irq_lock);
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imxdi->irq = platform_get_irq(pdev, 0);
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if (imxdi->irq < 0)
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return imxdi->irq;
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init_waitqueue_head(&imxdi->write_wait);
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INIT_WORK(&imxdi->work, dryice_work);
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mutex_init(&imxdi->write_mutex);
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imxdi->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(imxdi->clk))
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return PTR_ERR(imxdi->clk);
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rc = clk_prepare_enable(imxdi->clk);
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if (rc)
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return rc;
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/*
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* Initialize dryice hardware
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*/
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/* mask all interrupts */
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__raw_writel(0, imxdi->ioaddr + DIER);
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rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
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IRQF_SHARED, pdev->name, imxdi);
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if (rc) {
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dev_warn(&pdev->dev, "interrupt not available.\n");
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goto err;
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}
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/* put dryice into valid state */
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if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
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rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
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if (rc)
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goto err;
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}
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/* initialize alarm */
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rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
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if (rc)
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goto err;
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rc = di_write_wait(imxdi, 0, DCALR);
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if (rc)
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goto err;
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/* clear alarm flag */
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if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
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rc = di_write_wait(imxdi, DSR_CAF, DSR);
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if (rc)
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goto err;
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}
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/* the timer won't count if it has never been written to */
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if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
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rc = di_write_wait(imxdi, 0, DTCMR);
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if (rc)
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goto err;
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}
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/* start keeping time */
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if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
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rc = di_write_wait(imxdi,
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__raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
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DCR);
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if (rc)
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goto err;
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}
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platform_set_drvdata(pdev, imxdi);
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imxdi->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
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&dryice_rtc_ops, THIS_MODULE);
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if (IS_ERR(imxdi->rtc)) {
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rc = PTR_ERR(imxdi->rtc);
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goto err;
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}
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return 0;
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err:
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clk_disable_unprepare(imxdi->clk);
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return rc;
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}
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static int __exit dryice_rtc_remove(struct platform_device *pdev)
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{
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struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
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flush_work(&imxdi->work);
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/* mask all interrupts */
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__raw_writel(0, imxdi->ioaddr + DIER);
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clk_disable_unprepare(imxdi->clk);
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id dryice_dt_ids[] = {
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{ .compatible = "fsl,imx25-rtc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dryice_dt_ids);
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#endif
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static struct platform_driver dryice_rtc_driver = {
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.driver = {
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.name = "imxdi_rtc",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(dryice_dt_ids),
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},
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.remove = __exit_p(dryice_rtc_remove),
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};
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module_platform_driver_probe(dryice_rtc_driver, dryice_rtc_probe);
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MODULE_AUTHOR("Freescale Semiconductor, Inc.");
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MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
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MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
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MODULE_LICENSE("GPL");
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