Thierry Reding 00c674e42c clk: tegra: Fix clock rate computation ... The PLL output frequency is multiplied during the P-divider computation, so it needs to be divided by the P-divider again before returning. This fixes an issue where clk_round_rate() would return the multiplied frequency instead of the real one after the P-divider. Signed-off-by: Thierry Reding <treding@nvidia.com>		2013-11-26 18:44:00 +02:00
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Makefile	clk: tegra: Implement clocks for Tegra114	2013-04-04 17:17:12 -06:00
clk-audio-sync.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-divider.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-periph-gate.c	clk: tegra: Workaround for Tegra114 MSENC problem	2013-04-04 16:10:59 -06:00
clk-periph.c	clk: tegra: Add flags to tegra_clk_periph()	2013-04-04 16:10:56 -06:00
clk-pll-out.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-pll.c	clk: tegra: Fix clock rate computation	2013-11-26 18:44:00 +02:00
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra20.c	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
clk-tegra30.c	clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks	2013-11-26 18:43:55 +02:00
clk-tegra114.c	clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d	2013-11-26 18:43:59 +02:00
clk.c	clk: tegra: Use common of_clk_init function	2013-05-31 12:57:25 -07:00
clk.h	clk: tegra: T114: add DFLL DVCO reset control	2013-06-18 11:28:51 -07:00