874 lines
23 KiB
C
874 lines
23 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
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*/
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <asm/octeon/octeon.h>
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static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
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static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
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static int octeon_coreid_for_cpu(int cpu)
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{
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#ifdef CONFIG_SMP
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return cpu_logical_map(cpu);
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#else
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return cvmx_get_core_num();
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#endif
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}
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static void octeon_irq_core_ack(unsigned int irq)
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{
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unsigned int bit = irq - OCTEON_IRQ_SW0;
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/*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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* interrupt code.
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*/
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clear_c0_status(0x100 << bit);
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/* The two user interrupts must be cleared manually. */
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if (bit < 2)
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clear_c0_cause(0x100 << bit);
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}
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static void octeon_irq_core_eoi(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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unsigned int bit = irq - OCTEON_IRQ_SW0;
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/*
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* If an IRQ is being processed while we are disabling it the
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* handler will attempt to unmask the interrupt after it has
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* been disabled.
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*/
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if ((unlikely(desc->status & IRQ_DISABLED)))
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return;
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/*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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* interrupt code.
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*/
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set_c0_status(0x100 << bit);
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}
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static void octeon_irq_core_enable(unsigned int irq)
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{
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unsigned long flags;
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unsigned int bit = irq - OCTEON_IRQ_SW0;
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/*
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* We need to disable interrupts to make sure our updates are
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* atomic.
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*/
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local_irq_save(flags);
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set_c0_status(0x100 << bit);
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local_irq_restore(flags);
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}
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static void octeon_irq_core_disable_local(unsigned int irq)
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{
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unsigned long flags;
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unsigned int bit = irq - OCTEON_IRQ_SW0;
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/*
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* We need to disable interrupts to make sure our updates are
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* atomic.
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*/
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local_irq_save(flags);
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clear_c0_status(0x100 << bit);
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local_irq_restore(flags);
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}
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static void octeon_irq_core_disable(unsigned int irq)
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{
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#ifdef CONFIG_SMP
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on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local,
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(void *) (long) irq, 1);
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#else
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octeon_irq_core_disable_local(irq);
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#endif
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}
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static struct irq_chip octeon_irq_chip_core = {
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.name = "Core",
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.enable = octeon_irq_core_enable,
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.disable = octeon_irq_core_disable,
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.ack = octeon_irq_core_ack,
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.eoi = octeon_irq_core_eoi,
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};
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static void octeon_irq_ciu0_ack(unsigned int irq)
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{
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switch (irq) {
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case OCTEON_IRQ_GMX_DRP0:
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case OCTEON_IRQ_GMX_DRP1:
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case OCTEON_IRQ_IPD_DRP:
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case OCTEON_IRQ_KEY_ZERO:
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case OCTEON_IRQ_TIMER0:
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case OCTEON_IRQ_TIMER1:
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case OCTEON_IRQ_TIMER2:
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case OCTEON_IRQ_TIMER3:
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{
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int index = cvmx_get_core_num() * 2;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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/*
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* CIU timer type interrupts must be acknoleged by
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* writing a '1' bit to their sum0 bit.
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*/
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cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
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break;
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}
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default:
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break;
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}
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/*
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* In order to avoid any locking accessing the CIU, we
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* acknowledge CIU interrupts by disabling all of them. This
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* way we can use a per core register and avoid any out of
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* core locking requirements. This has the side affect that
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* CIU interrupts can't be processed recursively.
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*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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* interrupt code.
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*/
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clear_c0_status(0x100 << 2);
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}
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static void octeon_irq_ciu0_eoi(unsigned int irq)
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{
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/*
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* Enable all CIU interrupts again. We don't need to disable
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* IRQs to make these atomic since they are already disabled
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* earlier in the low level interrupt code.
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*/
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set_c0_status(0x100 << 2);
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}
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static int next_coreid_for_irq(struct irq_desc *desc)
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{
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#ifdef CONFIG_SMP
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int coreid;
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int weight = cpumask_weight(desc->affinity);
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if (weight > 1) {
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int cpu = smp_processor_id();
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for (;;) {
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cpu = cpumask_next(cpu, desc->affinity);
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if (cpu >= nr_cpu_ids) {
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cpu = -1;
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continue;
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} else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
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break;
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}
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}
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coreid = octeon_coreid_for_cpu(cpu);
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} else if (weight == 1) {
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coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
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} else {
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coreid = cvmx_get_core_num();
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}
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return coreid;
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#else
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return cvmx_get_core_num();
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#endif
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}
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static void octeon_irq_ciu0_enable(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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int coreid = next_coreid_for_irq(desc);
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unsigned long flags;
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uint64_t en0;
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int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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en0 |= 1ull << bit;
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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}
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static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
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{
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int coreid = cvmx_get_core_num();
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unsigned long flags;
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uint64_t en0;
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int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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en0 |= 1ull << bit;
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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}
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static void octeon_irq_ciu0_disable(unsigned int irq)
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{
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int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
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unsigned long flags;
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uint64_t en0;
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int cpu;
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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en0 &= ~(1ull << bit);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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}
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/*
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* We need to do a read after the last update to make sure all
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* of them are done.
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*/
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cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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}
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/*
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* Enable the irq on the next core in the affinity set for chips that
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* have the EN*_W1{S,C} registers.
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*/
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static void octeon_irq_ciu0_enable_v2(unsigned int irq)
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{
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int index;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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struct irq_desc *desc = irq_to_desc(irq);
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if ((desc->status & IRQ_DISABLED) == 0) {
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index = next_coreid_for_irq(desc) * 2;
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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}
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}
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/*
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* Enable the irq on the current CPU for chips that
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* have the EN*_W1{S,C} registers.
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*/
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static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
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{
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int index;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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index = cvmx_get_core_num() * 2;
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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}
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/*
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* Disable the irq on the current core for chips that have the EN*_W1{S,C}
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* registers.
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*/
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static void octeon_irq_ciu0_ack_v2(unsigned int irq)
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{
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int index = cvmx_get_core_num() * 2;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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switch (irq) {
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case OCTEON_IRQ_GMX_DRP0:
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case OCTEON_IRQ_GMX_DRP1:
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case OCTEON_IRQ_IPD_DRP:
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case OCTEON_IRQ_KEY_ZERO:
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case OCTEON_IRQ_TIMER0:
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case OCTEON_IRQ_TIMER1:
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case OCTEON_IRQ_TIMER2:
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case OCTEON_IRQ_TIMER3:
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/*
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* CIU timer type interrupts must be acknoleged by
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* writing a '1' bit to their sum0 bit.
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*/
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cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
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break;
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default:
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break;
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}
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
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}
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/*
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* Enable the irq on the current core for chips that have the EN*_W1{S,C}
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* registers.
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*/
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static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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int index = cvmx_get_core_num() * 2;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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if (likely((desc->status & IRQ_DISABLED) == 0))
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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}
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/*
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* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
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* registers.
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*/
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static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
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{
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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int index;
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int cpu;
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for_each_online_cpu(cpu) {
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index = octeon_coreid_for_cpu(cpu) * 2;
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
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}
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}
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#ifdef CONFIG_SMP
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static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
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{
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int cpu;
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struct irq_desc *desc = irq_to_desc(irq);
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int enable_one = (desc->status & IRQ_DISABLED) == 0;
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unsigned long flags;
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int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
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/*
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* For non-v2 CIU, we will allow only single CPU affinity.
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* This removes the need to do locking in the .ack/.eoi
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* functions.
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*/
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if (cpumask_weight(dest) != 1)
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return -EINVAL;
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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uint64_t en0 =
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cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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if (cpumask_test_cpu(cpu, dest) && enable_one) {
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enable_one = 0;
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en0 |= 1ull << bit;
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} else {
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en0 &= ~(1ull << bit);
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}
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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}
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/*
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* We need to do a read after the last update to make sure all
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* of them are done.
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*/
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cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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return 0;
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}
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/*
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* Set affinity for the irq for chips that have the EN*_W1{S,C}
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* registers.
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*/
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static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
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const struct cpumask *dest)
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{
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int cpu;
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int index;
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struct irq_desc *desc = irq_to_desc(irq);
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int enable_one = (desc->status & IRQ_DISABLED) == 0;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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for_each_online_cpu(cpu) {
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index = octeon_coreid_for_cpu(cpu) * 2;
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if (cpumask_test_cpu(cpu, dest) && enable_one) {
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enable_one = 0;
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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} else {
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
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}
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}
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return 0;
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}
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#endif
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/*
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* Newer octeon chips have support for lockless CIU operation.
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*/
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static struct irq_chip octeon_irq_chip_ciu0_v2 = {
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.name = "CIU0",
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.enable = octeon_irq_ciu0_enable_v2,
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.disable = octeon_irq_ciu0_disable_all_v2,
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.eoi = octeon_irq_ciu0_enable_v2,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity_v2,
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#endif
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};
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static struct irq_chip octeon_irq_chip_ciu0 = {
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.name = "CIU0",
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.enable = octeon_irq_ciu0_enable,
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.disable = octeon_irq_ciu0_disable,
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.eoi = octeon_irq_ciu0_eoi,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity,
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#endif
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};
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/* The mbox versions don't do any affinity or round-robin. */
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static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
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.name = "CIU0-M",
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.enable = octeon_irq_ciu0_enable_mbox_v2,
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.disable = octeon_irq_ciu0_disable,
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.eoi = octeon_irq_ciu0_eoi_mbox_v2,
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};
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static struct irq_chip octeon_irq_chip_ciu0_mbox = {
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.name = "CIU0-M",
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.enable = octeon_irq_ciu0_enable_mbox,
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.disable = octeon_irq_ciu0_disable,
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.eoi = octeon_irq_ciu0_eoi,
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};
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static void octeon_irq_ciu1_ack(unsigned int irq)
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{
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/*
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* In order to avoid any locking accessing the CIU, we
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* acknowledge CIU interrupts by disabling all of them. This
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* way we can use a per core register and avoid any out of
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* core locking requirements. This has the side affect that
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* CIU interrupts can't be processed recursively. We don't
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* need to disable IRQs to make these atomic since they are
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* already disabled earlier in the low level interrupt code.
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*/
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clear_c0_status(0x100 << 3);
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}
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static void octeon_irq_ciu1_eoi(unsigned int irq)
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{
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/*
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* Enable all CIU interrupts again. We don't need to disable
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* IRQs to make these atomic since they are already disabled
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* earlier in the low level interrupt code.
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*/
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set_c0_status(0x100 << 3);
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}
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static void octeon_irq_ciu1_enable(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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int coreid = next_coreid_for_irq(desc);
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unsigned long flags;
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uint64_t en1;
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int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
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en1 |= 1ull << bit;
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cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
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cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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}
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/*
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* Watchdog interrupts are special. They are associated with a single
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* core, so we hardwire the affinity to that core.
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*/
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static void octeon_irq_ciu1_wd_enable(unsigned int irq)
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{
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unsigned long flags;
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|
uint64_t en1;
|
|
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
|
|
int coreid = bit;
|
|
|
|
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
|
|
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
|
en1 |= 1ull << bit;
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
|
|
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
|
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
|
|
}
|
|
|
|
static void octeon_irq_ciu1_disable(unsigned int irq)
|
|
{
|
|
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
|
|
unsigned long flags;
|
|
uint64_t en1;
|
|
int cpu;
|
|
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
|
|
for_each_online_cpu(cpu) {
|
|
int coreid = octeon_coreid_for_cpu(cpu);
|
|
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
|
en1 &= ~(1ull << bit);
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
|
|
}
|
|
/*
|
|
* We need to do a read after the last update to make sure all
|
|
* of them are done.
|
|
*/
|
|
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
|
|
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
|
|
}
|
|
|
|
/*
|
|
* Enable the irq on the current core for chips that have the EN*_W1{S,C}
|
|
* registers.
|
|
*/
|
|
static void octeon_irq_ciu1_enable_v2(unsigned int irq)
|
|
{
|
|
int index;
|
|
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
|
|
if ((desc->status & IRQ_DISABLED) == 0) {
|
|
index = next_coreid_for_irq(desc) * 2 + 1;
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Watchdog interrupts are special. They are associated with a single
|
|
* core, so we hardwire the affinity to that core.
|
|
*/
|
|
static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
|
|
{
|
|
int index;
|
|
int coreid = irq - OCTEON_IRQ_WDOG0;
|
|
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
|
|
if ((desc->status & IRQ_DISABLED) == 0) {
|
|
index = coreid * 2 + 1;
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Disable the irq on the current core for chips that have the EN*_W1{S,C}
|
|
* registers.
|
|
*/
|
|
static void octeon_irq_ciu1_ack_v2(unsigned int irq)
|
|
{
|
|
int index = cvmx_get_core_num() * 2 + 1;
|
|
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
|
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
|
|
}
|
|
|
|
/*
|
|
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
|
|
* registers.
|
|
*/
|
|
static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
|
|
{
|
|
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
|
int index;
|
|
int cpu;
|
|
for_each_online_cpu(cpu) {
|
|
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
static int octeon_irq_ciu1_set_affinity(unsigned int irq,
|
|
const struct cpumask *dest)
|
|
{
|
|
int cpu;
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
int enable_one = (desc->status & IRQ_DISABLED) == 0;
|
|
unsigned long flags;
|
|
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
|
|
|
|
/*
|
|
* For non-v2 CIU, we will allow only single CPU affinity.
|
|
* This removes the need to do locking in the .ack/.eoi
|
|
* functions.
|
|
*/
|
|
if (cpumask_weight(dest) != 1)
|
|
return -EINVAL;
|
|
|
|
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
|
|
for_each_online_cpu(cpu) {
|
|
int coreid = octeon_coreid_for_cpu(cpu);
|
|
uint64_t en1 =
|
|
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
|
if (cpumask_test_cpu(cpu, dest) && enable_one) {
|
|
enable_one = 0;
|
|
en1 |= 1ull << bit;
|
|
} else {
|
|
en1 &= ~(1ull << bit);
|
|
}
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
|
|
}
|
|
/*
|
|
* We need to do a read after the last update to make sure all
|
|
* of them are done.
|
|
*/
|
|
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
|
|
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set affinity for the irq for chips that have the EN*_W1{S,C}
|
|
* registers.
|
|
*/
|
|
static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
|
|
const struct cpumask *dest)
|
|
{
|
|
int cpu;
|
|
int index;
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
int enable_one = (desc->status & IRQ_DISABLED) == 0;
|
|
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
|
for_each_online_cpu(cpu) {
|
|
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
|
|
if (cpumask_test_cpu(cpu, dest) && enable_one) {
|
|
enable_one = 0;
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
|
|
} else {
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Newer octeon chips have support for lockless CIU operation.
|
|
*/
|
|
static struct irq_chip octeon_irq_chip_ciu1_v2 = {
|
|
.name = "CIU1",
|
|
.enable = octeon_irq_ciu1_enable_v2,
|
|
.disable = octeon_irq_ciu1_disable_all_v2,
|
|
.eoi = octeon_irq_ciu1_enable_v2,
|
|
#ifdef CONFIG_SMP
|
|
.set_affinity = octeon_irq_ciu1_set_affinity_v2,
|
|
#endif
|
|
};
|
|
|
|
static struct irq_chip octeon_irq_chip_ciu1 = {
|
|
.name = "CIU1",
|
|
.enable = octeon_irq_ciu1_enable,
|
|
.disable = octeon_irq_ciu1_disable,
|
|
.eoi = octeon_irq_ciu1_eoi,
|
|
#ifdef CONFIG_SMP
|
|
.set_affinity = octeon_irq_ciu1_set_affinity,
|
|
#endif
|
|
};
|
|
|
|
static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
|
|
.name = "CIU1-W",
|
|
.enable = octeon_irq_ciu1_wd_enable_v2,
|
|
.disable = octeon_irq_ciu1_disable_all_v2,
|
|
.eoi = octeon_irq_ciu1_wd_enable_v2,
|
|
};
|
|
|
|
static struct irq_chip octeon_irq_chip_ciu1_wd = {
|
|
.name = "CIU1-W",
|
|
.enable = octeon_irq_ciu1_wd_enable,
|
|
.disable = octeon_irq_ciu1_disable,
|
|
.eoi = octeon_irq_ciu1_eoi,
|
|
};
|
|
|
|
static void (*octeon_ciu0_ack)(unsigned int);
|
|
static void (*octeon_ciu1_ack)(unsigned int);
|
|
|
|
void __init arch_init_irq(void)
|
|
{
|
|
unsigned int irq;
|
|
struct irq_chip *chip0;
|
|
struct irq_chip *chip0_mbox;
|
|
struct irq_chip *chip1;
|
|
struct irq_chip *chip1_wd;
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* Set the default affinity to the boot cpu. */
|
|
cpumask_clear(irq_default_affinity);
|
|
cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
|
|
#endif
|
|
|
|
if (NR_IRQS < OCTEON_IRQ_LAST)
|
|
pr_err("octeon_irq_init: NR_IRQS is set too low\n");
|
|
|
|
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
|
|
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
|
|
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
|
|
octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
|
|
octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
|
|
chip0 = &octeon_irq_chip_ciu0_v2;
|
|
chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
|
|
chip1 = &octeon_irq_chip_ciu1_v2;
|
|
chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
|
|
} else {
|
|
octeon_ciu0_ack = octeon_irq_ciu0_ack;
|
|
octeon_ciu1_ack = octeon_irq_ciu1_ack;
|
|
chip0 = &octeon_irq_chip_ciu0;
|
|
chip0_mbox = &octeon_irq_chip_ciu0_mbox;
|
|
chip1 = &octeon_irq_chip_ciu1;
|
|
chip1_wd = &octeon_irq_chip_ciu1_wd;
|
|
}
|
|
|
|
/* 0 - 15 reserved for i8259 master and slave controller. */
|
|
|
|
/* 17 - 23 Mips internal */
|
|
for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
|
|
set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
|
|
handle_percpu_irq);
|
|
}
|
|
|
|
/* 24 - 87 CIU_INT_SUM0 */
|
|
for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
|
|
switch (irq) {
|
|
case OCTEON_IRQ_MBOX0:
|
|
case OCTEON_IRQ_MBOX1:
|
|
set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
|
|
break;
|
|
default:
|
|
set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* 88 - 151 CIU_INT_SUM1 */
|
|
for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
|
|
set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
|
|
|
|
for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
|
|
set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
|
|
|
|
set_c0_status(0x300 << 2);
|
|
}
|
|
|
|
asmlinkage void plat_irq_dispatch(void)
|
|
{
|
|
const unsigned long core_id = cvmx_get_core_num();
|
|
const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
|
|
const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
|
|
const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
|
|
const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
|
|
unsigned long cop0_cause;
|
|
unsigned long cop0_status;
|
|
uint64_t ciu_en;
|
|
uint64_t ciu_sum;
|
|
unsigned int irq;
|
|
|
|
while (1) {
|
|
cop0_cause = read_c0_cause();
|
|
cop0_status = read_c0_status();
|
|
cop0_cause &= cop0_status;
|
|
cop0_cause &= ST0_IM;
|
|
|
|
if (unlikely(cop0_cause & STATUSF_IP2)) {
|
|
ciu_sum = cvmx_read_csr(ciu_sum0_address);
|
|
ciu_en = cvmx_read_csr(ciu_en0_address);
|
|
ciu_sum &= ciu_en;
|
|
if (likely(ciu_sum)) {
|
|
irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
|
|
octeon_ciu0_ack(irq);
|
|
do_IRQ(irq);
|
|
} else {
|
|
spurious_interrupt();
|
|
}
|
|
} else if (unlikely(cop0_cause & STATUSF_IP3)) {
|
|
ciu_sum = cvmx_read_csr(ciu_sum1_address);
|
|
ciu_en = cvmx_read_csr(ciu_en1_address);
|
|
ciu_sum &= ciu_en;
|
|
if (likely(ciu_sum)) {
|
|
irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
|
|
octeon_ciu1_ack(irq);
|
|
do_IRQ(irq);
|
|
} else {
|
|
spurious_interrupt();
|
|
}
|
|
} else if (likely(cop0_cause)) {
|
|
do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
void fixup_irqs(void)
|
|
{
|
|
int irq;
|
|
struct irq_desc *desc;
|
|
cpumask_t new_affinity;
|
|
unsigned long flags;
|
|
int do_set_affinity;
|
|
int cpu;
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
|
|
octeon_irq_core_disable_local(irq);
|
|
|
|
for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
|
|
desc = irq_to_desc(irq);
|
|
switch (irq) {
|
|
case OCTEON_IRQ_MBOX0:
|
|
case OCTEON_IRQ_MBOX1:
|
|
/* The eoi function will disable them on this CPU. */
|
|
desc->chip->eoi(irq);
|
|
break;
|
|
case OCTEON_IRQ_WDOG0:
|
|
case OCTEON_IRQ_WDOG1:
|
|
case OCTEON_IRQ_WDOG2:
|
|
case OCTEON_IRQ_WDOG3:
|
|
case OCTEON_IRQ_WDOG4:
|
|
case OCTEON_IRQ_WDOG5:
|
|
case OCTEON_IRQ_WDOG6:
|
|
case OCTEON_IRQ_WDOG7:
|
|
case OCTEON_IRQ_WDOG8:
|
|
case OCTEON_IRQ_WDOG9:
|
|
case OCTEON_IRQ_WDOG10:
|
|
case OCTEON_IRQ_WDOG11:
|
|
case OCTEON_IRQ_WDOG12:
|
|
case OCTEON_IRQ_WDOG13:
|
|
case OCTEON_IRQ_WDOG14:
|
|
case OCTEON_IRQ_WDOG15:
|
|
/*
|
|
* These have special per CPU semantics and
|
|
* are handled in the watchdog driver.
|
|
*/
|
|
break;
|
|
default:
|
|
raw_spin_lock_irqsave(&desc->lock, flags);
|
|
/*
|
|
* If this irq has an action, it is in use and
|
|
* must be migrated if it has affinity to this
|
|
* cpu.
|
|
*/
|
|
if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
|
|
if (cpumask_weight(desc->affinity) > 1) {
|
|
/*
|
|
* It has multi CPU affinity,
|
|
* just remove this CPU from
|
|
* the affinity set.
|
|
*/
|
|
cpumask_copy(&new_affinity, desc->affinity);
|
|
cpumask_clear_cpu(cpu, &new_affinity);
|
|
} else {
|
|
/*
|
|
* Otherwise, put it on lowest
|
|
* numbered online CPU.
|
|
*/
|
|
cpumask_clear(&new_affinity);
|
|
cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
|
|
}
|
|
do_set_affinity = 1;
|
|
} else {
|
|
do_set_affinity = 0;
|
|
}
|
|
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
|
|
|
if (do_set_affinity)
|
|
irq_set_affinity(irq, &new_affinity);
|
|
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif /* CONFIG_HOTPLUG_CPU */
|