OpenCloudOS-Kernel/drivers/gpu
Imre Deak 001bd2cb17 drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
The pattern of a power well backing a set of pipe IRQ or VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
GEN9+ power well code in follow-up patches.

Also use u8 for pipe_mask in related helpers to match the type in the
power well struct.

v2:
- Use u8 instead of u32 for irq_pipe_mask. (Ville)

v3:
- Use u8 for pipe_mask in related helpers too for clarity.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170712155413.29839-1-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-07-27 09:38:53 +02:00
..
drm drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes 2017-07-27 09:38:53 +02:00
host1x Linux 4.12-rc7 2017-06-27 08:28:30 +10:00
ipu-v3 drm: Convert to using %pOF instead of full_name 2017-07-26 13:45:06 +02:00
vga sched/wait: Rename wait_queue_t => wait_queue_entry_t 2017-06-20 12:18:27 +02:00
Makefile