612 lines
15 KiB
C
612 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMD Secure Processor device driver
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*
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* Copyright (C) 2013,2019 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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* Author: Gary R Hook <gary.hook@amd.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/dma-mapping.h>
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#include <linux/kthread.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/ccp.h>
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#include "ccp-dev.h"
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#include "psp-dev.h"
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#include "hygon/sp-dev.h"
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/* used for version string AA.BB.CC.DD */
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#define AA GENMASK(31, 24)
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#define BB GENMASK(23, 16)
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#define CC GENMASK(15, 8)
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#define DD GENMASK(7, 0)
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#define MSIX_VECTORS 2
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struct sp_pci {
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int msix_count;
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struct msix_entry msix_entry[MSIX_VECTORS];
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};
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static struct sp_device *sp_dev_master;
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#define security_attribute_show(name, def) \
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static ssize_t name##_show(struct device *d, struct device_attribute *attr, \
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char *buf) \
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{ \
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struct sp_device *sp = dev_get_drvdata(d); \
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struct psp_device *psp = sp->psp_data; \
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int bit = PSP_SECURITY_##def << PSP_CAPABILITY_PSP_SECURITY_OFFSET; \
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return sysfs_emit(buf, "%d\n", (psp->capability & bit) > 0); \
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}
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security_attribute_show(fused_part, FUSED_PART)
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static DEVICE_ATTR_RO(fused_part);
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security_attribute_show(debug_lock_on, DEBUG_LOCK_ON)
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static DEVICE_ATTR_RO(debug_lock_on);
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security_attribute_show(tsme_status, TSME_STATUS)
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static DEVICE_ATTR_RO(tsme_status);
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security_attribute_show(anti_rollback_status, ANTI_ROLLBACK_STATUS)
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static DEVICE_ATTR_RO(anti_rollback_status);
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security_attribute_show(rpmc_production_enabled, RPMC_PRODUCTION_ENABLED)
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static DEVICE_ATTR_RO(rpmc_production_enabled);
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security_attribute_show(rpmc_spirom_available, RPMC_SPIROM_AVAILABLE)
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static DEVICE_ATTR_RO(rpmc_spirom_available);
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security_attribute_show(hsp_tpm_available, HSP_TPM_AVAILABLE)
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static DEVICE_ATTR_RO(hsp_tpm_available);
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security_attribute_show(rom_armor_enforced, ROM_ARMOR_ENFORCED)
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static DEVICE_ATTR_RO(rom_armor_enforced);
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static struct attribute *psp_security_attrs[] = {
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&dev_attr_fused_part.attr,
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&dev_attr_debug_lock_on.attr,
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&dev_attr_tsme_status.attr,
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&dev_attr_anti_rollback_status.attr,
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&dev_attr_rpmc_production_enabled.attr,
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&dev_attr_rpmc_spirom_available.attr,
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&dev_attr_hsp_tpm_available.attr,
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&dev_attr_rom_armor_enforced.attr,
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NULL
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};
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static umode_t psp_security_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct sp_device *sp = dev_get_drvdata(dev);
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struct psp_device *psp = sp->psp_data;
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if (psp && (psp->capability & PSP_CAPABILITY_PSP_SECURITY_REPORTING))
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return 0444;
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return 0;
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}
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static struct attribute_group psp_security_attr_group = {
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.attrs = psp_security_attrs,
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.is_visible = psp_security_is_visible,
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};
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#define version_attribute_show(name, _offset) \
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static ssize_t name##_show(struct device *d, struct device_attribute *attr, \
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char *buf) \
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{ \
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struct sp_device *sp = dev_get_drvdata(d); \
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struct psp_device *psp = sp->psp_data; \
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unsigned int val = ioread32(psp->io_regs + _offset); \
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return sysfs_emit(buf, "%02lx.%02lx.%02lx.%02lx\n", \
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FIELD_GET(AA, val), \
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FIELD_GET(BB, val), \
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FIELD_GET(CC, val), \
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FIELD_GET(DD, val)); \
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}
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version_attribute_show(bootloader_version, psp->vdata->bootloader_info_reg)
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static DEVICE_ATTR_RO(bootloader_version);
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version_attribute_show(tee_version, psp->vdata->tee->info_reg)
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static DEVICE_ATTR_RO(tee_version);
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static struct attribute *psp_firmware_attrs[] = {
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&dev_attr_bootloader_version.attr,
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&dev_attr_tee_version.attr,
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NULL,
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};
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static umode_t psp_firmware_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct sp_device *sp = dev_get_drvdata(dev);
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struct psp_device *psp = sp->psp_data;
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unsigned int val = 0xffffffff;
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if (!psp)
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return 0;
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if (attr == &dev_attr_bootloader_version.attr &&
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psp->vdata->bootloader_info_reg)
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val = ioread32(psp->io_regs + psp->vdata->bootloader_info_reg);
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if (attr == &dev_attr_tee_version.attr &&
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psp->capability & PSP_CAPABILITY_TEE &&
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psp->vdata->tee->info_reg)
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val = ioread32(psp->io_regs + psp->vdata->tee->info_reg);
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/* If platform disallows accessing this register it will be all f's */
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if (val != 0xffffffff)
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return 0444;
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return 0;
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}
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static struct attribute_group psp_firmware_attr_group = {
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.attrs = psp_firmware_attrs,
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.is_visible = psp_firmware_is_visible,
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};
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static const struct attribute_group *psp_groups[] = {
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&psp_security_attr_group,
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&psp_firmware_attr_group,
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NULL,
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};
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static int sp_get_msix_irqs(struct sp_device *sp)
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{
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struct sp_pci *sp_pci = sp->dev_specific;
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struct device *dev = sp->dev;
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struct pci_dev *pdev = to_pci_dev(dev);
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int v, ret;
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for (v = 0; v < ARRAY_SIZE(sp_pci->msix_entry); v++)
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sp_pci->msix_entry[v].entry = v;
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ret = pci_enable_msix_range(pdev, sp_pci->msix_entry, 1, v);
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if (ret < 0)
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return ret;
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sp_pci->msix_count = ret;
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sp->use_tasklet = true;
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sp->psp_irq = sp_pci->msix_entry[0].vector;
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sp->ccp_irq = (sp_pci->msix_count > 1) ? sp_pci->msix_entry[1].vector
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: sp_pci->msix_entry[0].vector;
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return 0;
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}
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static int sp_get_msi_irq(struct sp_device *sp)
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{
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struct device *dev = sp->dev;
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struct pci_dev *pdev = to_pci_dev(dev);
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int ret;
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ret = pci_enable_msi(pdev);
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if (ret)
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return ret;
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sp->ccp_irq = pdev->irq;
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sp->psp_irq = pdev->irq;
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return 0;
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}
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static int sp_get_irqs(struct sp_device *sp)
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{
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struct device *dev = sp->dev;
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int ret;
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ret = sp_get_msix_irqs(sp);
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if (!ret)
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return 0;
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/* Couldn't get MSI-X vectors, try MSI */
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dev_notice(dev, "could not enable MSI-X (%d), trying MSI\n", ret);
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ret = sp_get_msi_irq(sp);
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if (!ret)
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return 0;
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/* Couldn't get MSI interrupt */
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dev_notice(dev, "could not enable MSI (%d)\n", ret);
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return ret;
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}
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static void sp_free_irqs(struct sp_device *sp)
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{
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struct sp_pci *sp_pci = sp->dev_specific;
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struct device *dev = sp->dev;
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struct pci_dev *pdev = to_pci_dev(dev);
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if (sp_pci->msix_count)
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pci_disable_msix(pdev);
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else if (sp->psp_irq)
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pci_disable_msi(pdev);
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sp->ccp_irq = 0;
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sp->psp_irq = 0;
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}
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static bool sp_pci_is_master(struct sp_device *sp)
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{
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struct device *dev_cur, *dev_new;
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struct pci_dev *pdev_cur, *pdev_new;
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dev_new = sp->dev;
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dev_cur = sp_dev_master->dev;
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pdev_new = to_pci_dev(dev_new);
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pdev_cur = to_pci_dev(dev_cur);
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if (pdev_new->bus->number < pdev_cur->bus->number)
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return true;
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if (PCI_SLOT(pdev_new->devfn) < PCI_SLOT(pdev_cur->devfn))
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return true;
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if (PCI_FUNC(pdev_new->devfn) < PCI_FUNC(pdev_cur->devfn))
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return true;
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return false;
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}
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static void psp_set_master(struct sp_device *sp)
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{
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if (!sp_dev_master) {
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sp_dev_master = sp;
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return;
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}
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if (sp_pci_is_master(sp))
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sp_dev_master = sp;
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}
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static struct sp_device *psp_get_master(void)
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{
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return sp_dev_master;
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}
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static void psp_clear_master(struct sp_device *sp)
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{
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if (sp == sp_dev_master) {
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sp_dev_master = NULL;
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dev_dbg(sp->dev, "Cleared sp_dev_master\n");
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}
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}
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static int sp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct sp_device *sp;
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struct sp_pci *sp_pci;
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struct device *dev = &pdev->dev;
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void __iomem * const *iomap_table;
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int bar_mask;
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int ret;
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ret = -ENOMEM;
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sp = sp_alloc_struct(dev);
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if (!sp)
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goto e_err;
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sp_pci = devm_kzalloc(dev, sizeof(*sp_pci), GFP_KERNEL);
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if (!sp_pci)
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goto e_err;
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sp->dev_specific = sp_pci;
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sp->dev_vdata = (struct sp_dev_vdata *)id->driver_data;
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if (!sp->dev_vdata) {
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ret = -ENODEV;
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dev_err(dev, "missing driver data\n");
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goto e_err;
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}
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ret = pcim_enable_device(pdev);
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if (ret) {
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dev_err(dev, "pcim_enable_device failed (%d)\n", ret);
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goto e_err;
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}
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bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
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ret = pcim_iomap_regions(pdev, bar_mask, "ccp");
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if (ret) {
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dev_err(dev, "pcim_iomap_regions failed (%d)\n", ret);
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goto e_err;
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}
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iomap_table = pcim_iomap_table(pdev);
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if (!iomap_table) {
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dev_err(dev, "pcim_iomap_table failed\n");
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ret = -ENOMEM;
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goto e_err;
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}
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sp->io_map = iomap_table[sp->dev_vdata->bar];
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if (!sp->io_map) {
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dev_err(dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto e_err;
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}
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ret = sp_get_irqs(sp);
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if (ret)
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goto e_err;
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pci_set_master(pdev);
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sp->set_psp_master_device = psp_set_master;
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sp->get_psp_master_device = psp_get_master;
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sp->clear_psp_master_device = psp_clear_master;
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
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if (ret) {
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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if (ret) {
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dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n",
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ret);
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goto free_irqs;
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}
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}
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dev_set_drvdata(dev, sp);
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ret = sp_init(sp);
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if (ret)
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goto free_irqs;
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return 0;
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free_irqs:
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sp_free_irqs(sp);
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e_err:
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dev_notice(dev, "initialization failed\n");
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return ret;
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}
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static void sp_pci_shutdown(struct pci_dev *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sp_device *sp = dev_get_drvdata(dev);
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if (!sp)
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return;
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sp_destroy(sp);
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}
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static void sp_pci_remove(struct pci_dev *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sp_device *sp = dev_get_drvdata(dev);
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if (!sp)
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return;
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sp_destroy(sp);
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sp_free_irqs(sp);
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}
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static int __maybe_unused sp_pci_suspend(struct device *dev)
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{
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struct sp_device *sp = dev_get_drvdata(dev);
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return sp_suspend(sp);
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}
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static int __maybe_unused sp_pci_resume(struct device *dev)
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{
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struct sp_device *sp = dev_get_drvdata(dev);
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return sp_resume(sp);
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}
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#ifdef CONFIG_CRYPTO_DEV_SP_PSP
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static const struct sev_vdata sevv1 = {
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.cmdresp_reg = 0x10580, /* C2PMSG_32 */
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.cmdbuff_addr_lo_reg = 0x105e0, /* C2PMSG_56 */
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.cmdbuff_addr_hi_reg = 0x105e4, /* C2PMSG_57 */
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};
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static const struct sev_vdata sevv2 = {
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.cmdresp_reg = 0x10980, /* C2PMSG_32 */
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.cmdbuff_addr_lo_reg = 0x109e0, /* C2PMSG_56 */
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.cmdbuff_addr_hi_reg = 0x109e4, /* C2PMSG_57 */
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};
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static const struct tee_vdata teev1 = {
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.cmdresp_reg = 0x10544, /* C2PMSG_17 */
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.cmdbuff_addr_lo_reg = 0x10548, /* C2PMSG_18 */
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.cmdbuff_addr_hi_reg = 0x1054c, /* C2PMSG_19 */
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.ring_wptr_reg = 0x10550, /* C2PMSG_20 */
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.ring_rptr_reg = 0x10554, /* C2PMSG_21 */
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.info_reg = 0x109e8, /* C2PMSG_58 */
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};
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static const struct tee_vdata teev2 = {
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.cmdresp_reg = 0x10944, /* C2PMSG_17 */
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.cmdbuff_addr_lo_reg = 0x10948, /* C2PMSG_18 */
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.cmdbuff_addr_hi_reg = 0x1094c, /* C2PMSG_19 */
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.ring_wptr_reg = 0x10950, /* C2PMSG_20 */
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.ring_rptr_reg = 0x10954, /* C2PMSG_21 */
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};
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static const struct platform_access_vdata pa_v1 = {
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.cmdresp_reg = 0x10570, /* C2PMSG_28 */
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.cmdbuff_addr_lo_reg = 0x10574, /* C2PMSG_29 */
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.cmdbuff_addr_hi_reg = 0x10578, /* C2PMSG_30 */
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.doorbell_button_reg = 0x10a24, /* C2PMSG_73 */
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.doorbell_cmd_reg = 0x10a40, /* C2PMSG_80 */
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};
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static const struct platform_access_vdata pa_v2 = {
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.doorbell_button_reg = 0x10a24, /* C2PMSG_73 */
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.doorbell_cmd_reg = 0x10a40, /* C2PMSG_80 */
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};
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static const struct psp_vdata pspv1 = {
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.sev = &sevv1,
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.bootloader_info_reg = 0x105ec, /* C2PMSG_59 */
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.feature_reg = 0x105fc, /* C2PMSG_63 */
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.inten_reg = 0x10610, /* P2CMSG_INTEN */
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.intsts_reg = 0x10614, /* P2CMSG_INTSTS */
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};
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static const struct psp_vdata pspv2 = {
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.sev = &sevv2,
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.bootloader_info_reg = 0x109ec, /* C2PMSG_59 */
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.feature_reg = 0x109fc, /* C2PMSG_63 */
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.inten_reg = 0x10690, /* P2CMSG_INTEN */
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.intsts_reg = 0x10694, /* P2CMSG_INTSTS */
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};
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static const struct psp_vdata pspv3 = {
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.tee = &teev1,
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.platform_access = &pa_v1,
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.bootloader_info_reg = 0x109ec, /* C2PMSG_59 */
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.feature_reg = 0x109fc, /* C2PMSG_63 */
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.inten_reg = 0x10690, /* P2CMSG_INTEN */
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.intsts_reg = 0x10694, /* P2CMSG_INTSTS */
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.platform_features = PLATFORM_FEATURE_DBC,
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};
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static const struct psp_vdata pspv4 = {
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.sev = &sevv2,
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.tee = &teev1,
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.bootloader_info_reg = 0x109ec, /* C2PMSG_59 */
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.feature_reg = 0x109fc, /* C2PMSG_63 */
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.inten_reg = 0x10690, /* P2CMSG_INTEN */
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.intsts_reg = 0x10694, /* P2CMSG_INTSTS */
|
|
};
|
|
|
|
static const struct psp_vdata pspv5 = {
|
|
.tee = &teev2,
|
|
.platform_access = &pa_v2,
|
|
.feature_reg = 0x109fc, /* C2PMSG_63 */
|
|
.inten_reg = 0x10510, /* P2CMSG_INTEN */
|
|
.intsts_reg = 0x10514, /* P2CMSG_INTSTS */
|
|
};
|
|
|
|
static const struct psp_vdata pspv6 = {
|
|
.sev = &sevv2,
|
|
.tee = &teev2,
|
|
.feature_reg = 0x109fc, /* C2PMSG_63 */
|
|
.inten_reg = 0x10510, /* P2CMSG_INTEN */
|
|
.intsts_reg = 0x10514, /* P2CMSG_INTSTS */
|
|
};
|
|
|
|
#endif
|
|
|
|
static const struct sp_dev_vdata dev_vdata[] = {
|
|
{ /* 0 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_CCP
|
|
.ccp_vdata = &ccpv3,
|
|
#endif
|
|
},
|
|
{ /* 1 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_CCP
|
|
.ccp_vdata = &ccpv5a,
|
|
#endif
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_PSP
|
|
.psp_vdata = &pspv1,
|
|
#endif
|
|
},
|
|
{ /* 2 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_CCP
|
|
.ccp_vdata = &ccpv5b,
|
|
#endif
|
|
},
|
|
{ /* 3 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_CCP
|
|
.ccp_vdata = &ccpv5a,
|
|
#endif
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_PSP
|
|
.psp_vdata = &pspv2,
|
|
#endif
|
|
},
|
|
{ /* 4 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_CCP
|
|
.ccp_vdata = &ccpv5a,
|
|
#endif
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_PSP
|
|
.psp_vdata = &pspv3,
|
|
#endif
|
|
},
|
|
{ /* 5 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_PSP
|
|
.psp_vdata = &pspv4,
|
|
#endif
|
|
},
|
|
{ /* 6 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_PSP
|
|
.psp_vdata = &pspv3,
|
|
#endif
|
|
},
|
|
{ /* 7 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_PSP
|
|
.psp_vdata = &pspv5,
|
|
#endif
|
|
},
|
|
{ /* 8 */
|
|
.bar = 2,
|
|
#ifdef CONFIG_CRYPTO_DEV_SP_PSP
|
|
.psp_vdata = &pspv6,
|
|
#endif
|
|
},
|
|
};
|
|
static const struct pci_device_id sp_pci_table[] = {
|
|
{ PCI_VDEVICE(AMD, 0x1537), (kernel_ulong_t)&dev_vdata[0] },
|
|
{ PCI_VDEVICE(AMD, 0x1456), (kernel_ulong_t)&dev_vdata[1] },
|
|
{ PCI_VDEVICE(AMD, 0x1468), (kernel_ulong_t)&dev_vdata[2] },
|
|
{ PCI_VDEVICE(AMD, 0x1486), (kernel_ulong_t)&dev_vdata[3] },
|
|
{ PCI_VDEVICE(AMD, 0x15DF), (kernel_ulong_t)&dev_vdata[4] },
|
|
{ PCI_VDEVICE(AMD, 0x14CA), (kernel_ulong_t)&dev_vdata[5] },
|
|
{ PCI_VDEVICE(AMD, 0x15C7), (kernel_ulong_t)&dev_vdata[6] },
|
|
{ PCI_VDEVICE(AMD, 0x1649), (kernel_ulong_t)&dev_vdata[6] },
|
|
{ PCI_VDEVICE(AMD, 0x17E0), (kernel_ulong_t)&dev_vdata[7] },
|
|
{ PCI_VDEVICE(AMD, 0x156E), (kernel_ulong_t)&dev_vdata[8] },
|
|
{ PCI_VDEVICE(HYGON, 0x1456), (kernel_ulong_t)&hygon_dev_vdata[0] },
|
|
{ PCI_VDEVICE(HYGON, 0x1468), (kernel_ulong_t)&hygon_dev_vdata[1] },
|
|
{ PCI_VDEVICE(HYGON, 0x1486), (kernel_ulong_t)&hygon_dev_vdata[2] },
|
|
{ PCI_VDEVICE(HYGON, 0x14b8), (kernel_ulong_t)&hygon_dev_vdata[1] },
|
|
{ PCI_VDEVICE(HYGON, 0x14a6), (kernel_ulong_t)&hygon_dev_vdata[2] },
|
|
/* Last entry must be zero */
|
|
{ 0, }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, sp_pci_table);
|
|
|
|
static SIMPLE_DEV_PM_OPS(sp_pci_pm_ops, sp_pci_suspend, sp_pci_resume);
|
|
|
|
static struct pci_driver sp_pci_driver = {
|
|
.name = "ccp",
|
|
.id_table = sp_pci_table,
|
|
.probe = sp_pci_probe,
|
|
.remove = sp_pci_remove,
|
|
.shutdown = sp_pci_shutdown,
|
|
.driver.pm = &sp_pci_pm_ops,
|
|
.dev_groups = psp_groups,
|
|
};
|
|
|
|
int sp_pci_init(void)
|
|
{
|
|
return pci_register_driver(&sp_pci_driver);
|
|
}
|
|
|
|
void sp_pci_exit(void)
|
|
{
|
|
pci_unregister_driver(&sp_pci_driver);
|
|
}
|