167 lines
4.1 KiB
C
167 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a7779 Core CPG Clocks
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*
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* Copyright (C) 2013, 2014 Horms Solutions Ltd.
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*
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* Contact: Simon Horman <horms@verge.net.au>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a7779-clock.h>
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#define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)
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/* -----------------------------------------------------------------------------
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* CPG Clock Data
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*/
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/*
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* MD1 = 1 MD1 = 0
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* (PLLA = 1500) (PLLA = 1600)
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* (MHz) (MHz)
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*------------------------------------------------+--------------------
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* clkz 1000 (2/3) 800 (1/2)
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* clkzs 250 (1/6) 200 (1/8)
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* clki 750 (1/2) 800 (1/2)
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* clks 250 (1/6) 200 (1/8)
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* clks1 125 (1/12) 100 (1/16)
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* clks3 187.5 (1/8) 200 (1/8)
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* clks4 93.7 (1/16) 100 (1/16)
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* clkp 62.5 (1/24) 50 (1/32)
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* clkg 62.5 (1/24) 66.6 (1/24)
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* clkb, CLKOUT
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* (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
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* (MD2 = 1) 41.6 (1/36) 50 (1/32)
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*/
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#define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1)
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struct cpg_clk_config {
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unsigned int z_mult;
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unsigned int z_div;
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unsigned int zs_and_s_div;
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unsigned int s1_div;
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unsigned int p_div;
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unsigned int b_and_out_div;
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};
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static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
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{ 1, 2, 8, 16, 32, 24 },
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{ 2, 3, 6, 12, 24, 24 },
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{ 1, 2, 8, 16, 32, 32 },
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{ 2, 3, 6, 12, 24, 36 },
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};
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/*
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* MD PLLA Ratio
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* 12 11
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*------------------------
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* 0 0 x42
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* 0 1 x48
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* 1 0 x56
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* 1 1 x64
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*/
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#define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11)
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static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
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/* -----------------------------------------------------------------------------
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* Initialization
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*/
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static struct clk * __init
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r8a7779_cpg_register_clock(struct device_node *np,
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const struct cpg_clk_config *config,
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unsigned int plla_mult, const char *name)
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{
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const char *parent_name = "plla";
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unsigned int mult = 1;
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unsigned int div = 1;
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if (!strcmp(name, "plla")) {
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parent_name = of_clk_get_parent_name(np, 0);
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mult = plla_mult;
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} else if (!strcmp(name, "z")) {
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div = config->z_div;
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mult = config->z_mult;
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} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
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div = config->zs_and_s_div;
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} else if (!strcmp(name, "s1")) {
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div = config->s1_div;
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} else if (!strcmp(name, "p")) {
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div = config->p_div;
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} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
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div = config->b_and_out_div;
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} else {
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return ERR_PTR(-EINVAL);
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}
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return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
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}
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static void __init r8a7779_cpg_clocks_init(struct device_node *np)
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{
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const struct cpg_clk_config *config;
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struct clk_onecell_data *data;
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struct clk **clks;
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unsigned int i, plla_mult;
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int num_clks;
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u32 mode;
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if (rcar_rst_read_mode_pins(&mode))
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return;
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num_clks = of_property_count_strings(np, "clock-output-names");
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if (num_clks < 0) {
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pr_err("%s: failed to count clocks\n", __func__);
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return;
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}
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
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if (data == NULL || clks == NULL) {
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/* We're leaking memory on purpose, there's no point in cleaning
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* up as the system won't boot anyway.
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*/
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return;
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}
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data->clks = clks;
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data->clk_num = num_clks;
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config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
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plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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struct clk *clk;
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of_property_read_string_index(np, "clock-output-names", i,
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&name);
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clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);
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if (IS_ERR(clk))
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pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
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__func__, np, name, PTR_ERR(clk));
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else
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data->clks[i] = clk;
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, data);
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cpg_mstp_add_clk_domain(np);
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}
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CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
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r8a7779_cpg_clocks_init);
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