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OpenCloudOS-Kernel/arch/arm64/mm/fault.c

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Based on arch/arm/mm/fault.c
*
* Copyright (C) 1995 Linus Torvalds
* Copyright (C) 1995-2004 Russell King
* Copyright (C) 2012 ARM Ltd.
* Copyright (C) 2020 Ampere Computing LLC
*/
#include <linux/acpi.h>
#include <linux/bitfield.h>
#include <linux/extable.h>
#include <linux/kfence.h>
#include <linux/signal.h>
#include <linux/mm.h>
#include <linux/hardirq.h>
#include <linux/init.h>
#include <linux/kasan.h>
#include <linux/kprobes.h>
#include <linux/uaccess.h>
#include <linux/page-flags.h>
#include <linux/sched/signal.h>
#include <linux/sched/debug.h>
#include <linux/highmem.h>
#include <linux/perf_event.h>
#include <linux/preempt.h>
#include <linux/hugetlb.h>
#include <asm/acpi.h>
#include <asm/bug.h>
#include <asm/cmpxchg.h>
#include <asm/cpufeature.h>
#include <asm/efi.h>
#include <asm/exception.h>
#include <asm/daifflags.h>
#include <asm/debug-monitors.h>
#include <asm/esr.h>
#include <asm/kprobes.h>
#include <asm/mte.h>
#include <asm/patching.h>
#include <asm/processor.h>
#include <asm/sysreg.h>
#include <asm/system_misc.h>
#include <asm/tlbflush.h>
#include <asm/traps.h>
struct fault_info {
int (*fn)(unsigned long far, unsigned long esr,
struct pt_regs *regs);
int sig;
int code;
const char *name;
};
static const struct fault_info fault_info[];
static struct fault_info debug_fault_info[];
static inline const struct fault_info *esr_to_fault_info(unsigned long esr)
{
return fault_info + (esr & ESR_ELx_FSC);
}
static inline const struct fault_info *esr_to_debug_fault_info(unsigned long esr)
{
return debug_fault_info + DBG_ESR_EVT(esr);
}
static void data_abort_decode(unsigned long esr)
{
unsigned long iss2 = ESR_ELx_ISS2(esr);
pr_alert("Data abort info:\n");
if (esr & ESR_ELx_ISV) {
pr_alert(" Access size = %u byte(s)\n",
1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT));
pr_alert(" SSE = %lu, SRT = %lu\n",
(esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT,
(esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT);
pr_alert(" SF = %lu, AR = %lu\n",
(esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
(esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
} else {
pr_alert(" ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n",
esr & ESR_ELx_ISS_MASK, iss2);
}
pr_alert(" CM = %lu, WnR = %lu, TnD = %lu, TagAccess = %lu\n",
(esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT,
(esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT,
(iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT,
(iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT);
pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu, Xs = %llu\n",
(iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT,
(iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT,
(iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT,
(iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT);
}
static void mem_abort_decode(unsigned long esr)
{
pr_alert("Mem abort info:\n");
pr_alert(" ESR = 0x%016lx\n", esr);
pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n",
ESR_ELx_EC(esr), esr_get_class_string(esr),
(esr & ESR_ELx_IL) ? 32 : 16);
pr_alert(" SET = %lu, FnV = %lu\n",
(esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT,
(esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT);
pr_alert(" EA = %lu, S1PTW = %lu\n",
(esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT,
(esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT);
pr_alert(" FSC = 0x%02lx: %s\n", (esr & ESR_ELx_FSC),
esr_to_fault_info(esr)->name);
if (esr_is_data_abort(esr))
data_abort_decode(esr);
}
static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm)
{
/* Either init_pg_dir or swapper_pg_dir */
if (mm == &init_mm)
return __pa_symbol(mm->pgd);
return (unsigned long)virt_to_phys(mm->pgd);
}
/*
* Dump out the page tables associated with 'addr' in the currently active mm.
*/
static void show_pte(unsigned long addr)
{
struct mm_struct *mm;
pgd_t *pgdp;
pgd_t pgd;
if (is_ttbr0_addr(addr)) {
/* TTBR0 */
mm = current->active_mm;
if (mm == &init_mm) {
pr_alert("[%016lx] user address but active_mm is swapper\n",
addr);
return;
}
} else if (is_ttbr1_addr(addr)) {
/* TTBR1 */
mm = &init_mm;
} else {
pr_alert("[%016lx] address between user and kernel address ranges\n",
addr);
return;
}
pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n",
mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
vabits_actual, mm_to_pgd_phys(mm));
pgdp = pgd_offset(mm, addr);
pgd = READ_ONCE(*pgdp);
pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
do {
p4d_t *p4dp, p4d;
pud_t *pudp, pud;
pmd_t *pmdp, pmd;
pte_t *ptep, pte;
if (pgd_none(pgd) || pgd_bad(pgd))
break;
p4dp = p4d_offset(pgdp, addr);
p4d = READ_ONCE(*p4dp);
pr_cont(", p4d=%016llx", p4d_val(p4d));
if (p4d_none(p4d) || p4d_bad(p4d))
break;
pudp = pud_offset(p4dp, addr);
pud = READ_ONCE(*pudp);
pr_cont(", pud=%016llx", pud_val(pud));
if (pud_none(pud) || pud_bad(pud))
break;
pmdp = pmd_offset(pudp, addr);
pmd = READ_ONCE(*pmdp);
pr_cont(", pmd=%016llx", pmd_val(pmd));
if (pmd_none(pmd) || pmd_bad(pmd))
break;
ptep = pte_offset_map(pmdp, addr);
if (!ptep)
break;
pte = READ_ONCE(*ptep);
pr_cont(", pte=%016llx", pte_val(pte));
pte_unmap(ptep);
} while(0);
pr_cont("\n");
}
/*
* This function sets the access flags (dirty, accessed), as well as write
* permission, and only to a more permissive setting.
*
* It needs to cope with hardware update of the accessed/dirty state by other
* agents in the system and can safely skip the __sync_icache_dcache() call as,
* like set_pte_at(), the PTE is never changed from no-exec to exec here.
*
* Returns whether or not the PTE actually changed.
*/
int ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long address, pte_t *ptep,
pte_t entry, int dirty)
{
pteval_t old_pteval, pteval;
pte_t pte = READ_ONCE(*ptep);
if (pte_same(pte, entry))
return 0;
/* only preserve the access flags and write permission */
pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY;
/*
* Setting the flags must be done atomically to avoid racing with the
* hardware update of the access/dirty state. The PTE_RDONLY bit must
* be set to the most permissive (lowest value) of *ptep and entry
* (calculated as: a & b == ~(~a | ~b)).
*/
pte_val(entry) ^= PTE_RDONLY;
pteval = pte_val(pte);
do {
old_pteval = pteval;
pteval ^= PTE_RDONLY;
pteval |= pte_val(entry);
pteval ^= PTE_RDONLY;
pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);
} while (pteval != old_pteval);
/* Invalidate a stale read-only entry */
if (dirty)
flush_tlb_page(vma, address);
return 1;
}
static bool is_el1_instruction_abort(unsigned long esr)
{
return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR;
}
static bool is_el1_data_abort(unsigned long esr)
{
return ESR_ELx_EC(esr) == ESR_ELx_EC_DABT_CUR;
}
static inline bool is_el1_permission_fault(unsigned long addr, unsigned long esr,
struct pt_regs *regs)
{
unsigned long fsc_type = esr & ESR_ELx_FSC_TYPE;
if (!is_el1_data_abort(esr) && !is_el1_instruction_abort(esr))
return false;
if (fsc_type == ESR_ELx_FSC_PERM)
return true;
if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan())
return fsc_type == ESR_ELx_FSC_FAULT &&
(regs->pstate & PSR_PAN_BIT);
return false;
}
static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr,
unsigned long esr,
struct pt_regs *regs)
{
unsigned long flags;
u64 par, dfsc;
if (!is_el1_data_abort(esr) ||
(esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT)
return false;
local_irq_save(flags);
asm volatile("at s1e1r, %0" :: "r" (addr));
isb();
par = read_sysreg_par();
local_irq_restore(flags);
/*
* If we now have a valid translation, treat the translation fault as
* spurious.
*/
if (!(par & SYS_PAR_EL1_F))
return true;
/*
* If we got a different type of fault from the AT instruction,
* treat the translation fault as spurious.
*/
dfsc = FIELD_GET(SYS_PAR_EL1_FST, par);
return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT;
}
static void die_kernel_fault(const char *msg, unsigned long addr,
unsigned long esr, struct pt_regs *regs)
{
bust_spinlocks(1);
pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg,
addr);
kasan_non_canonical_hook(addr);
mem_abort_decode(esr);
show_pte(addr);
die("Oops", regs, esr);
bust_spinlocks(0);
make_task_dead(SIGKILL);
}
#ifdef CONFIG_KASAN_HW_TAGS
static void report_tag_fault(unsigned long addr, unsigned long esr,
struct pt_regs *regs)
{
/*
* SAS bits aren't set for all faults reported in EL1, so we can't
* find out access size.
*/
bool is_write = !!(esr & ESR_ELx_WNR);
kasan_report((void *)addr, 0, is_write, regs->pc);
}
#else
/* Tag faults aren't enabled without CONFIG_KASAN_HW_TAGS. */
static inline void report_tag_fault(unsigned long addr, unsigned long esr,
struct pt_regs *regs) { }
#endif
static void do_tag_recovery(unsigned long addr, unsigned long esr,
struct pt_regs *regs)
{
report_tag_fault(addr, esr, regs);
/*
* Disable MTE Tag Checking on the local CPU for the current EL.
* It will be done lazily on the other CPUs when they will hit a
* tag fault.
*/
sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK,
SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF, NONE));
isb();
}
static bool is_el1_mte_sync_tag_check_fault(unsigned long esr)
{
unsigned long fsc = esr & ESR_ELx_FSC;
if (!is_el1_data_abort(esr))
return false;
if (fsc == ESR_ELx_FSC_MTE)
return true;
return false;
}
static bool is_translation_fault(unsigned long esr)
{
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_FAULT;
}
static void __do_kernel_fault(unsigned long addr, unsigned long esr,
struct pt_regs *regs)
{
const char *msg;
/*
* Are we prepared to handle this kernel fault?
* We are almost certainly not prepared to handle instruction faults.
*/
if (!is_el1_instruction_abort(esr) && fixup_exception(regs))
return;
if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs),
"Ignoring spurious kernel translation fault at virtual address %016lx\n", addr))
return;
if (is_el1_mte_sync_tag_check_fault(esr)) {
do_tag_recovery(addr, esr, regs);
return;
}
if (is_el1_permission_fault(addr, esr, regs)) {
if (esr & ESR_ELx_WNR)
msg = "write to read-only memory";
else if (is_el1_instruction_abort(esr))
msg = "execute from non-executable memory";
else
msg = "read from unreadable memory";
} else if (addr < PAGE_SIZE) {
msg = "NULL pointer dereference";
} else {
if (is_translation_fault(esr) &&
kfence_handle_page_fault(addr, esr & ESR_ELx_WNR, regs))
return;
msg = "paging request";
}
if (efi_runtime_fixup_exception(regs, msg))
return;
die_kernel_fault(msg, addr, esr, regs);
}
static void set_thread_esr(unsigned long address, unsigned long esr)
{
current->thread.fault_address = address;
/*
* If the faulting address is in the kernel, we must sanitize the ESR.
* From userspace's point of view, kernel-only mappings don't exist
* at all, so we report them as level 0 translation faults.
* (This is not quite the way that "no mapping there at all" behaves:
* an alignment fault not caused by the memory type would take
* precedence over translation fault for a real access to empty
* space. Unfortunately we can't easily distinguish "alignment fault
* not caused by memory type" from "alignment fault caused by memory
* type", so we ignore this wrinkle and just return the translation
* fault.)
*/
if (!is_ttbr0_addr(current->thread.fault_address)) {
switch (ESR_ELx_EC(esr)) {
case ESR_ELx_EC_DABT_LOW:
/*
* These bits provide only information about the
* faulting instruction, which userspace knows already.
* We explicitly clear bits which are architecturally
* RES0 in case they are given meanings in future.
* We always report the ESR as if the fault was taken
* to EL1 and so ISV and the bits in ISS[23:14] are
* clear. (In fact it always will be a fault to EL1.)
*/
esr &= ESR_ELx_EC_MASK | ESR_ELx_IL |
ESR_ELx_CM | ESR_ELx_WNR;
esr |= ESR_ELx_FSC_FAULT;
break;
case ESR_ELx_EC_IABT_LOW:
/*
* Claim a level 0 translation fault.
* All other bits are architecturally RES0 for faults
* reported with that DFSC value, so we clear them.
*/
esr &= ESR_ELx_EC_MASK | ESR_ELx_IL;
esr |= ESR_ELx_FSC_FAULT;
break;
default:
/*
* This should never happen (entry.S only brings us
* into this code for insn and data aborts from a lower
* exception level). Fail safe by not providing an ESR
* context record at all.
*/
WARN(1, "ESR 0x%lx is not DABT or IABT from EL0\n", esr);
esr = 0;
break;
}
}
current->thread.fault_code = esr;
}
static void do_bad_area(unsigned long far, unsigned long esr,
struct pt_regs *regs)
{
unsigned long addr = untagged_addr(far);
/*
* If we are in kernel mode at this point, we have no context to
* handle this fault with.
*/
if (user_mode(regs)) {
const struct fault_info *inf = esr_to_fault_info(esr);
set_thread_esr(addr, esr);
arm64_force_sig_fault(inf->sig, inf->code, far, inf->name);
} else {
__do_kernel_fault(addr, esr, regs);
}
}
#define VM_FAULT_BADMAP ((__force vm_fault_t)0x010000)
#define VM_FAULT_BADACCESS ((__force vm_fault_t)0x020000)
static vm_fault_t __do_page_fault(struct mm_struct *mm,
struct vm_area_struct *vma, unsigned long addr,
unsigned int mm_flags, unsigned long vm_flags,
struct pt_regs *regs)
{
/*
* Ok, we have a good vm_area for this memory access, so we can handle
* it.
* Check that the permissions on the VMA allow for the fault which
* occurred.
*/
if (!(vma->vm_flags & vm_flags))
return VM_FAULT_BADACCESS;
return handle_mm_fault(vma, addr, mm_flags, regs);
}
static bool is_el0_instruction_abort(unsigned long esr)
{
return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW;
}
/*
* Note: not valid for EL1 DC IVAC, but we never use that such that it
* should fault. EL0 cannot issue DC IVAC (undef).
*/
static bool is_write_abort(unsigned long esr)
{
return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM);
}
static int __kprobes do_page_fault(unsigned long far, unsigned long esr,
struct pt_regs *regs)
{
const struct fault_info *inf;
struct mm_struct *mm = current->mm;
vm_fault_t fault;
unsigned long vm_flags;
unsigned int mm_flags = FAULT_FLAG_DEFAULT;
unsigned long addr = untagged_addr(far);
struct vm_area_struct *vma;
if (kprobe_page_fault(regs, esr))
return 0;
/*
* If we're in an interrupt or have no user context, we must not take
* the fault.
*/
if (faulthandler_disabled() || !mm)
goto no_context;
if (user_mode(regs))
mm_flags |= FAULT_FLAG_USER;
/*
* vm_flags tells us what bits we must have in vma->vm_flags
* for the fault to be benign, __do_page_fault() would check
* vma->vm_flags & vm_flags and returns an error if the
* intersection is empty
*/
if (is_el0_instruction_abort(esr)) {
/* It was exec fault */
vm_flags = VM_EXEC;
mm_flags |= FAULT_FLAG_INSTRUCTION;
} else if (is_write_abort(esr)) {
/* It was write fault */
vm_flags = VM_WRITE;
mm_flags |= FAULT_FLAG_WRITE;
} else {
/* It was read fault */
vm_flags = VM_READ;
/* Write implies read */
vm_flags |= VM_WRITE;
/* If EPAN is absent then exec implies read */
if (!cpus_have_const_cap(ARM64_HAS_EPAN))
vm_flags |= VM_EXEC;
}
if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) {
if (is_el1_instruction_abort(esr))
die_kernel_fault("execution of user memory",
addr, esr, regs);
if (!search_exception_tables(regs->pc))
die_kernel_fault("access to user memory outside uaccess routines",
addr, esr, regs);
}
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
if (!(mm_flags & FAULT_FLAG_USER))
goto lock_mmap;
vma = lock_vma_under_rcu(mm, addr);
if (!vma)
goto lock_mmap;
if (!(vma->vm_flags & vm_flags)) {
vma_end_read(vma);
goto lock_mmap;
}
fault = handle_mm_fault(vma, addr, mm_flags | FAULT_FLAG_VMA_LOCK, regs);
if (!(fault & (VM_FAULT_RETRY | VM_FAULT_COMPLETED)))
vma_end_read(vma);
if (!(fault & VM_FAULT_RETRY)) {
count_vm_vma_lock_event(VMA_LOCK_SUCCESS);
goto done;
}
count_vm_vma_lock_event(VMA_LOCK_RETRY);
/* Quick path to respond to signals */
if (fault_signal_pending(fault, regs)) {
if (!user_mode(regs))
goto no_context;
return 0;
}
lock_mmap:
retry:
vma = lock_mm_and_find_vma(mm, addr, regs);
if (unlikely(!vma)) {
fault = VM_FAULT_BADMAP;
goto done;
}
fault = __do_page_fault(mm, vma, addr, mm_flags, vm_flags, regs);
/* Quick path to respond to signals */
if (fault_signal_pending(fault, regs)) {
if (!user_mode(regs))
goto no_context;
return 0;
}
/* The fault is fully completed (including releasing mmap lock) */
if (fault & VM_FAULT_COMPLETED)
return 0;
if (fault & VM_FAULT_RETRY) {
mm_flags |= FAULT_FLAG_TRIED;
goto retry;
}
mmap_read_unlock(mm);
done:
/*
* Handle the "normal" (no error) case first.
*/
if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP |
VM_FAULT_BADACCESS))))
return 0;
/*
* If we are in kernel mode at this point, we have no context to
* handle this fault with.
*/
if (!user_mode(regs))
goto no_context;
if (fault & VM_FAULT_OOM) {
/*
* We ran out of memory, call the OOM killer, and return to
* userspace (which will retry the fault, or kill us if we got
* oom-killed).
*/
pagefault_out_of_memory();
return 0;
}
inf = esr_to_fault_info(esr);
set_thread_esr(addr, esr);
if (fault & VM_FAULT_SIGBUS) {
/*
* We had some memory, but were unable to successfully fix up
* this page fault.
*/
arm64_force_sig_fault(SIGBUS, BUS_ADRERR, far, inf->name);
} else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) {
unsigned int lsb;
lsb = PAGE_SHIFT;
if (fault & VM_FAULT_HWPOISON_LARGE)
lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
arm64_force_sig_mceerr(BUS_MCEERR_AR, far, lsb, inf->name);
} else {
/*
* Something tried to access memory that isn't in our memory
* map.
*/
arm64_force_sig_fault(SIGSEGV,
fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR,
far, inf->name);
}
return 0;
no_context:
__do_kernel_fault(addr, esr, regs);
return 0;
}
static int __kprobes do_translation_fault(unsigned long far,
unsigned long esr,
struct pt_regs *regs)
{
unsigned long addr = untagged_addr(far);
if (is_ttbr0_addr(addr))
return do_page_fault(far, esr, regs);
do_bad_area(far, esr, regs);
return 0;
}
static int copy_from_user_io(void *to, const void __user *from, unsigned long n)
{
const u8 __user *src = from;
u8 *dest = to;
for (; n; n--)
if (get_user(*dest++, src++))
break;
return n;
}
static int copy_to_user_io(void __user *to, const void *from, unsigned long n)
{
const u8 *src = from;
u8 __user *dest = to;
for (; n; n--)
if (put_user(*src++, dest++))
break;
return n;
}
static int align_load(unsigned long addr, int sz, u64 *out)
{
union {
u8 d8;
u16 d16;
u32 d32;
u64 d64;
char c[8];
} data;
if (sz != 1 && sz != 2 && sz != 4 && sz != 8)
return 1;
if (is_ttbr0_addr(addr)) {
if (copy_from_user_io(data.c, (const void __user *)addr, sz))
return 1;
} else
memcpy_fromio(data.c, (const void __iomem *)addr, sz);
switch (sz) {
case 1:
*out = data.d8;
break;
case 2:
*out = data.d16;
break;
case 4:
*out = data.d32;
break;
case 8:
*out = data.d64;
break;
default:
return 1;
}
return 0;
}
static int align_store(unsigned long addr, int sz, u64 val)
{
union {
u8 d8;
u16 d16;
u32 d32;
u64 d64;
char c[8];
} data;
switch (sz) {
case 1:
data.d8 = val;
break;
case 2:
data.d16 = val;
break;
case 4:
data.d32 = val;
break;
case 8:
data.d64 = val;
break;
default:
return 1;
}
if (is_ttbr0_addr(addr)) {
if (copy_to_user_io((void __user *)addr, data.c, sz))
return 1;
} else
memcpy_toio((void __iomem *)addr, data.c, sz);
return 0;
}
static int align_dc_zva(unsigned long addr, struct pt_regs *regs)
{
int bs = read_cpuid(DCZID_EL0) & 0xf;
int sz = 1 << (bs + 2);
addr &= ~(sz - 1);
if (is_ttbr0_addr(addr)) {
for (; sz; sz--) {
if (align_store(addr, 1, 0))
return 1;
}
} else
memset_io((void __iomem *)addr, 0, sz);
return 0;
}
static u64 get_vn_dt(int n, int t)
{
u64 res;
switch (n) {
#define V(n) \
case n: \
asm("cbnz %w1, 1f\n\t" \
"mov %0, v"#n".d[0]\n\t" \
"b 2f\n\t" \
"1: mov %0, v"#n".d[1]\n\t" \
"2:" : "=r" (res) : "r" (t)); \
break
V(0); V(1); V(2); V(3); V(4); V(5); V(6); V(7);
V(8); V(9); V(10); V(11); V(12); V(13); V(14); V(15);
V(16); V(17); V(18); V(19); V(20); V(21); V(22); V(23);
V(24); V(25); V(26); V(27); V(28); V(29); V(30); V(31);
#undef V
default:
res = 0;
break;
}
return res;
}
static void set_vn_dt(int n, int t, u64 val)
{
switch (n) {
#define V(n) \
case n: \
asm("cbnz %w1, 1f\n\t" \
"mov v"#n".d[0], %0\n\t" \
"b 2f\n\t" \
"1: mov v"#n".d[1], %0\n\t" \
"2:" :: "r" (val), "r" (t)); \
break
V(0); V(1); V(2); V(3); V(4); V(5); V(6); V(7);
V(8); V(9); V(10); V(11); V(12); V(13); V(14); V(15);
V(16); V(17); V(18); V(19); V(20); V(21); V(22); V(23);
V(24); V(25); V(26); V(27); V(28); V(29); V(30); V(31);
#undef V
default:
break;
}
}
static u64 replicate64(u64 val, int bits)
{
switch (bits) {
case 8:
val = (val << 8) | (val & 0xff);
fallthrough;
case 16:
val = (val << 16) | (val & 0xffff);
fallthrough;
case 32:
val = (val << 32) | (val & 0xffffffff);
break;
default:
break;
}
return val;
}
static u64 elem_get(u64 hi, u64 lo, int index, int esize)
{
int shift = index * esize;
u64 mask = GENMASK(esize - 1, 0);
if (shift < 64)
return (lo >> shift) & mask;
else
return (hi >> (shift - 64)) & mask;
}
static void elem_set(u64 *hi, u64 *lo, int index, int esize, u64 val)
{
int shift = index * esize;
u64 mask = GENMASK(esize - 1, 0);
if (shift < 64)
*lo = (*lo & ~(mask << shift)) | ((val & mask) << shift);
else
*hi = (*hi & ~(mask << (shift - 64))) | ((val & mask) << (shift - 64));
}
static int align_ldst_pair(u32 insn, struct pt_regs *regs)
{
const u32 OPC = GENMASK(31, 30);
const u32 L_MASK = BIT(22);
int opc = FIELD_GET(OPC, insn);
int L = FIELD_GET(L_MASK, insn);
bool wback = !!(insn & BIT(23));
bool postindex = !(insn & BIT(24));
int n = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
int t = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
int t2 = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2, insn);
bool is_store = !L;
bool is_signed = !!(opc & 1);
int scale = 2 + (opc >> 1);
int datasize = 8 << scale;
u64 uoffset = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_7, insn);
s64 offset = sign_extend64(uoffset, 6) << scale;
u64 address;
u64 data1, data2;
u64 dbytes;
if ((is_store && (opc & 1)) || opc == 3)
return 1;
if (wback && (t == n || t2 == n) && n != 31)
return 1;
if (!is_store && t == t2)
return 1;
dbytes = datasize / 8;
address = regs_get_register(regs, n << 3);
if (!postindex)
address += offset;
if (is_store) {
data1 = pt_regs_read_reg(regs, t);
data2 = pt_regs_read_reg(regs, t2);
if (align_store(address, dbytes, data1) ||
align_store(address + dbytes, dbytes, data2))
return 1;
} else {
if (align_load(address, dbytes, &data1) ||
align_load(address + dbytes, dbytes, &data2))
return 1;
if (is_signed) {
data1 = sign_extend64(data1, datasize - 1);
data2 = sign_extend64(data2, datasize - 1);
}
pt_regs_write_reg(regs, t, data1);
pt_regs_write_reg(regs, t2, data2);
}
if (wback) {
if (postindex)
address += offset;
if (n == 31)
regs->sp = address;
else
pt_regs_write_reg(regs, n, address);
}
return 0;
}
static int align_ldst_vector_single(u32 insn, struct pt_regs *regs)
{
const u32 Q_MASK = BIT(30);
const u32 L_MASK = BIT(22);
const u32 R_MASK = BIT(21);
const u32 OPCODE = GENMASK(15, 13);
const u32 S_MASK = BIT(12);
const u32 SIZE = GENMASK(11, 10);
u32 Q = FIELD_GET(Q_MASK, insn);
u32 L = FIELD_GET(L_MASK, insn);
u32 R = FIELD_GET(R_MASK, insn);
u32 opcode = FIELD_GET(OPCODE, insn);
u32 S = FIELD_GET(S_MASK, insn);
u32 size = FIELD_GET(SIZE, insn);
int t = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
int n = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
int m = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn);
bool wback = !!(insn & BIT(23));
int init_scale = opcode >> 1;
int scale = init_scale;
int selem = (((opcode & 1) << 1) | R) + 1;
bool replicate = false;
int index;
int datasize;
int esize;
u64 address;
u64 offs;
u64 rval_d0, rval_d1;
u64 element;
int ebytes;
int s;
u64 data;
switch (scale) {
case 3:
if (!L || S)
return 1;
scale = size;
replicate = true;
break;
case 0:
index = (Q << 3) | (S << 2) | size;
break;
case 1:
if (size & 1)
return 1;
index = (Q << 2) | (S << 1) | (size >> 1);
break;
case 2:
if (size & 2)
return 1;
if (!(size & 1))
index = (Q << 1) | S;
else {
if (S)
return 1;
index = Q;
scale = 3;
}
break;
}
datasize = Q ? 128 : 64;
esize = 8 << scale;
ebytes = esize / 8;
address = regs_get_register(regs, n << 3);
offs = 0;
if (replicate) {
for (s = 0; s < selem; s++) {
if (align_load(address + offs, ebytes, &element))
return 1;
data = replicate64(element, esize);
set_vn_dt(t, 0, data);
if (datasize == 128)
set_vn_dt(t, 1, data);
else
set_vn_dt(t, 1, 0);
offs += ebytes;
t = (t + 1) & 31;
}
} else {
for (s = 0; s < selem; s++) {
rval_d0 = get_vn_dt(t, 0);
rval_d1 = get_vn_dt(t, 1);
if (L) {
if (align_load(address + offs, ebytes, &data))
return 1;
elem_set(&rval_d1, &rval_d0, index, esize, data);
set_vn_dt(t, 0, rval_d0);
set_vn_dt(t, 1, rval_d1);
} else {
data = elem_get(rval_d1, rval_d0, index, esize);
if (align_store(address + offs, ebytes, data))
return 1;
}
offs += ebytes;
t = (t + 1) & 31;
}
}
if (wback) {
if (m != 31)
offs = regs_get_register(regs, m << 3);
if (n == 31)
regs->sp = address + offs;
else
pt_regs_write_reg(regs, n, address + offs);
}
return 0;
}
static int align_ldst_pair_simdfp(u32 insn, struct pt_regs *regs)
{
const u32 OPC = GENMASK(31, 30);
const u32 L_MASK = BIT(22);
int opc = FIELD_GET(OPC, insn);
int L = FIELD_GET(L_MASK, insn);
bool wback = !!(insn & BIT(23));
bool postindex = !(insn & BIT(24));
int n = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
int t = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
int t2 = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2, insn);
bool is_store = !L;
int scale = 2 + opc;
int datasize = 8 << scale;
u64 uoffset = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_7, insn);
s64 offset = sign_extend64(uoffset, 6) << scale;
u64 address;
u64 data1_d0, data1_d1, data2_d0, data2_d1;
u64 dbytes;
if (opc == 0x3)
return 1;
if (!is_store && t == t2)
return 1;
dbytes = datasize / 8;
address = regs_get_register(regs, n << 3);
if (!postindex)
address += offset;
if (is_store) {
data1_d0 = get_vn_dt(t, 0);
data2_d0 = get_vn_dt(t2, 0);
if (datasize == 128) {
data1_d1 = get_vn_dt(t, 1);
data2_d1 = get_vn_dt(t2, 1);
if (align_store(address, 8, data1_d0) ||
align_store(address + 8, 8, data1_d1) ||
align_store(address + 16, 8, data2_d0) ||
align_store(address + 24, 8, data2_d1))
return 1;
} else {
if (align_store(address, dbytes, data1_d0) ||
align_store(address + dbytes, dbytes, data2_d0))
return 1;
}
} else {
if (datasize == 128) {
if (align_load(address, 8, &data1_d0) ||
align_load(address + 8, 8, &data1_d1) ||
align_load(address + 16, 8, &data2_d0) ||
align_load(address + 24, 8, &data2_d1))
return 1;
} else {
if (align_load(address, dbytes, &data1_d0) ||
align_load(address + dbytes, dbytes, &data2_d0))
return 1;
data1_d1 = data2_d1 = 0;
}
set_vn_dt(t, 0, data1_d0);
set_vn_dt(t, 1, data1_d1);
set_vn_dt(t2, 0, data2_d0);
set_vn_dt(t2, 1, data2_d1);
}
if (wback) {
if (postindex)
address += offset;
if (n == 31)
regs->sp = address;
else
pt_regs_write_reg(regs, n, address);
}
return 0;
}
static int align_ldst_regoff(u32 insn, struct pt_regs *regs)
{
const u32 SIZE = GENMASK(31, 30);
const u32 OPC = GENMASK(23, 22);
const u32 OPTION = GENMASK(15, 13);
const u32 S = BIT(12);
u32 size = FIELD_GET(SIZE, insn);
u32 opc = FIELD_GET(OPC, insn);
u32 option = FIELD_GET(OPTION, insn);
u32 s = FIELD_GET(S, insn);
int scale = size;
int extend_len = (option & 0x1) ? 64 : 32;
bool extend_unsigned = !(option & 0x4);
int shift = s ? scale : 0;
int n = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
int t = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
int m = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn);
bool is_store;
bool is_signed;
int regsize;
int datasize;
u64 offset;
u64 address;
u64 data;
if ((opc & 0x2) == 0) {
/* store or zero-extending load */
is_store = !(opc & 0x1);
regsize = size == 0x3 ? 64 : 32;
is_signed = false;
} else {
if (size == 0x3) {
if ((opc & 0x1) == 0) {
/* prefetch */
return 0;
} else {
/* undefined */
return 1;
}
} else {
/* sign-extending load */
is_store = false;
if (size == 0x2 && (opc & 0x1) == 0x1) {
/* undefined */
return 1;
}
regsize = (opc & 0x1) == 0x1 ? 32 : 64;
is_signed = true;
}
}
datasize = 8 << scale;
if (n == t && n != 31)
return 1;
offset = pt_regs_read_reg(regs, m);
if (extend_len == 32) {
offset &= (u32)~0;
if (!extend_unsigned)
sign_extend64(offset, 31);
}
offset <<= shift;
address = regs_get_register(regs, n << 3) + offset;
if (is_store) {
data = pt_regs_read_reg(regs, t);
if (align_store(address, datasize / 8, data))
return 1;
} else {
if (align_load(address, datasize / 8, &data))
return 1;
if (is_signed) {
if (regsize == 32)
data = sign_extend32(data, datasize - 1);
else
data = sign_extend64(data, datasize - 1);
}
}
return 0;
}
static int align_ldst_regoff_simdfp(u32 insn, struct pt_regs *regs)
{
const u32 SIZE = GENMASK(31, 30);
const u32 OPC = GENMASK(23, 22);
const u32 OPTION = GENMASK(15, 13);
const u32 S = BIT(12);
u32 size = FIELD_GET(SIZE, insn);
u32 opc = FIELD_GET(OPC, insn);
u32 option = FIELD_GET(OPTION, insn);
u32 s = FIELD_GET(S, insn);
int scale = (opc & 0x2) << 1 | size;
int extend_len = (option & 0x1) ? 64 : 32;
bool extend_unsigned = !(option & 0x4);
int shift = s ? scale : 0;
int n = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
int t = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
int m = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn);
bool is_store = !(opc & BIT(0));
int datasize;
u64 offset;
u64 address;
u64 data_d0, data_d1;
if ((opc & 0x2) == 0)
return 1;
datasize = 8 << scale;
if (n == t && n != 31)
return 1;
offset = pt_regs_read_reg(regs, m);
if (extend_len == 32) {
offset &= (u32)~0;
if (!extend_unsigned)
sign_extend64(offset, 31);
}
offset <<= shift;
address = regs_get_register(regs, n << 3) + offset;
if (is_store) {
data_d0 = get_vn_dt(t, 0);
if (datasize == 128) {
data_d1 = get_vn_dt(t, 1);
if (align_store(address, 8, data_d0) ||
align_store(address + 8, 8, data_d1))
return 1;
} else {
if (align_store(address, datasize / 8, data_d0))
return 1;
}
} else {
if (datasize == 128) {
if (align_load(address, 8, &data_d0) ||
align_load(address + 8, 8, &data_d1))
return 1;
} else {
if (align_load(address, datasize / 8, &data_d0))
return 1;
data_d1 = 0;
}
set_vn_dt(t, 0, data_d0);
set_vn_dt(t, 1, data_d1);
}
return 0;
}
static int align_ldst_imm(u32 insn, struct pt_regs *regs)
{
const u32 SIZE = GENMASK(31, 30);
const u32 OPC = GENMASK(23, 22);
u32 size = FIELD_GET(SIZE, insn);
u32 opc = FIELD_GET(OPC, insn);
bool wback = !(insn & BIT(24)) && !!(insn & BIT(10));
bool postindex = wback && !(insn & BIT(11));
int scale = size;
u64 offset;
int n = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
int t = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
bool is_store;
bool is_signed;
int regsize;
int datasize;
u64 address;
u64 data;
if (!(insn & BIT(24))) {
u64 uoffset =
aarch64_insn_decode_immediate(AARCH64_INSN_IMM_9, insn);
offset = sign_extend64(uoffset, 8);
} else {
offset = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, insn);
offset <<= scale;
}
if ((opc & 0x2) == 0) {
/* store or zero-extending load */
is_store = !(opc & 0x1);
regsize = size == 0x3 ? 64 : 32;
is_signed = false;
} else {
if (size == 0x3) {
if (FIELD_GET(GENMASK(11, 10), insn) == 0 && (opc & 0x1) == 0) {
/* prefetch */
return 0;
} else {
/* undefined */
return 1;
}
} else {
/* sign-extending load */
is_store = false;
if (size == 0x2 && (opc & 0x1) == 0x1) {
/* undefined */
return 1;
}
regsize = (opc & 0x1) == 0x1 ? 32 : 64;
is_signed = true;
}
}
datasize = 8 << scale;
if (n == t && n != 31)
return 1;
address = regs_get_register(regs, n << 3);
if (!postindex)
address += offset;
if (is_store) {
data = pt_regs_read_reg(regs, t);
if (align_store(address, datasize / 8, data))
return 1;
} else {
if (align_load(address, datasize / 8, &data))
return 1;
if (is_signed) {
if (regsize == 32)
data = sign_extend32(data, datasize - 1);
else
data = sign_extend64(data, datasize - 1);
}
pt_regs_write_reg(regs, t, data);
}
if (wback) {
if (postindex)
address += offset;
if (n == 31)
regs->sp = address;
else
pt_regs_write_reg(regs, n, address);
}
return 0;
}
static int align_ldst_imm_simdfp(u32 insn, struct pt_regs *regs)
{
const u32 SIZE = GENMASK(31, 30);
const u32 OPC = GENMASK(23, 22);
u32 size = FIELD_GET(SIZE, insn);
u32 opc = FIELD_GET(OPC, insn);
bool wback = !(insn & BIT(24)) && !!(insn & BIT(10));
bool postindex = wback && !(insn & BIT(11));
int scale = (opc & 0x2) << 1 | size;
u64 offset;
int n = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
int t = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
bool is_store = !(opc & BIT(0)) ;
int datasize;
u64 address;
u64 data_d0, data_d1;
if (scale > 4)
return 1;
if (!(insn & BIT(24))) {
u64 uoffset =
aarch64_insn_decode_immediate(AARCH64_INSN_IMM_9, insn);
offset = sign_extend64(uoffset, 8);
} else {
offset = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, insn);
offset <<= scale;
}
datasize = 8 << scale;
address = regs_get_register(regs, n << 3);
if (!postindex)
address += offset;
if (is_store) {
data_d0 = get_vn_dt(t, 0);
if (datasize == 128) {
data_d1 = get_vn_dt(t, 1);
if (align_store(address, 8, data_d0) ||
align_store(address + 8, 8, data_d1))
return 1;
} else {
if (align_store(address, datasize / 8, data_d0))
return 1;
}
} else {
if (datasize == 128) {
if (align_load(address, 8, &data_d0) ||
align_load(address + 8, 8, &data_d1))
return 1;
} else {
if (align_load(address, datasize / 8, &data_d0))
return 1;
data_d1 = 0;
}
set_vn_dt(t, 0, data_d0);
set_vn_dt(t, 1, data_d1);
}
if (wback) {
if (postindex)
address += offset;
if (n == 31)
regs->sp = address;
else
pt_regs_write_reg(regs, n, address);
}
return 0;
}
static int align_ldst(u32 insn, struct pt_regs *regs)
{
const u32 op0 = FIELD_GET(GENMASK(31, 28), insn);
const u32 op1 = FIELD_GET(BIT(26), insn);
const u32 op2 = FIELD_GET(GENMASK(24, 23), insn);
const u32 op3 = FIELD_GET(GENMASK(21, 16), insn);
const u32 op4 = FIELD_GET(GENMASK(11, 10), insn);
if ((op0 & 0x3) == 0x2) {
/*
* |------+-----+-----+-----+-----+-----------------------------------------|
* | op0 | op1 | op2 | op3 | op4 | Decode group |
* |------+-----+-----+-----+-----+-----------------------------------------|
* | xx10 | - | 00 | - | - | Load/store no-allocate pair (offset) |
* | xx10 | - | 01 | - | - | Load/store register pair (post-indexed) |
* | xx10 | - | 10 | - | - | Load/store register pair (offset) |
* | xx10 | - | 11 | - | - | Load/store register pair (pre-indexed) |
* |------+-----+-----+-----+-----+-----------------------------------------|
*/
if (op1 == 0) { /* V == 0 */
/* general */
return align_ldst_pair(insn, regs);
} else {
/* simdfp */
return align_ldst_pair_simdfp(insn, regs);
}
} else if ((op0 & 0x3) == 0x3 &&
(((op2 & 0x2) == 0 && (op3 & 0x20) == 0 && op4 != 0x2) ||
((op2 & 0x2) == 0x2))) {
/*
* |------+-----+-----+--------+-----+----------------------------------------------|
* | op0 | op1 | op2 | op3 | op4 | Decode group |
* |------+-----+-----+--------+-----+----------------------------------------------|
* | xx11 | - | 0x | 0xxxxx | 00 | Load/store register (unscaled immediate) |
* | xx11 | - | 0x | 0xxxxx | 01 | Load/store register (immediate post-indexed) |
* | xx11 | - | 0x | 0xxxxx | 11 | Load/store register (immediate pre-indexed) |
* | xx11 | - | 1x | - | - | Load/store register (unsigned immediate) |
* |------+-----+-----+--------+-----+----------------------------------------------|
*/
if (op1 == 0) { /* V == 0 */
/* general */
return align_ldst_imm(insn, regs);
} else {
/* simdfp */
return align_ldst_imm_simdfp(insn, regs);
}
} else if ((op0 & 0x3) == 0x3 && (op2 & 0x2) == 0 &&
(op3 & 0x20) == 0x20 && op4 == 0x2) {
/*
* |------+-----+-----+--------+-----+---------------------------------------|
* | op0 | op1 | op2 | op3 | op4 | |
* |------+-----+-----+--------+-----+---------------------------------------|
* | xx11 | - | 0x | 1xxxxx | 10 | Load/store register (register offset) |
* |------+-----+-----+--------+-----+---------------------------------------|
*/
if (op1 == 0) { /* V == 0 */
/* general */
return align_ldst_regoff(insn, regs);
} else {
/* simdfp */
return align_ldst_regoff_simdfp(insn, regs);
}
} else if ((op0 & 0xb) == 0 && op1 == 1 &&
((op2 == 2 && ((op3 & 0x1f) == 0)) || op2 == 3)) {
/*
* |------+-----+-----+--------+-----+-------------------------------------------|
* | op0 | op1 | op2 | op3 | op4 | |
* |------+-----+-----+--------+-----+-------------------------------------------|
* | 0x00 | 1 | 10 | x00000 | - | Advanced SIMD load/store single structure |
* | 0x00 | 1 | 11 | - | - | Advanced SIMD load/store single structure |
* | | | | | | (post-indexed) |
* |------+-----+-----+--------+-----+-------------------------------------------|
*/
return align_ldst_vector_single(insn, regs);
} else
return 1;
}
enum aarch64_insn_encoding_class {
AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
AARCH64_INSN_CLS_SVE, /* SVE instructions */
AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
AARCH64_INSN_CLS_LDST, /* Loads and stores */
AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
system instructions */
};
static const int aarch64_insn_encoding_class[] = {
AARCH64_INSN_CLS_UNKNOWN,
AARCH64_INSN_CLS_UNKNOWN,
AARCH64_INSN_CLS_SVE,
AARCH64_INSN_CLS_UNKNOWN,
AARCH64_INSN_CLS_LDST,
AARCH64_INSN_CLS_DP_REG,
AARCH64_INSN_CLS_LDST,
AARCH64_INSN_CLS_DP_FPSIMD,
AARCH64_INSN_CLS_DP_IMM,
AARCH64_INSN_CLS_DP_IMM,
AARCH64_INSN_CLS_BR_SYS,
AARCH64_INSN_CLS_BR_SYS,
AARCH64_INSN_CLS_LDST,
AARCH64_INSN_CLS_DP_REG,
AARCH64_INSN_CLS_LDST,
AARCH64_INSN_CLS_DP_FPSIMD,
};
enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
{
return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
}
#include "pcie_unalign_access.c"
static int fixup_alignment(unsigned long addr, unsigned int esr,
struct pt_regs *regs)
{
u32 insn;
int res;
struct pt_regs t = *regs;
int type;
if (user_mode(regs)) {
__le32 insn_le;
if (!is_ttbr0_addr(addr))
return 1;
if (get_user(insn_le,
(__le32 __user *)instruction_pointer(regs)))
return 1;
insn = le32_to_cpu(insn_le);
} else {
if (aarch64_insn_read((void *)instruction_pointer(regs), &insn))
return 1;
}
pr_debug("start to handle insn:%x\n", insn);
type = aarch64_get_insn_class(insn);
switch (type) {
case AARCH64_INSN_CLS_BR_SYS:
if (aarch64_insn_is_dc_zva(insn))
res = align_dc_zva(addr, regs);
else
res = 1;
break;
case AARCH64_INSN_CLS_LDST:
res = align_ldst(insn, regs);
if (res) {
/* Try it again, copy back if we succeed */
res = align_ldst_new(insn, &t);
if (!res)
*regs = t;
}
break;
default:
res = 1;
}
if (!res) {
instruction_pointer_set(regs, instruction_pointer(regs) + 4);
} else {
pr_err("cannot handle insn:%x, type:%d\n", insn, type);
dump_stack();
}
return res;
}
static int do_alignment_fault(unsigned long far, unsigned long esr,
struct pt_regs *regs)
{
if (IS_ENABLED(CONFIG_COMPAT_ALIGNMENT_FIXUPS) &&
compat_user_mode(regs))
return do_compat_alignment_fixup(far, regs);
#ifdef CONFIG_ALTRA_ERRATUM_82288
if (!fixup_alignment(far, esr, regs))
return 0;
#endif
do_bad_area(far, esr, regs);
return 0;
}
static int do_bad(unsigned long far, unsigned long esr, struct pt_regs *regs)
{
return 1; /* "fault" */
}
static int do_sea(unsigned long far, unsigned long esr, struct pt_regs *regs)
{
const struct fault_info *inf;
unsigned long siaddr;
inf = esr_to_fault_info(esr);
if (user_mode(regs) && apei_claim_sea(regs) == 0) {
/*
* APEI claimed this as a firmware-first notification.
* Some processing deferred to task_work before ret_to_user().
*/
return 0;
}
if (esr & ESR_ELx_FnV) {
siaddr = 0;
} else {
/*
* The architecture specifies that the tag bits of FAR_EL1 are
* UNKNOWN for synchronous external aborts. Mask them out now
* so that userspace doesn't see them.
*/
siaddr = untagged_addr(far);
}
arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr);
return 0;
}
static int do_tag_check_fault(unsigned long far, unsigned long esr,
struct pt_regs *regs)
{
/*
* The architecture specifies that bits 63:60 of FAR_EL1 are UNKNOWN
* for tag check faults. Set them to corresponding bits in the untagged
* address.
*/
far = (__untagged_addr(far) & ~MTE_TAG_MASK) | (far & MTE_TAG_MASK);
do_bad_area(far, esr, regs);
return 0;
}
static const struct fault_info fault_info[] = {
{ do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" },
{ do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" },
{ do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" },
{ do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 8" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 12" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
{ do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" },
{ do_tag_check_fault, SIGSEGV, SEGV_MTESERR, "synchronous tag check fault" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 18" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 19" },
{ do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" },
{ do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" },
{ do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" },
{ do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" },
{ do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented
{ do_bad, SIGKILL, SI_KERNEL, "unknown 25" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 26" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 27" },
{ do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
{ do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
{ do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
{ do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
{ do_bad, SIGKILL, SI_KERNEL, "unknown 32" },
{ do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 34" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 35" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 36" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 37" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 38" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 39" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 40" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 41" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 42" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 43" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 44" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 45" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 46" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 47" },
{ do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" },
{ do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 50" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 51" },
{ do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" },
{ do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 54" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 55" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 56" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 57" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 58" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 59" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 60" },
{ do_bad, SIGKILL, SI_KERNEL, "section domain fault" },
{ do_bad, SIGKILL, SI_KERNEL, "page domain fault" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 63" },
};
void do_mem_abort(unsigned long far, unsigned long esr, struct pt_regs *regs)
{
const struct fault_info *inf = esr_to_fault_info(esr);
unsigned long addr = untagged_addr(far);
if (!inf->fn(far, esr, regs))
return;
if (!user_mode(regs))
die_kernel_fault(inf->name, addr, esr, regs);
/*
* At this point we have an unrecognized fault type whose tag bits may
* have been defined as UNKNOWN. Therefore we only expose the untagged
* address to the signal handler.
*/
arm64_notify_die(inf->name, regs, inf->sig, inf->code, addr, esr);
}
NOKPROBE_SYMBOL(do_mem_abort);
void do_sp_pc_abort(unsigned long addr, unsigned long esr, struct pt_regs *regs)
{
arm64_notify_die("SP/PC alignment exception", regs, SIGBUS, BUS_ADRALN,
addr, esr);
}
NOKPROBE_SYMBOL(do_sp_pc_abort);
/*
* __refdata because early_brk64 is __init, but the reference to it is
* clobbered at arch_initcall time.
* See traps.c and debug-monitors.c:debug_traps_init().
*/
static struct fault_info __refdata debug_fault_info[] = {
{ do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" },
{ do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" },
{ do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 3" },
{ do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" },
{ do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" },
{ early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" },
{ do_bad, SIGKILL, SI_KERNEL, "unknown 7" },
};
void __init hook_debug_fault_code(int nr,
int (*fn)(unsigned long, unsigned long, struct pt_regs *),
int sig, int code, const char *name)
{
BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info));
debug_fault_info[nr].fn = fn;
debug_fault_info[nr].sig = sig;
debug_fault_info[nr].code = code;
debug_fault_info[nr].name = name;
}
/*
* In debug exception context, we explicitly disable preemption despite
* having interrupts disabled.
* This serves two purposes: it makes it much less likely that we would
* accidentally schedule in exception context and it will force a warning
* if we somehow manage to schedule by accident.
*/
static void debug_exception_enter(struct pt_regs *regs)
{
preempt_disable();
/* This code is a bit fragile. Test it. */
RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work");
}
NOKPROBE_SYMBOL(debug_exception_enter);
static void debug_exception_exit(struct pt_regs *regs)
{
preempt_enable_no_resched();
}
NOKPROBE_SYMBOL(debug_exception_exit);
void do_debug_exception(unsigned long addr_if_watchpoint, unsigned long esr,
struct pt_regs *regs)
{
const struct fault_info *inf = esr_to_debug_fault_info(esr);
unsigned long pc = instruction_pointer(regs);
debug_exception_enter(regs);
if (user_mode(regs) && !is_ttbr0_addr(pc))
arm64_apply_bp_hardening();
if (inf->fn(addr_if_watchpoint, esr, regs)) {
arm64_notify_die(inf->name, regs, inf->sig, inf->code, pc, esr);
}
debug_exception_exit(regs);
}
NOKPROBE_SYMBOL(do_debug_exception);
/*
* Used during anonymous page fault handling.
*/
struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma,
unsigned long vaddr)
{
gfp_t flags = GFP_HIGHUSER_MOVABLE | __GFP_ZERO;
/*
* If the page is mapped with PROT_MTE, initialise the tags at the
* point of allocation and page zeroing as this is usually faster than
* separate DC ZVA and STGM.
*/
if (vma->vm_flags & VM_MTE)
flags |= __GFP_ZEROTAGS;
return vma_alloc_folio(flags, 0, vma, vaddr, false);
}
void tag_clear_highpage(struct page *page)
{
/* Newly allocated page, shouldn't have been tagged yet */
WARN_ON_ONCE(!try_page_mte_tagging(page));
mte_zero_clear_page_tags(page_address(page));
set_page_mte_tagged(page);
}
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