59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ALSA SoC PCM Driver
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*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*/
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#include "chip_offset_byte.h"
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#define ACP3x_PHY_BASE_ADDRESS 0x1240000
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#define ACP3x_I2S_MODE 0
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#define ACP3x_REG_START 0x1240000
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#define ACP3x_REG_END 0x1250200
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#define I2S_MODE 0x04
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#define BT_TX_THRESHOLD 26
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#define BT_RX_THRESHOLD 25
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#define ACP3x_POWER_ON 0x00
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#define ACP3x_POWER_ON_IN_PROGRESS 0x01
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#define ACP3x_POWER_OFF 0x02
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#define ACP3x_POWER_OFF_IN_PROGRESS 0x03
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#define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001
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#define ACP_SRAM_PTE_OFFSET 0x02050000
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define MEM_WINDOW_START 0x4000000
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#define PLAYBACK_FIFO_ADDR_OFFSET 0x400
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#define CAPTURE_FIFO_ADDR_OFFSET 0x500
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#define PLAYBACK_MIN_NUM_PERIODS 2
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#define PLAYBACK_MAX_NUM_PERIODS 8
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#define PLAYBACK_MAX_PERIOD_SIZE 16384
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#define PLAYBACK_MIN_PERIOD_SIZE 4096
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#define CAPTURE_MIN_NUM_PERIODS 2
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#define CAPTURE_MAX_NUM_PERIODS 8
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#define CAPTURE_MAX_PERIOD_SIZE 16384
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#define CAPTURE_MIN_PERIOD_SIZE 4096
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#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
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#define MIN_BUFFER MAX_BUFFER
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#define FIFO_SIZE 0x100
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#define DMA_SIZE 0x40
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#define FRM_LEN 0x100
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#define SLOT_WIDTH_8 0x08
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#define SLOT_WIDTH_16 0x10
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#define SLOT_WIDTH_24 0x18
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#define SLOT_WIDTH_32 0x20
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static inline u32 rv_readl(void __iomem *base_addr)
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{
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return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);
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}
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static inline void rv_writel(u32 val, void __iomem *base_addr)
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{
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writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);
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}
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