453 lines
12 KiB
C
453 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* arch-independent dma-mapping routines
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*
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* Copyright (c) 2006 SUSE Linux Products GmbH
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* Copyright (c) 2006 Tejun Heo <teheo@suse.de>
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*/
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#include <linux/memblock.h> /* for max_pfn */
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#include <linux/acpi.h>
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#include <linux/dma-direct.h>
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#include <linux/dma-noncoherent.h>
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#include <linux/export.h>
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#include <linux/gfp.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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/*
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* Managed DMA API
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*/
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struct dma_devres {
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size_t size;
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void *vaddr;
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dma_addr_t dma_handle;
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unsigned long attrs;
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};
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static void dmam_release(struct device *dev, void *res)
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{
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struct dma_devres *this = res;
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dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle,
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this->attrs);
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}
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static int dmam_match(struct device *dev, void *res, void *match_data)
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{
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struct dma_devres *this = res, *match = match_data;
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if (this->vaddr == match->vaddr) {
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WARN_ON(this->size != match->size ||
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this->dma_handle != match->dma_handle);
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return 1;
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}
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return 0;
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}
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/**
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* dmam_free_coherent - Managed dma_free_coherent()
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* @dev: Device to free coherent memory for
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* @size: Size of allocation
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* @vaddr: Virtual address of the memory to free
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* @dma_handle: DMA handle of the memory to free
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*
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* Managed dma_free_coherent().
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*/
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void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle)
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{
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struct dma_devres match_data = { size, vaddr, dma_handle };
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dma_free_coherent(dev, size, vaddr, dma_handle);
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WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data));
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}
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EXPORT_SYMBOL(dmam_free_coherent);
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/**
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* dmam_alloc_attrs - Managed dma_alloc_attrs()
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* @dev: Device to allocate non_coherent memory for
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* @size: Size of allocation
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* @dma_handle: Out argument for allocated DMA handle
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* @gfp: Allocation flags
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* @attrs: Flags in the DMA_ATTR_* namespace.
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*
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* Managed dma_alloc_attrs(). Memory allocated using this function will be
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* automatically released on driver detach.
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*
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* RETURNS:
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* Pointer to allocated memory on success, NULL on failure.
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*/
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void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp, unsigned long attrs)
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{
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struct dma_devres *dr;
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void *vaddr;
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dr = devres_alloc(dmam_release, sizeof(*dr), gfp);
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if (!dr)
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return NULL;
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vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs);
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if (!vaddr) {
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devres_free(dr);
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return NULL;
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}
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dr->vaddr = vaddr;
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dr->dma_handle = *dma_handle;
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dr->size = size;
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dr->attrs = attrs;
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devres_add(dev, dr);
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return vaddr;
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}
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EXPORT_SYMBOL(dmam_alloc_attrs);
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/*
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* Create scatter-list for the already allocated DMA buffer.
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*/
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int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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struct page *page;
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int ret;
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if (!dev_is_dma_coherent(dev)) {
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unsigned long pfn;
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if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
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return -ENXIO;
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/* If the PFN is not valid, we do not have a struct page */
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pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr);
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if (!pfn_valid(pfn))
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return -ENXIO;
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page = pfn_to_page(pfn);
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} else {
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page = virt_to_page(cpu_addr);
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}
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ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
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if (!ret)
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sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
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return ret;
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}
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/*
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* The whole dma_get_sgtable() idea is fundamentally unsafe - it seems
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* that the intention is to allow exporting memory allocated via the
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* coherent DMA APIs through the dma_buf API, which only accepts a
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* scattertable. This presents a couple of problems:
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* 1. Not all memory allocated via the coherent DMA APIs is backed by
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* a struct page
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* 2. Passing coherent DMA memory into the streaming APIs is not allowed
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* as we will try to flush the memory through a different alias to that
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* actually being used (and the flushes are redundant.)
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*/
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int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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if (dma_is_direct(ops))
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return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr,
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size, attrs);
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if (!ops->get_sgtable)
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return -ENXIO;
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return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, attrs);
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}
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EXPORT_SYMBOL(dma_get_sgtable_attrs);
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#ifdef CONFIG_MMU
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/*
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* Return the page attributes used for mapping dma_alloc_* memory, either in
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* kernel space if remapping is needed, or to userspace through dma_mmap_*.
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*/
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pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs)
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{
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if (force_dma_unencrypted(dev))
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prot = pgprot_decrypted(prot);
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if (dev_is_dma_coherent(dev) ||
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(IS_ENABLED(CONFIG_DMA_NONCOHERENT_CACHE_SYNC) &&
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(attrs & DMA_ATTR_NON_CONSISTENT)))
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return prot;
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#ifdef CONFIG_ARCH_HAS_DMA_WRITE_COMBINE
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if (attrs & DMA_ATTR_WRITE_COMBINE)
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return pgprot_writecombine(prot);
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#endif
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return pgprot_dmacoherent(prot);
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}
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#endif /* CONFIG_MMU */
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/*
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* Create userspace mapping for the DMA-coherent memory.
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*/
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int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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#ifdef CONFIG_MMU
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unsigned long user_count = vma_pages(vma);
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unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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unsigned long off = vma->vm_pgoff;
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unsigned long pfn;
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int ret = -ENXIO;
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vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
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if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
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return ret;
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if (off >= count || user_count > count - off)
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return -ENXIO;
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if (!dev_is_dma_coherent(dev)) {
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if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
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return -ENXIO;
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/* If the PFN is not valid, we do not have a struct page */
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pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr);
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if (!pfn_valid(pfn))
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return -ENXIO;
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} else {
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pfn = page_to_pfn(virt_to_page(cpu_addr));
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}
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return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
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user_count << PAGE_SHIFT, vma->vm_page_prot);
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#else
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return -ENXIO;
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#endif /* CONFIG_MMU */
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}
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/**
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* dma_can_mmap - check if a given device supports dma_mmap_*
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* @dev: device to check
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*
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* Returns %true if @dev supports dma_mmap_coherent() and dma_mmap_attrs() to
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* map DMA allocations to userspace.
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*/
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bool dma_can_mmap(struct device *dev)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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if (dma_is_direct(ops)) {
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return IS_ENABLED(CONFIG_MMU) &&
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(dev_is_dma_coherent(dev) ||
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IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN));
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}
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return ops->mmap != NULL;
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}
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EXPORT_SYMBOL_GPL(dma_can_mmap);
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/**
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* dma_mmap_attrs - map a coherent DMA allocation into user space
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @vma: vm_area_struct describing requested user mapping
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* @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs
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* @dma_addr: device-view address returned from dma_alloc_attrs
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* @size: size of memory originally requested in dma_alloc_attrs
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* @attrs: attributes of mapping properties requested in dma_alloc_attrs
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*
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* Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user
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* space. The coherent DMA buffer must not be freed by the driver until the
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* user space mapping has been released.
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*/
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int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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if (dma_is_direct(ops))
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return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size,
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attrs);
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if (!ops->mmap)
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return -ENXIO;
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return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
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}
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EXPORT_SYMBOL(dma_mmap_attrs);
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u64 dma_get_required_mask(struct device *dev)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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if (dma_is_direct(ops))
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return dma_direct_get_required_mask(dev);
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if (ops->get_required_mask)
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return ops->get_required_mask(dev);
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/*
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* We require every DMA ops implementation to at least support a 32-bit
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* DMA mask (and use bounce buffering if that isn't supported in
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* hardware). As the direct mapping code has its own routine to
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* actually report an optimal mask we default to 32-bit here as that
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* is the right thing for most IOMMUs, and at least not actively
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* harmful in general.
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*/
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return DMA_BIT_MASK(32);
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}
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EXPORT_SYMBOL_GPL(dma_get_required_mask);
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void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t flag, unsigned long attrs)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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void *cpu_addr;
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WARN_ON_ONCE(!dev->coherent_dma_mask);
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if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr))
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return cpu_addr;
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/* let the implementation decide on the zone to allocate from: */
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flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
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if (dma_is_direct(ops))
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cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);
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else if (ops->alloc)
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cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
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else
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return NULL;
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debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
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return cpu_addr;
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}
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EXPORT_SYMBOL(dma_alloc_attrs);
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void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr))
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return;
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/*
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* On non-coherent platforms which implement DMA-coherent buffers via
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* non-cacheable remaps, ops->free() may call vunmap(). Thus getting
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* this far in IRQ context is a) at risk of a BUG_ON() or trying to
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* sleep on some machines, and b) an indication that the driver is
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* probably misusing the coherent API anyway.
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*/
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WARN_ON(irqs_disabled());
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if (!cpu_addr)
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return;
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debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
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if (dma_is_direct(ops))
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dma_direct_free(dev, size, cpu_addr, dma_handle, attrs);
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else if (ops->free)
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ops->free(dev, size, cpu_addr, dma_handle, attrs);
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}
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EXPORT_SYMBOL(dma_free_attrs);
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int dma_supported(struct device *dev, u64 mask)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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if (dma_is_direct(ops))
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return dma_direct_supported(dev, mask);
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if (!ops->dma_supported)
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return 1;
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return ops->dma_supported(dev, mask);
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}
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EXPORT_SYMBOL(dma_supported);
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#ifdef CONFIG_ARCH_HAS_DMA_SET_MASK
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void arch_dma_set_mask(struct device *dev, u64 mask);
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#else
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#define arch_dma_set_mask(dev, mask) do { } while (0)
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#endif
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int dma_set_mask(struct device *dev, u64 mask)
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{
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/*
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* Truncate the mask to the actually supported dma_addr_t width to
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* avoid generating unsupportable addresses.
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*/
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mask = (dma_addr_t)mask;
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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arch_dma_set_mask(dev, mask);
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*dev->dma_mask = mask;
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return 0;
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}
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EXPORT_SYMBOL(dma_set_mask);
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#ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
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int dma_set_coherent_mask(struct device *dev, u64 mask)
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{
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/*
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* Truncate the mask to the actually supported dma_addr_t width to
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* avoid generating unsupportable addresses.
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*/
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mask = (dma_addr_t)mask;
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if (!dma_supported(dev, mask))
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return -EIO;
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dev->coherent_dma_mask = mask;
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return 0;
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}
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EXPORT_SYMBOL(dma_set_coherent_mask);
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#endif
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void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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BUG_ON(!valid_dma_direction(dir));
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if (dma_is_direct(ops))
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arch_dma_cache_sync(dev, vaddr, size, dir);
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else if (ops->cache_sync)
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ops->cache_sync(dev, vaddr, size, dir);
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}
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EXPORT_SYMBOL(dma_cache_sync);
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size_t dma_max_mapping_size(struct device *dev)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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size_t size = SIZE_MAX;
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if (dma_is_direct(ops))
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size = dma_direct_max_mapping_size(dev);
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else if (ops && ops->max_mapping_size)
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size = ops->max_mapping_size(dev);
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return size;
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}
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EXPORT_SYMBOL_GPL(dma_max_mapping_size);
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size_t dma_opt_mapping_size(struct device *dev)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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size_t size = SIZE_MAX;
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if (ops && ops->opt_mapping_size)
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size = ops->opt_mapping_size();
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return min(dma_max_mapping_size(dev), size);
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}
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EXPORT_SYMBOL_GPL(dma_opt_mapping_size);
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unsigned long dma_get_merge_boundary(struct device *dev)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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if (!ops || !ops->get_merge_boundary)
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return 0; /* can't merge */
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return ops->get_merge_boundary(dev);
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}
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EXPORT_SYMBOL_GPL(dma_get_merge_boundary);
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