197 lines
5.2 KiB
C
197 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* valkyriefb.h: Constants of all sorts for valkyriefb
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*
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* Created 8 August 1998 by
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* Martin Costabel <costabel@wanadoo.fr> and Kevin Schoedel
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*
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* Vmode-switching changes and vmode 15/17 modifications created 29 August
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* 1998 by Barry K. Nathan <barryn@pobox.com>.
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*
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* vmode 10 changed by Steven Borley <sjb@salix.demon.co.uk>, 14 mai 2000
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*
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* Ported to 68k Macintosh by David Huggins-Daines <dhd@debian.org>
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*
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* Based directly on:
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*
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* controlfb.h: Constants of all sorts for controlfb
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* Copyright (C) 1998 Daniel Jacobowitz <dan@debian.org>
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*
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* pmc-valkyrie.h: Console support for PowerMac "control" display adaptor.
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* Copyright (C) 1997 Paul Mackerras.
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*
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* pmc-valkyrie.c: Console support for PowerMac "control" display adaptor.
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* Copyright (C) 1997 Paul Mackerras.
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*
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* and indirectly from:
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*
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* pmc-control.h: Console support for PowerMac "control" display adaptor.
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* Copyright (C) 1997 Paul Mackerras.
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*
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* pmc-control.c: Console support for PowerMac "control" display adaptor.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* platinumfb.c: Console support for PowerMac "platinum" display adaptor.
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* Copyright (C) 1998 Jon Howell
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*/
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#ifdef CONFIG_MAC
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/* Valkyrie registers are word-aligned on m68k */
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#define VALKYRIE_REG_PADSIZE 3
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#else
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#define VALKYRIE_REG_PADSIZE 7
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#endif
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/*
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* Structure of the registers for the Valkyrie colormap registers.
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*/
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struct cmap_regs {
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unsigned char addr;
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char pad1[VALKYRIE_REG_PADSIZE];
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unsigned char lut;
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};
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/*
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* Structure of the registers for the "valkyrie" display adaptor.
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*/
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struct vpreg { /* padded register */
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unsigned char r;
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char pad[VALKYRIE_REG_PADSIZE];
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};
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struct valkyrie_regs {
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struct vpreg mode;
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struct vpreg depth;
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struct vpreg status;
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struct vpreg reg3;
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struct vpreg intr;
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struct vpreg reg5;
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struct vpreg intr_enb;
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struct vpreg msense;
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};
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/*
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* Register initialization tables for the valkyrie display.
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*
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* Dot clock rate is
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* 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
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*/
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struct valkyrie_regvals {
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unsigned char mode;
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unsigned char clock_params[3];
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int pitch[2]; /* bytes/line, indexed by color_mode */
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int hres;
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int vres;
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};
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#ifndef CONFIG_MAC
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/* Register values for 1024x768, 75Hz mode (17) */
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/* I'm not sure which mode this is (16 or 17), so I'm defining it as 17,
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* since the equivalent mode in controlfb (which I adapted this from) is
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* also 17. Just because MacOS can't do this on Valkyrie doesn't mean we
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* can't! :)
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*
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* I was going to use 12, 31, 3, which I found by myself, but instead I'm
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* using 11, 28, 3 like controlfb, for consistency's sake.
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*/
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static struct valkyrie_regvals valkyrie_reg_init_17 = {
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15,
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{ 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
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{ 1024, 0 },
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1024, 768
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};
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/* Register values for 1024x768, 72Hz mode (15) */
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/* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
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* that didn't match MacOS in the same video mode on this chip, and it also
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* caused the 15" Apple Studio Display to not work in this mode. While this
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* mode still doesn't match MacOS exactly (as far as I can tell), it's a lot
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* closer now, and it works with the Apple Studio Display.
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*
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* Yes, even though MacOS calls it "72Hz", in reality it's about 70Hz.
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*/
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static struct valkyrie_regvals valkyrie_reg_init_15 = {
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15,
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{ 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
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/* I interpolated the V=69.71 from the vmode 14 and old 15
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* numbers. Is this result correct?
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*/
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{ 1024, 0 },
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1024, 768
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};
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/* Register values for 1024x768, 60Hz mode (14) */
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static struct valkyrie_regvals valkyrie_reg_init_14 = {
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14,
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{ 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
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{ 1024, 0 },
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1024, 768
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};
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#endif /* !defined CONFIG_MAC */
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/* Register values for 832x624, 75Hz mode (13) */
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static struct valkyrie_regvals valkyrie_reg_init_13 = {
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9,
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{ 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
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{ 832, 0 },
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832, 624
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};
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/* Register values for 800x600, 72Hz mode (11) */
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static struct valkyrie_regvals valkyrie_reg_init_11 = {
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13,
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{ 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
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{ 800, 0 },
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800, 600
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};
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/* Register values for 800x600, 60Hz mode (10) */
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static struct valkyrie_regvals valkyrie_reg_init_10 = {
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12,
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{ 25, 32, 3 }, /* pixel clock = 40.0015MHz,
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used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
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{ 800, 1600 },
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800, 600
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};
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/* Register values for 640x480, 67Hz mode (6) */
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static struct valkyrie_regvals valkyrie_reg_init_6 = {
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6,
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{ 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
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{ 640, 1280 },
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640, 480
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};
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/* Register values for 640x480, 60Hz mode (5) */
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static struct valkyrie_regvals valkyrie_reg_init_5 = {
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11,
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{ 23, 37, 2 }, /* pixel clock = 25.14MHz for V=59.85Hz */
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{ 640, 1280 },
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640, 480
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};
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static struct valkyrie_regvals *valkyrie_reg_init[VMODE_MAX] = {
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NULL,
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NULL,
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NULL,
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NULL,
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&valkyrie_reg_init_5,
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&valkyrie_reg_init_6,
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NULL,
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NULL,
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NULL,
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&valkyrie_reg_init_10,
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&valkyrie_reg_init_11,
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NULL,
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&valkyrie_reg_init_13,
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#ifndef CONFIG_MAC
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&valkyrie_reg_init_14,
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&valkyrie_reg_init_15,
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NULL,
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&valkyrie_reg_init_17,
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#endif
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};
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