211 lines
6.0 KiB
C
211 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* drivers/video/geode/display_gx1.c
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* -- Geode GX1 display controller
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*
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* Copyright (C) 2005 Arcom Control Systems Ltd.
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*
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* Based on AMD's original 2.4 driver:
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* Copyright (C) 2004 Advanced Micro Devices, Inc.
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*/
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#include <linux/spinlock.h>
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#include <linux/fb.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/div64.h>
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#include <asm/delay.h>
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#include "geodefb.h"
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#include "display_gx1.h"
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static DEFINE_SPINLOCK(gx1_conf_reg_lock);
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static u8 gx1_read_conf_reg(u8 reg)
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{
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u8 val, ccr3;
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unsigned long flags;
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spin_lock_irqsave(&gx1_conf_reg_lock, flags);
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outb(CONFIG_CCR3, 0x22);
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ccr3 = inb(0x23);
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outb(CONFIG_CCR3, 0x22);
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outb(ccr3 | CONFIG_CCR3_MAPEN, 0x23);
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outb(reg, 0x22);
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val = inb(0x23);
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outb(CONFIG_CCR3, 0x22);
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outb(ccr3, 0x23);
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spin_unlock_irqrestore(&gx1_conf_reg_lock, flags);
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return val;
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}
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unsigned gx1_gx_base(void)
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{
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return (gx1_read_conf_reg(CONFIG_GCR) & 0x03) << 30;
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}
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int gx1_frame_buffer_size(void)
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{
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void __iomem *mc_regs;
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u32 bank_cfg;
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int d;
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unsigned dram_size = 0, fb_base;
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mc_regs = ioremap(gx1_gx_base() + 0x8400, 0x100);
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if (!mc_regs)
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return -ENOMEM;
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/* Calculate the total size of both DIMM0 and DIMM1. */
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bank_cfg = readl(mc_regs + MC_BANK_CFG);
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for (d = 0; d < 2; d++) {
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if ((bank_cfg & MC_BCFG_DIMM0_PG_SZ_MASK) != MC_BCFG_DIMM0_PG_SZ_NO_DIMM)
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dram_size += 0x400000 << ((bank_cfg & MC_BCFG_DIMM0_SZ_MASK) >> 8);
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bank_cfg >>= 16; /* look at DIMM1 next */
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}
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fb_base = (readl(mc_regs + MC_GBASE_ADD) & MC_GADD_GBADD_MASK) << 19;
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iounmap(mc_regs);
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return dram_size - fb_base;
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}
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static void gx1_set_mode(struct fb_info *info)
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{
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struct geodefb_par *par = info->par;
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u32 gcfg, tcfg, ocfg, dclk_div, val;
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int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
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int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
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/* Unlock the display controller registers. */
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readl(par->dc_regs + DC_UNLOCK);
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writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
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gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
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tcfg = readl(par->dc_regs + DC_TIMING_CFG);
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/* Blank the display and disable the timing generator. */
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tcfg &= ~(DC_TCFG_BLKE | DC_TCFG_TGEN);
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writel(tcfg, par->dc_regs + DC_TIMING_CFG);
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/* Wait for pending memory requests before disabling the FIFO load. */
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udelay(100);
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/* Disable FIFO load and compression. */
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gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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/* Setup DCLK and its divisor. */
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gcfg &= ~DC_GCFG_DCLK_MASK;
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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par->vid_ops->set_dclk(info);
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dclk_div = DC_GCFG_DCLK_DIV_1; /* FIXME: may need to divide DCLK by 2 sometimes? */
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gcfg |= dclk_div;
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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/* Wait for the clock generatation to settle. This is needed since
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* some of the register writes that follow require that clock to be
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* present. */
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udelay(1000); /* FIXME: seems a little long */
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/*
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* Setup new mode.
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*/
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/* Clear all unused feature bits. */
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gcfg = DC_GCFG_VRDY | dclk_div;
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/* Set FIFO priority (default 6/5) and enable. */
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/* FIXME: increase fifo priority for 1280x1024 modes? */
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gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
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/* FIXME: Set pixel and line double bits if necessary. */
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/* Framebuffer start offset. */
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writel(0, par->dc_regs + DC_FB_ST_OFFSET);
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/* Line delta and line buffer length. */
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writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
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writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
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par->dc_regs + DC_BUF_SIZE);
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/* Output configuration. Enable panel data, set pixel format. */
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ocfg = DC_OCFG_PCKE | DC_OCFG_PDEL | DC_OCFG_PDEH;
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if (info->var.bits_per_pixel == 8) ocfg |= DC_OCFG_8BPP;
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/* Enable timing generator, sync and FP data. */
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tcfg = DC_TCFG_FPPE | DC_TCFG_HSYE | DC_TCFG_VSYE | DC_TCFG_BLKE
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| DC_TCFG_TGEN;
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/* Horizontal and vertical timings. */
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hactive = info->var.xres;
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hblankstart = hactive;
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hsyncstart = hblankstart + info->var.right_margin;
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hsyncend = hsyncstart + info->var.hsync_len;
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hblankend = hsyncend + info->var.left_margin;
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htotal = hblankend;
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vactive = info->var.yres;
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vblankstart = vactive;
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vsyncstart = vblankstart + info->var.lower_margin;
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vsyncend = vsyncstart + info->var.vsync_len;
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vblankend = vsyncend + info->var.upper_margin;
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vtotal = vblankend;
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val = (hactive - 1) | ((htotal - 1) << 16);
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writel(val, par->dc_regs + DC_H_TIMING_1);
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val = (hblankstart - 1) | ((hblankend - 1) << 16);
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writel(val, par->dc_regs + DC_H_TIMING_2);
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val = (hsyncstart - 1) | ((hsyncend - 1) << 16);
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writel(val, par->dc_regs + DC_H_TIMING_3);
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writel(val, par->dc_regs + DC_FP_H_TIMING);
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val = (vactive - 1) | ((vtotal - 1) << 16);
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writel(val, par->dc_regs + DC_V_TIMING_1);
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val = (vblankstart - 1) | ((vblankend - 1) << 16);
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writel(val, par->dc_regs + DC_V_TIMING_2);
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val = (vsyncstart - 1) | ((vsyncend - 1) << 16);
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writel(val, par->dc_regs + DC_V_TIMING_3);
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val = (vsyncstart - 2) | ((vsyncend - 2) << 16);
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writel(val, par->dc_regs + DC_FP_V_TIMING);
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/* Write final register values. */
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writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
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writel(tcfg, par->dc_regs + DC_TIMING_CFG);
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udelay(1000); /* delay after TIMING_CFG. FIXME: perhaps a little long */
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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par->vid_ops->configure_display(info);
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/* Relock display controller registers */
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writel(0, par->dc_regs + DC_UNLOCK);
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/* FIXME: write line_length and bpp to Graphics Pipeline GP_BLT_STATUS
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* register. */
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}
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static void gx1_set_hw_palette_reg(struct fb_info *info, unsigned regno,
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unsigned red, unsigned green, unsigned blue)
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{
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struct geodefb_par *par = info->par;
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int val;
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/* Hardware palette is in RGB 6-6-6 format. */
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val = (red << 2) & 0x3f000;
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val |= (green >> 4) & 0x00fc0;
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val |= (blue >> 10) & 0x0003f;
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writel(regno, par->dc_regs + DC_PAL_ADDRESS);
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writel(val, par->dc_regs + DC_PAL_DATA);
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}
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const struct geode_dc_ops gx1_dc_ops = {
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.set_mode = gx1_set_mode,
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.set_palette_reg = gx1_set_hw_palette_reg,
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};
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