146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors: Dave Airlie <airlied@redhat.com>
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*/
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#include <linux/pci.h>
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#include "ast_drv.h"
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void ast_post_chip_2500(struct drm_device *dev);
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void ast_enable_vga(struct drm_device *dev)
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{
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struct ast_private *ast = to_ast_private(dev);
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u8 ch;
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ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
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ch = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
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ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, ch | 0x01);
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}
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void ast_disable_vga(struct drm_device *dev)
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{
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struct ast_private *ast = to_ast_private(dev);
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ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x0);
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}
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void ast_enable_mmio(struct drm_device *dev)
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{
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struct ast_private *ast = to_ast_private(dev);
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ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
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}
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bool ast_is_vga_enabled(struct drm_device *dev)
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{
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struct ast_private *ast = to_ast_private(dev);
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u8 ch;
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ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
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return !!(ch & 0x01);
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}
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static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
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static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
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static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
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static void ast_set_def_ext_reg(struct drm_device *dev)
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{
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struct ast_private *ast = to_ast_private(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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u8 i, index, reg;
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const u8 *ext_reg_info;
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/* reset scratch */
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for (i = 0x81; i <= 0x9f; i++)
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ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
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if (ast->chip == AST2300 || ast->chip == AST2400 ||
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ast->chip == AST2500 || ast->chip == AST2600) {
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if (pdev->revision >= 0x20)
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ext_reg_info = extreginfo_ast2300;
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else
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ext_reg_info = extreginfo_ast2300a0;
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} else
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ext_reg_info = extreginfo;
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index = 0xa0;
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while (*ext_reg_info != 0xff) {
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00,
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*ext_reg_info);
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index++;
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ext_reg_info++;
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}
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/* disable standard IO/MEM decode if secondary */
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/* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
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/* Set Ext. Default */
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
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/* Enable RAMDAC for A1 */
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reg = 0x04;
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if (ast->chip == AST2300 || ast->chip == AST2400 ||
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ast->chip == AST2500 || ast->chip == AST2600)
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reg |= 0x20;
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
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}
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void ast_post_gpu(struct drm_device *dev)
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{
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struct ast_private *ast = to_ast_private(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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u32 reg;
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pci_read_config_dword(pdev, 0x04, ®);
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reg |= 0x3;
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pci_write_config_dword(pdev, 0x04, reg);
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ast_enable_vga(dev);
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ast_open_key(ast);
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ast_enable_mmio(dev);
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ast_set_def_ext_reg(dev);
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if (ast->chip == AST2600) {
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ast_dp_launch(dev, 1);
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} else if (ast->config_mode == ast_use_p2a) {
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if (ast->chip == AST2500)
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ast_post_chip_2500(dev);
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ast_init_3rdtx(dev);
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} else {
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/* Enable DVO */
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if (ast->tx_chip_type != AST_TX_NONE)
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ast_set_index_reg_mask(ast,
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AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
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}
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}
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