780 lines
26 KiB
C
780 lines
26 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
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* of PCI-SCSI IO processors.
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*
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* Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
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*
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* This driver is derived from the Linux sym53c8xx driver.
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* Copyright (C) 1998-2000 Gerard Roudier
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*
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* The sym53c8xx driver is derived from the ncr53c8xx driver that had been
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* a port of the FreeBSD ncr driver to Linux-1.2.13.
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*
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* The original ncr driver has been written for 386bsd and FreeBSD by
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* Wolfgang Stanglmeier <wolf@cologne.de>
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* Stefan Esser <se@mi.Uni-Koeln.de>
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* Copyright (C) 1994 Wolfgang Stanglmeier
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*
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* Other major contributions:
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*
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* NVRAM detection and reading.
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* Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
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*
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*-----------------------------------------------------------------------------
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*/
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#ifndef SYM_DEFS_H
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#define SYM_DEFS_H
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#define SYM_VERSION "2.2.3"
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#define SYM_DRIVER_NAME "sym-" SYM_VERSION
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/*
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* SYM53C8XX device features descriptor.
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*/
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struct sym_chip {
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u_short device_id;
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u_short revision_id;
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char *name;
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u_char burst_max; /* log-base-2 of max burst */
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u_char offset_max;
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u_char nr_divisor;
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u_char lp_probe_bit;
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u_int features;
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#define FE_LED0 (1<<0)
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#define FE_WIDE (1<<1) /* Wide data transfers */
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#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
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#define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
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#define FE_DBLR (1<<4) /* Clock doubler present */
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#define FE_QUAD (1<<5) /* Clock quadrupler present */
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#define FE_ERL (1<<6) /* Enable read line */
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#define FE_CLSE (1<<7) /* Cache line size enable */
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#define FE_WRIE (1<<8) /* Write & Invalidate enable */
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#define FE_ERMP (1<<9) /* Enable read multiple */
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#define FE_BOF (1<<10) /* Burst opcode fetch */
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#define FE_DFS (1<<11) /* DMA fifo size */
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#define FE_PFEN (1<<12) /* Prefetch enable */
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#define FE_LDSTR (1<<13) /* Load/Store supported */
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#define FE_RAM (1<<14) /* On chip RAM present */
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#define FE_VARCLK (1<<15) /* Clock frequency may vary */
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#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
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#define FE_64BIT (1<<17) /* 64-bit PCI BUS interface */
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#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
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#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
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#define FE_LEDC (1<<20) /* Hardware control of LED */
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#define FE_ULTRA3 (1<<21) /* Ultra 3 - 80 Mtrans/sec DT */
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#define FE_66MHZ (1<<22) /* 66MHz PCI support */
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#define FE_CRC (1<<23) /* CRC support */
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#define FE_DIFF (1<<24) /* SCSI HVD support */
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#define FE_DFBC (1<<25) /* Have DFBC register */
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#define FE_LCKFRQ (1<<26) /* Have LCKFRQ */
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#define FE_C10 (1<<27) /* Various C10 core (mis)features */
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#define FE_U3EN (1<<28) /* U3EN bit usable */
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#define FE_DAC (1<<29) /* Support PCI DAC (64 bit addressing) */
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#define FE_ISTAT1 (1<<30) /* Have ISTAT1, MBOX0, MBOX1 registers */
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#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
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#define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
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};
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/*
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* SYM53C8XX IO register data structure.
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*/
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struct sym_reg {
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/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
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/*01*/ u8 nc_scntl1; /* no reset */
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#define ISCON 0x10 /* connected to scsi */
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#define CRST 0x08 /* force reset */
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#define IARB 0x02 /* immediate arbitration */
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/*02*/ u8 nc_scntl2; /* no disconnect expected */
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#define SDU 0x80 /* cmd: disconnect will raise error */
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#define CHM 0x40 /* sta: chained mode */
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#define WSS 0x08 /* sta: wide scsi send [W]*/
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#define WSR 0x01 /* sta: wide scsi received [W]*/
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/*03*/ u8 nc_scntl3; /* cnf system clock dependent */
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#define EWS 0x08 /* cmd: enable wide scsi [W]*/
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#define ULTRA 0x80 /* cmd: ULTRA enable */
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/* bits 0-2, 7 rsvd for C1010 */
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/*04*/ u8 nc_scid; /* cnf host adapter scsi address */
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#define RRE 0x40 /* r/w:e enable response to resel. */
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#define SRE 0x20 /* r/w:e enable response to select */
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/*05*/ u8 nc_sxfer; /* ### Sync speed and count */
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/* bits 6-7 rsvd for C1010 */
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/*06*/ u8 nc_sdid; /* ### Destination-ID */
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/*07*/ u8 nc_gpreg; /* ??? IO-Pins */
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/*08*/ u8 nc_sfbr; /* ### First byte received */
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/*09*/ u8 nc_socl;
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#define CREQ 0x80 /* r/w: SCSI-REQ */
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#define CACK 0x40 /* r/w: SCSI-ACK */
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#define CBSY 0x20 /* r/w: SCSI-BSY */
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#define CSEL 0x10 /* r/w: SCSI-SEL */
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#define CATN 0x08 /* r/w: SCSI-ATN */
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#define CMSG 0x04 /* r/w: SCSI-MSG */
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#define CC_D 0x02 /* r/w: SCSI-C_D */
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#define CI_O 0x01 /* r/w: SCSI-I_O */
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/*0a*/ u8 nc_ssid;
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/*0b*/ u8 nc_sbcl;
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/*0c*/ u8 nc_dstat;
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#define DFE 0x80 /* sta: dma fifo empty */
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#define MDPE 0x40 /* int: master data parity error */
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#define BF 0x20 /* int: script: bus fault */
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#define ABRT 0x10 /* int: script: command aborted */
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#define SSI 0x08 /* int: script: single step */
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#define SIR 0x04 /* int: script: interrupt instruct. */
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#define IID 0x01 /* int: script: illegal instruct. */
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/*0d*/ u8 nc_sstat0;
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#define ILF 0x80 /* sta: data in SIDL register lsb */
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#define ORF 0x40 /* sta: data in SODR register lsb */
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#define OLF 0x20 /* sta: data in SODL register lsb */
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#define AIP 0x10 /* sta: arbitration in progress */
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#define LOA 0x08 /* sta: arbitration lost */
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#define WOA 0x04 /* sta: arbitration won */
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#define IRST 0x02 /* sta: scsi reset signal */
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#define SDP 0x01 /* sta: scsi parity signal */
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/*0e*/ u8 nc_sstat1;
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#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
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/*0f*/ u8 nc_sstat2;
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#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
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#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
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#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
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#define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
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#define LDSC 0x02 /* sta: disconnect & reconnect */
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/*10*/ u8 nc_dsa; /* --> Base page */
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/*11*/ u8 nc_dsa1;
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/*12*/ u8 nc_dsa2;
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/*13*/ u8 nc_dsa3;
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/*14*/ u8 nc_istat; /* --> Main Command and status */
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#define CABRT 0x80 /* cmd: abort current operation */
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#define SRST 0x40 /* mod: reset chip */
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#define SIGP 0x20 /* r/w: message from host to script */
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#define SEM 0x10 /* r/w: message between host + script */
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#define CON 0x08 /* sta: connected to scsi */
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#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
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#define SIP 0x02 /* sta: scsi-interrupt */
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#define DIP 0x01 /* sta: host/script interrupt */
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/*15*/ u8 nc_istat1; /* 896 only */
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#define FLSH 0x04 /* sta: chip is flushing */
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#define SCRUN 0x02 /* sta: scripts are running */
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#define SIRQD 0x01 /* r/w: disable INT pin */
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/*16*/ u8 nc_mbox0; /* 896 only */
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/*17*/ u8 nc_mbox1; /* 896 only */
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/*18*/ u8 nc_ctest0;
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/*19*/ u8 nc_ctest1;
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/*1a*/ u8 nc_ctest2;
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#define CSIGP 0x40
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/* bits 0-2,7 rsvd for C1010 */
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/*1b*/ u8 nc_ctest3;
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#define FLF 0x08 /* cmd: flush dma fifo */
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#define CLF 0x04 /* cmd: clear dma fifo */
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#define FM 0x02 /* mod: fetch pin mode */
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#define WRIE 0x01 /* mod: write and invalidate enable */
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/* bits 4-7 rsvd for C1010 */
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/*1c*/ u32 nc_temp; /* ### Temporary stack */
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/*20*/ u8 nc_dfifo;
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/*21*/ u8 nc_ctest4;
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#define BDIS 0x80 /* mod: burst disable */
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#define MPEE 0x08 /* mod: master parity error enable */
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/*22*/ u8 nc_ctest5;
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#define DFS 0x20 /* mod: dma fifo size */
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/* bits 0-1, 3-7 rsvd for C1010 */
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/*23*/ u8 nc_ctest6;
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/*24*/ u32 nc_dbc; /* ### Byte count and command */
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/*28*/ u32 nc_dnad; /* ### Next command register */
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/*2c*/ u32 nc_dsp; /* --> Script Pointer */
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/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
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/*34*/ u8 nc_scratcha; /* Temporary register a */
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/*35*/ u8 nc_scratcha1;
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/*36*/ u8 nc_scratcha2;
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/*37*/ u8 nc_scratcha3;
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/*38*/ u8 nc_dmode;
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#define BL_2 0x80 /* mod: burst length shift value +2 */
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#define BL_1 0x40 /* mod: burst length shift value +1 */
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#define ERL 0x08 /* mod: enable read line */
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#define ERMP 0x04 /* mod: enable read multiple */
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#define BOF 0x02 /* mod: burst op code fetch */
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/*39*/ u8 nc_dien;
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/*3a*/ u8 nc_sbr;
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/*3b*/ u8 nc_dcntl; /* --> Script execution control */
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#define CLSE 0x80 /* mod: cache line size enable */
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#define PFF 0x40 /* cmd: pre-fetch flush */
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#define PFEN 0x20 /* mod: pre-fetch enable */
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#define SSM 0x10 /* mod: single step mode */
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#define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
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#define STD 0x04 /* cmd: start dma mode */
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#define IRQD 0x02 /* mod: irq disable */
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#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
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/* bits 0-1 rsvd for C1010 */
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/*3c*/ u32 nc_adder;
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/*40*/ u16 nc_sien; /* -->: interrupt enable */
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/*42*/ u16 nc_sist; /* <--: interrupt status */
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#define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
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#define STO 0x0400/* sta: timeout (select) */
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#define GEN 0x0200/* sta: timeout (general) */
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#define HTH 0x0100/* sta: timeout (handshake) */
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#define MA 0x80 /* sta: phase mismatch */
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#define CMP 0x40 /* sta: arbitration complete */
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#define SEL 0x20 /* sta: selected by another device */
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#define RSL 0x10 /* sta: reselected by another device*/
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#define SGE 0x08 /* sta: gross error (over/underflow)*/
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#define UDC 0x04 /* sta: unexpected disconnect */
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#define RST 0x02 /* sta: scsi bus reset detected */
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#define PAR 0x01 /* sta: scsi parity error */
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/*44*/ u8 nc_slpar;
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/*45*/ u8 nc_swide;
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/*46*/ u8 nc_macntl;
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/*47*/ u8 nc_gpcntl;
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/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
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/*49*/ u8 nc_stime1; /* cmd: timeout user defined */
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/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
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/*4c*/ u8 nc_stest0;
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/*4d*/ u8 nc_stest1;
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#define SCLK 0x80 /* Use the PCI clock as SCSI clock */
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#define DBLEN 0x08 /* clock doubler running */
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#define DBLSEL 0x04 /* clock doubler selected */
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/*4e*/ u8 nc_stest2;
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#define ROF 0x40 /* reset scsi offset (after gross error!) */
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#define EXT 0x02 /* extended filtering */
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/*4f*/ u8 nc_stest3;
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#define TE 0x80 /* c: tolerAnt enable */
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#define HSC 0x20 /* c: Halt SCSI Clock */
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#define CSF 0x02 /* c: clear scsi fifo */
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/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
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/*52*/ u8 nc_stest4;
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#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
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#define SMODE_HVD 0x40 /* High Voltage Differential */
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#define SMODE_SE 0x80 /* Single Ended */
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#define SMODE_LVD 0xc0 /* Low Voltage Differential */
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#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
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/* bits 0-5 rsvd for C1010 */
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/*53*/ u8 nc_53_;
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/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
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/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
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#define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
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#define PMJCTL 0x40 /* Phase Mismatch Jump Control */
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#define ENNDJ 0x20 /* Enable Non Data PM Jump */
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#define DISFC 0x10 /* Disable Auto FIFO Clear */
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#define DILS 0x02 /* Disable Internal Load/Store */
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#define DPR 0x01 /* Disable Pipe Req */
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/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
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#define ZMOD 0x80 /* High Impedance Mode */
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#define DDAC 0x08 /* Disable Dual Address Cycle */
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#define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
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#define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
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#define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
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/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
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/*5a*/ u16 nc_5a_;
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/*5c*/ u8 nc_scr0; /* Working register B */
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/*5d*/ u8 nc_scr1;
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/*5e*/ u8 nc_scr2;
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/*5f*/ u8 nc_scr3;
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/*60*/ u8 nc_scrx[64]; /* Working register C-R */
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/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
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/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
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/*a8*/ u32 nc_sfs; /* Script Fetch Selector */
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/*ac*/ u32 nc_drs; /* DSA Relative Selector */
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/*b0*/ u32 nc_sbms; /* Static Block Move Selector */
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/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
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/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
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/*bc*/ u16 nc_scntl4; /* C1010 only */
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#define U3EN 0x80 /* Enable Ultra 3 */
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#define AIPCKEN 0x40 /* AIP checking enable */
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/* Also enable AIP generation on C10-33*/
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#define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
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#define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
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#define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */
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#define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */
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/*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */
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/*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */
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#define DISAIP 0x08 /* Disable AIP generation C10-66 only */
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/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
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/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
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/*c8*/ u8 nc_rbc; /* Remaining Byte Count */
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/*c9*/ u8 nc_rbc1;
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/*ca*/ u8 nc_rbc2;
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/*cb*/ u8 nc_rbc3;
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/*cc*/ u8 nc_ua; /* Updated Address */
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/*cd*/ u8 nc_ua1;
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/*ce*/ u8 nc_ua2;
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/*cf*/ u8 nc_ua3;
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/*d0*/ u32 nc_esa; /* Entry Storage Address */
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/*d4*/ u8 nc_ia; /* Instruction Address */
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/*d5*/ u8 nc_ia1;
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/*d6*/ u8 nc_ia2;
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/*d7*/ u8 nc_ia3;
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/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
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/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
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/* Following for C1010 only */
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/*e0*/ u16 nc_crcpad; /* CRC Value */
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/*e2*/ u8 nc_crccntl0; /* CRC control register */
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#define SNDCRC 0x10 /* Send CRC Request */
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/*e3*/ u8 nc_crccntl1; /* CRC control register */
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/*e4*/ u32 nc_crcdata; /* CRC data register */
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/*e8*/ u32 nc_e8_;
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/*ec*/ u32 nc_ec_;
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/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
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};
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/*-----------------------------------------------------------
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*
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* Utility macros for the script.
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*
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*-----------------------------------------------------------
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*/
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#define REGJ(p,r) (offsetof(struct sym_reg, p ## r))
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#define REG(r) REGJ (nc_, r)
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/*-----------------------------------------------------------
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*
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* SCSI phases
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*
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*-----------------------------------------------------------
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*/
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#define SCR_DATA_OUT 0x00000000
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#define SCR_DATA_IN 0x01000000
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#define SCR_COMMAND 0x02000000
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#define SCR_STATUS 0x03000000
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#define SCR_DT_DATA_OUT 0x04000000
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#define SCR_DT_DATA_IN 0x05000000
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#define SCR_MSG_OUT 0x06000000
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#define SCR_MSG_IN 0x07000000
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/* DT phases are illegal for non Ultra3 mode */
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#define SCR_ILG_OUT 0x04000000
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#define SCR_ILG_IN 0x05000000
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/*-----------------------------------------------------------
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*
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* Data transfer via SCSI.
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*
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*-----------------------------------------------------------
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*
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* MOVE_ABS (LEN)
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* <<start address>>
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*
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* MOVE_IND (LEN)
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* <<dnad_offset>>
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*
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* MOVE_TBL
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* <<dnad_offset>>
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*
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*-----------------------------------------------------------
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*/
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#define OPC_MOVE 0x08000000
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#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
|
|
/* #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) */
|
|
#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
|
|
|
|
#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
|
|
/* #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) */
|
|
#define SCR_CHMOV_TBL (0x10000000)
|
|
|
|
#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
|
|
/* We steal the `indirect addressing' flag for target mode MOVE in scripts */
|
|
|
|
#define OPC_TCHMOVE 0x08000000
|
|
|
|
#define SCR_TCHMOVE_ABS(l) ((0x20000000 | OPC_TCHMOVE) | (l))
|
|
#define SCR_TCHMOVE_TBL (0x30000000 | OPC_TCHMOVE)
|
|
|
|
#define SCR_TMOV_ABS(l) ((0x20000000) | (l))
|
|
#define SCR_TMOV_TBL (0x30000000)
|
|
#endif
|
|
|
|
struct sym_tblmove {
|
|
u32 size;
|
|
u32 addr;
|
|
};
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* Selection
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
|
|
* <<alternate_address>>
|
|
*
|
|
* SEL_TBL | << dnad_offset>> [ | REL_JMP]
|
|
* <<alternate_address>>
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_SEL_ABS 0x40000000
|
|
#define SCR_SEL_ABS_ATN 0x41000000
|
|
#define SCR_SEL_TBL 0x42000000
|
|
#define SCR_SEL_TBL_ATN 0x43000000
|
|
|
|
#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
|
|
#define SCR_RESEL_ABS 0x40000000
|
|
#define SCR_RESEL_ABS_ATN 0x41000000
|
|
#define SCR_RESEL_TBL 0x42000000
|
|
#define SCR_RESEL_TBL_ATN 0x43000000
|
|
#endif
|
|
|
|
struct sym_tblsel {
|
|
u_char sel_scntl4; /* C1010 only */
|
|
u_char sel_sxfer;
|
|
u_char sel_id;
|
|
u_char sel_scntl3;
|
|
};
|
|
|
|
#define SCR_JMP_REL 0x04000000
|
|
#define SCR_ID(id) (((u32)(id)) << 16)
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* Waiting for Disconnect or Reselect
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* WAIT_DISC
|
|
* dummy: <<alternate_address>>
|
|
*
|
|
* WAIT_RESEL
|
|
* <<alternate_address>>
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_WAIT_DISC 0x48000000
|
|
#define SCR_WAIT_RESEL 0x50000000
|
|
|
|
#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
|
|
#define SCR_DISCONNECT 0x48000000
|
|
#endif
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* Bit Set / Reset
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* SET (flags {|.. })
|
|
*
|
|
* CLR (flags {|.. })
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_SET(f) (0x58000000 | (f))
|
|
#define SCR_CLR(f) (0x60000000 | (f))
|
|
|
|
#define SCR_CARRY 0x00000400
|
|
#define SCR_TRG 0x00000200
|
|
#define SCR_ACK 0x00000040
|
|
#define SCR_ATN 0x00000008
|
|
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* Memory to memory move
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* COPY (bytecount)
|
|
* << source_address >>
|
|
* << destination_address >>
|
|
*
|
|
* SCR_COPY sets the NO FLUSH option by default.
|
|
* SCR_COPY_F does not set this option.
|
|
*
|
|
* For chips which do not support this option,
|
|
* sym_fw_bind_script() will remove this bit.
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_NO_FLUSH 0x01000000
|
|
|
|
#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
|
|
#define SCR_COPY_F(n) (0xc0000000 | (n))
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* Register move and binary operations
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* SFBR_REG (reg, op, data) reg = SFBR op data
|
|
* << 0 >>
|
|
*
|
|
* REG_SFBR (reg, op, data) SFBR = reg op data
|
|
* << 0 >>
|
|
*
|
|
* REG_REG (reg, op, data) reg = reg op data
|
|
* << 0 >>
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* On 825A, 875, 895 and 896 chips the content
|
|
* of SFBR register can be used as data (SCR_SFBR_DATA).
|
|
* The 896 has additionnal IO registers starting at
|
|
* offset 0x80. Bit 7 of register offset is stored in
|
|
* bit 7 of the SCRIPTS instruction first DWORD.
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
|
|
|
|
#define SCR_SFBR_REG(reg,op,data) \
|
|
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
|
|
|
#define SCR_REG_SFBR(reg,op,data) \
|
|
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
|
|
|
#define SCR_REG_REG(reg,op,data) \
|
|
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
|
|
|
|
|
#define SCR_LOAD 0x00000000
|
|
#define SCR_SHL 0x01000000
|
|
#define SCR_OR 0x02000000
|
|
#define SCR_XOR 0x03000000
|
|
#define SCR_AND 0x04000000
|
|
#define SCR_SHR 0x05000000
|
|
#define SCR_ADD 0x06000000
|
|
#define SCR_ADDC 0x07000000
|
|
|
|
#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* FROM_REG (reg) SFBR = reg
|
|
* << 0 >>
|
|
*
|
|
* TO_REG (reg) reg = SFBR
|
|
* << 0 >>
|
|
*
|
|
* LOAD_REG (reg, data) reg = <data>
|
|
* << 0 >>
|
|
*
|
|
* LOAD_SFBR(data) SFBR = <data>
|
|
* << 0 >>
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_FROM_REG(reg) \
|
|
SCR_REG_SFBR(reg,SCR_OR,0)
|
|
|
|
#define SCR_TO_REG(reg) \
|
|
SCR_SFBR_REG(reg,SCR_OR,0)
|
|
|
|
#define SCR_LOAD_REG(reg,data) \
|
|
SCR_REG_REG(reg,SCR_LOAD,data)
|
|
|
|
#define SCR_LOAD_SFBR(data) \
|
|
(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* LOAD from memory to register.
|
|
* STORE from register to memory.
|
|
*
|
|
* Only supported by 810A, 860, 825A, 875, 895 and 896.
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* LOAD_ABS (LEN)
|
|
* <<start address>>
|
|
*
|
|
* LOAD_REL (LEN) (DSA relative)
|
|
* <<dsa_offset>>
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
|
|
#define SCR_NO_FLUSH2 0x02000000
|
|
#define SCR_DSA_REL2 0x10000000
|
|
|
|
#define SCR_LOAD_R(reg, how, n) \
|
|
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
|
|
|
|
#define SCR_STORE_R(reg, how, n) \
|
|
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
|
|
|
|
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
|
|
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
|
|
#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
|
|
#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
|
|
|
|
#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
|
|
#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
|
|
#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
|
|
#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
|
|
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* Waiting for Disconnect or Reselect
|
|
*
|
|
*-----------------------------------------------------------
|
|
*
|
|
* JUMP [ | IFTRUE/IFFALSE ( ... ) ]
|
|
* <<address>>
|
|
*
|
|
* JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
|
|
* <<distance>>
|
|
*
|
|
* CALL [ | IFTRUE/IFFALSE ( ... ) ]
|
|
* <<address>>
|
|
*
|
|
* CALLR [ | IFTRUE/IFFALSE ( ... ) ]
|
|
* <<distance>>
|
|
*
|
|
* RETURN [ | IFTRUE/IFFALSE ( ... ) ]
|
|
* <<dummy>>
|
|
*
|
|
* INT [ | IFTRUE/IFFALSE ( ... ) ]
|
|
* <<ident>>
|
|
*
|
|
* INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
|
|
* <<ident>>
|
|
*
|
|
* Conditions:
|
|
* WHEN (phase)
|
|
* IF (phase)
|
|
* CARRYSET
|
|
* DATA (data, mask)
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
#define SCR_NO_OP 0x80000000
|
|
#define SCR_JUMP 0x80080000
|
|
#define SCR_JUMP64 0x80480000
|
|
#define SCR_JUMPR 0x80880000
|
|
#define SCR_CALL 0x88080000
|
|
#define SCR_CALLR 0x88880000
|
|
#define SCR_RETURN 0x90080000
|
|
#define SCR_INT 0x98080000
|
|
#define SCR_INT_FLY 0x98180000
|
|
|
|
#define IFFALSE(arg) (0x00080000 | (arg))
|
|
#define IFTRUE(arg) (0x00000000 | (arg))
|
|
|
|
#define WHEN(phase) (0x00030000 | (phase))
|
|
#define IF(phase) (0x00020000 | (phase))
|
|
|
|
#define DATA(D) (0x00040000 | ((D) & 0xff))
|
|
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
|
|
|
|
#define CARRYSET (0x00200000)
|
|
|
|
/*-----------------------------------------------------------
|
|
*
|
|
* SCSI constants.
|
|
*
|
|
*-----------------------------------------------------------
|
|
*/
|
|
|
|
/*
|
|
* Messages
|
|
*/
|
|
|
|
#define M_COMPLETE COMMAND_COMPLETE
|
|
#define M_EXTENDED EXTENDED_MESSAGE
|
|
#define M_SAVE_DP SAVE_POINTERS
|
|
#define M_RESTORE_DP RESTORE_POINTERS
|
|
#define M_DISCONNECT DISCONNECT
|
|
#define M_ID_ERROR INITIATOR_ERROR
|
|
#define M_ABORT ABORT_TASK_SET
|
|
#define M_REJECT MESSAGE_REJECT
|
|
#define M_NOOP NOP
|
|
#define M_PARITY MSG_PARITY_ERROR
|
|
#define M_LCOMPLETE LINKED_CMD_COMPLETE
|
|
#define M_FCOMPLETE LINKED_FLG_CMD_COMPLETE
|
|
#define M_RESET TARGET_RESET
|
|
#define M_ABORT_TAG ABORT_TASK
|
|
#define M_CLEAR_QUEUE CLEAR_TASK_SET
|
|
#define M_INIT_REC INITIATE_RECOVERY
|
|
#define M_REL_REC RELEASE_RECOVERY
|
|
#define M_TERMINATE (0x11)
|
|
#define M_SIMPLE_TAG SIMPLE_QUEUE_TAG
|
|
#define M_HEAD_TAG HEAD_OF_QUEUE_TAG
|
|
#define M_ORDERED_TAG ORDERED_QUEUE_TAG
|
|
#define M_IGN_RESIDUE IGNORE_WIDE_RESIDUE
|
|
|
|
#define M_X_MODIFY_DP EXTENDED_MODIFY_DATA_POINTER
|
|
#define M_X_SYNC_REQ EXTENDED_SDTR
|
|
#define M_X_WIDE_REQ EXTENDED_WDTR
|
|
#define M_X_PPR_REQ EXTENDED_PPR
|
|
|
|
/*
|
|
* PPR protocol options
|
|
*/
|
|
#define PPR_OPT_IU (0x01)
|
|
#define PPR_OPT_DT (0x02)
|
|
#define PPR_OPT_QAS (0x04)
|
|
#define PPR_OPT_MASK (0x07)
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
|
|
#define S_GOOD SAM_STAT_GOOD
|
|
#define S_CHECK_COND SAM_STAT_CHECK_CONDITION
|
|
#define S_COND_MET SAM_STAT_CONDITION_MET
|
|
#define S_BUSY SAM_STAT_BUSY
|
|
#define S_INT SAM_STAT_INTERMEDIATE
|
|
#define S_INT_COND_MET SAM_STAT_INTERMEDIATE_CONDITION_MET
|
|
#define S_CONFLICT SAM_STAT_RESERVATION_CONFLICT
|
|
#define S_TERMINATED SAM_STAT_COMMAND_TERMINATED
|
|
#define S_QUEUE_FULL SAM_STAT_TASK_SET_FULL
|
|
#define S_ILLEGAL (0xff)
|
|
|
|
#endif /* defined SYM_DEFS_H */
|