170 lines
3.7 KiB
C
170 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
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* Copyright (c) 2014- QLogic Corporation.
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* All rights reserved
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* www.qlogic.com
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*
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* Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
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*/
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#include "bfad_drv.h"
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#include "bfa_modules.h"
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#include "bfi_reg.h"
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BFA_TRC_FILE(HAL, IOCFC_CT);
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/*
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* Dummy interrupt handler for handling spurious interrupt during chip-reinit.
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*/
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static void
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bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
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{
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}
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void
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bfa_hwct_reginit(struct bfa_s *bfa)
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{
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struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
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void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
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int fn = bfa_ioc_pcifn(&bfa->ioc);
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if (fn == 0) {
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bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
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} else {
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bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
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}
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}
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void
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bfa_hwct2_reginit(struct bfa_s *bfa)
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{
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struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
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void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
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bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
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bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK);
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}
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void
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bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
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{
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u32 r32;
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r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
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writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
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}
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/*
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* Actions to respond RME Interrupt for Catapult ASIC:
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* - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
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* - Acknowledge by writing to RME Queue Control register
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* - Update CI
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*/
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void
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bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
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{
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u32 r32;
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r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
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writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
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bfa_rspq_ci(bfa, rspq) = ci;
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writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
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}
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/*
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* Actions to respond RME Interrupt for Catapult2 ASIC:
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* - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
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* - Update CI
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*/
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void
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bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
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{
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bfa_rspq_ci(bfa, rspq) = ci;
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writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
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}
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void
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bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
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u32 *num_vecs, u32 *max_vec_bit)
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{
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*msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
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*max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
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*num_vecs = BFI_MSIX_CT_MAX;
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}
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/*
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* Setup MSI-X vector for catapult
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*/
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void
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bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
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{
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WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
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bfa_trc(bfa, nvecs);
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bfa->msix.nvecs = nvecs;
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bfa_hwct_msix_uninstall(bfa);
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}
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void
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bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
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{
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if (bfa->msix.nvecs == 0)
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return;
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if (bfa->msix.nvecs == 1)
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bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
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else
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bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
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}
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void
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bfa_hwct_msix_queue_install(struct bfa_s *bfa)
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{
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int i;
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if (bfa->msix.nvecs == 0)
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return;
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if (bfa->msix.nvecs == 1) {
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for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
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bfa->msix.handler[i] = bfa_msix_all;
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return;
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}
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for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
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bfa->msix.handler[i] = bfa_msix_reqq;
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for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
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bfa->msix.handler[i] = bfa_msix_rspq;
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}
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void
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bfa_hwct_msix_uninstall(struct bfa_s *bfa)
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{
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int i;
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for (i = 0; i < BFI_MSIX_CT_MAX; i++)
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bfa->msix.handler[i] = bfa_hwct_msix_dummy;
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}
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/*
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* Enable MSI-X vectors
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*/
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void
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bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
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{
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bfa_trc(bfa, 0);
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bfa_ioc_isr_mode_set(&bfa->ioc, msix);
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}
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void
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bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
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{
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*start = BFI_MSIX_RME_QMIN_CT;
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*end = BFI_MSIX_RME_QMAX_CT;
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}
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