439 lines
11 KiB
C
439 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3
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*
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* Copyright 1999 Derrick J Brashear (shadow@dementia.org)
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* Copyright 2008 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/ioport.h>
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#include <linux/miscdevice.h>
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#include <linux/mm.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#define UCTRL_MINOR 174
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#define DEBUG 1
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#ifdef DEBUG
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#define dprintk(x) printk x
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#else
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#define dprintk(x)
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#endif
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struct uctrl_regs {
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u32 uctrl_intr;
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u32 uctrl_data;
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u32 uctrl_stat;
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u32 uctrl_xxx[5];
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};
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struct ts102_regs {
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u32 card_a_intr;
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u32 card_a_stat;
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u32 card_a_ctrl;
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u32 card_a_xxx;
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u32 card_b_intr;
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u32 card_b_stat;
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u32 card_b_ctrl;
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u32 card_b_xxx;
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u32 uctrl_intr;
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u32 uctrl_data;
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u32 uctrl_stat;
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u32 uctrl_xxx;
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u32 ts102_xxx[4];
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};
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/* Bits for uctrl_intr register */
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#define UCTRL_INTR_TXE_REQ 0x01 /* transmit FIFO empty int req */
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#define UCTRL_INTR_TXNF_REQ 0x02 /* transmit FIFO not full int req */
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#define UCTRL_INTR_RXNE_REQ 0x04 /* receive FIFO not empty int req */
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#define UCTRL_INTR_RXO_REQ 0x08 /* receive FIFO overflow int req */
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#define UCTRL_INTR_TXE_MSK 0x10 /* transmit FIFO empty mask */
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#define UCTRL_INTR_TXNF_MSK 0x20 /* transmit FIFO not full mask */
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#define UCTRL_INTR_RXNE_MSK 0x40 /* receive FIFO not empty mask */
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#define UCTRL_INTR_RXO_MSK 0x80 /* receive FIFO overflow mask */
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/* Bits for uctrl_stat register */
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#define UCTRL_STAT_TXE_STA 0x01 /* transmit FIFO empty status */
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#define UCTRL_STAT_TXNF_STA 0x02 /* transmit FIFO not full status */
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#define UCTRL_STAT_RXNE_STA 0x04 /* receive FIFO not empty status */
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#define UCTRL_STAT_RXO_STA 0x08 /* receive FIFO overflow status */
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static DEFINE_MUTEX(uctrl_mutex);
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static const char *uctrl_extstatus[16] = {
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"main power available",
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"internal battery attached",
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"external battery attached",
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"external VGA attached",
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"external keyboard attached",
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"external mouse attached",
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"lid down",
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"internal battery currently charging",
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"external battery currently charging",
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"internal battery currently discharging",
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"external battery currently discharging",
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};
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/* Everything required for one transaction with the uctrl */
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struct uctrl_txn {
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u8 opcode;
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u8 inbits;
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u8 outbits;
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u8 *inbuf;
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u8 *outbuf;
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};
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struct uctrl_status {
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u8 current_temp; /* 0x07 */
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u8 reset_status; /* 0x0b */
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u16 event_status; /* 0x0c */
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u16 error_status; /* 0x10 */
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u16 external_status; /* 0x11, 0x1b */
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u8 internal_charge; /* 0x18 */
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u8 external_charge; /* 0x19 */
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u16 control_lcd; /* 0x20 */
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u8 control_bitport; /* 0x21 */
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u8 speaker_volume; /* 0x23 */
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u8 control_tft_brightness; /* 0x24 */
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u8 control_kbd_repeat_delay; /* 0x28 */
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u8 control_kbd_repeat_period; /* 0x29 */
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u8 control_screen_contrast; /* 0x2F */
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};
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enum uctrl_opcode {
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READ_SERIAL_NUMBER=0x1,
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READ_ETHERNET_ADDRESS=0x2,
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READ_HARDWARE_VERSION=0x3,
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READ_MICROCONTROLLER_VERSION=0x4,
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READ_MAX_TEMPERATURE=0x5,
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READ_MIN_TEMPERATURE=0x6,
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READ_CURRENT_TEMPERATURE=0x7,
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READ_SYSTEM_VARIANT=0x8,
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READ_POWERON_CYCLES=0x9,
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READ_POWERON_SECONDS=0xA,
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READ_RESET_STATUS=0xB,
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READ_EVENT_STATUS=0xC,
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READ_REAL_TIME_CLOCK=0xD,
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READ_EXTERNAL_VGA_PORT=0xE,
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READ_MICROCONTROLLER_ROM_CHECKSUM=0xF,
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READ_ERROR_STATUS=0x10,
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READ_EXTERNAL_STATUS=0x11,
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READ_USER_CONFIGURATION_AREA=0x12,
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READ_MICROCONTROLLER_VOLTAGE=0x13,
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READ_INTERNAL_BATTERY_VOLTAGE=0x14,
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READ_DCIN_VOLTAGE=0x15,
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READ_HORIZONTAL_POINTER_VOLTAGE=0x16,
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READ_VERTICAL_POINTER_VOLTAGE=0x17,
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READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18,
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READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19,
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READ_REAL_TIME_CLOCK_ALARM=0x1A,
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READ_EVENT_STATUS_NO_RESET=0x1B,
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READ_INTERNAL_KEYBOARD_LAYOUT=0x1C,
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READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D,
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READ_EEPROM_STATUS=0x1E,
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CONTROL_LCD=0x20,
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CONTROL_BITPORT=0x21,
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SPEAKER_VOLUME=0x23,
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CONTROL_TFT_BRIGHTNESS=0x24,
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CONTROL_WATCHDOG=0x25,
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CONTROL_FACTORY_EEPROM_AREA=0x26,
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CONTROL_KBD_TIME_UNTIL_REPEAT=0x28,
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CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29,
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CONTROL_TIMEZONE=0x2A,
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CONTROL_MARK_SPACE_RATIO=0x2B,
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CONTROL_DIAGNOSTIC_MODE=0x2E,
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CONTROL_SCREEN_CONTRAST=0x2F,
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RING_BELL=0x30,
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SET_DIAGNOSTIC_STATUS=0x32,
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CLEAR_KEY_COMBINATION_TABLE=0x33,
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PERFORM_SOFTWARE_RESET=0x34,
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SET_REAL_TIME_CLOCK=0x35,
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RECALIBRATE_POINTING_STICK=0x36,
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SET_BELL_FREQUENCY=0x37,
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SET_INTERNAL_BATTERY_CHARGE_RATE=0x39,
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SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A,
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SET_REAL_TIME_CLOCK_ALARM=0x3B,
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READ_EEPROM=0x40,
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WRITE_EEPROM=0x41,
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WRITE_TO_STATUS_DISPLAY=0x42,
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DEFINE_SPECIAL_CHARACTER=0x43,
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DEFINE_KEY_COMBINATION_ENTRY=0x50,
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DEFINE_STRING_TABLE_ENTRY=0x51,
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DEFINE_STATUS_SCREEN_DISPLAY=0x52,
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PERFORM_EMU_COMMANDS=0x64,
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READ_EMU_REGISTER=0x65,
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WRITE_EMU_REGISTER=0x66,
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READ_EMU_RAM=0x67,
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WRITE_EMU_RAM=0x68,
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READ_BQ_REGISTER=0x69,
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WRITE_BQ_REGISTER=0x6A,
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SET_USER_PASSWORD=0x70,
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VERIFY_USER_PASSWORD=0x71,
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GET_SYSTEM_PASSWORD_KEY=0x72,
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VERIFY_SYSTEM_PASSWORD=0x73,
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POWER_OFF=0x82,
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POWER_RESTART=0x83,
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};
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static struct uctrl_driver {
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struct uctrl_regs __iomem *regs;
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int irq;
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int pending;
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struct uctrl_status status;
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} *global_driver;
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static void uctrl_get_event_status(struct uctrl_driver *);
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static void uctrl_get_external_status(struct uctrl_driver *);
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static long
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uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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{
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switch (cmd) {
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int
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uctrl_open(struct inode *inode, struct file *file)
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{
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mutex_lock(&uctrl_mutex);
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uctrl_get_event_status(global_driver);
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uctrl_get_external_status(global_driver);
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mutex_unlock(&uctrl_mutex);
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return 0;
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}
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static irqreturn_t uctrl_interrupt(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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static const struct file_operations uctrl_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.unlocked_ioctl = uctrl_ioctl,
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.open = uctrl_open,
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};
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static struct miscdevice uctrl_dev = {
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UCTRL_MINOR,
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"uctrl",
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&uctrl_fops
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};
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/* Wait for space to write, then write to it */
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#define WRITEUCTLDATA(value) \
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{ \
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unsigned int i; \
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for (i = 0; i < 10000; i++) { \
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if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \
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break; \
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} \
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dprintk(("write data 0x%02x\n", value)); \
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sbus_writel(value, &driver->regs->uctrl_data); \
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}
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/* Wait for something to read, read it, then clear the bit */
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#define READUCTLDATA(value) \
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{ \
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unsigned int i; \
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value = 0; \
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for (i = 0; i < 10000; i++) { \
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if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \
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break; \
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udelay(1); \
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} \
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value = sbus_readl(&driver->regs->uctrl_data); \
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dprintk(("read data 0x%02x\n", value)); \
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sbus_writel(UCTRL_STAT_RXNE_STA, &driver->regs->uctrl_stat); \
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}
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static void uctrl_do_txn(struct uctrl_driver *driver, struct uctrl_txn *txn)
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{
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int stat, incnt, outcnt, bytecnt, intr;
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u32 byte;
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stat = sbus_readl(&driver->regs->uctrl_stat);
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intr = sbus_readl(&driver->regs->uctrl_intr);
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sbus_writel(stat, &driver->regs->uctrl_stat);
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dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr));
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incnt = txn->inbits;
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outcnt = txn->outbits;
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byte = (txn->opcode << 8);
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WRITEUCTLDATA(byte);
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bytecnt = 0;
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while (incnt > 0) {
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byte = (txn->inbuf[bytecnt] << 8);
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WRITEUCTLDATA(byte);
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incnt--;
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bytecnt++;
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}
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/* Get the ack */
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READUCTLDATA(byte);
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dprintk(("ack was %x\n", (byte >> 8)));
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bytecnt = 0;
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while (outcnt > 0) {
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READUCTLDATA(byte);
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txn->outbuf[bytecnt] = (byte >> 8);
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dprintk(("set byte to %02x\n", byte));
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outcnt--;
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bytecnt++;
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}
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}
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static void uctrl_get_event_status(struct uctrl_driver *driver)
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{
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struct uctrl_txn txn;
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u8 outbits[2];
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txn.opcode = READ_EVENT_STATUS;
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txn.inbits = 0;
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txn.outbits = 2;
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txn.inbuf = NULL;
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txn.outbuf = outbits;
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uctrl_do_txn(driver, &txn);
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dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
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driver->status.event_status =
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((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff);
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dprintk(("ev is %x\n", driver->status.event_status));
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}
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static void uctrl_get_external_status(struct uctrl_driver *driver)
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{
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struct uctrl_txn txn;
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u8 outbits[2];
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int i, v;
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txn.opcode = READ_EXTERNAL_STATUS;
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txn.inbits = 0;
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txn.outbits = 2;
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txn.inbuf = NULL;
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txn.outbuf = outbits;
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uctrl_do_txn(driver, &txn);
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dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
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driver->status.external_status =
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((outbits[0] * 256) + (outbits[1]));
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dprintk(("ex is %x\n", driver->status.external_status));
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v = driver->status.external_status;
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for (i = 0; v != 0; i++, v >>= 1) {
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if (v & 1) {
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dprintk(("%s%s", " ", uctrl_extstatus[i]));
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}
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}
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dprintk(("\n"));
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}
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static int uctrl_probe(struct platform_device *op)
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{
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struct uctrl_driver *p;
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int err = -ENOMEM;
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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if (!p) {
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printk(KERN_ERR "uctrl: Unable to allocate device struct.\n");
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goto out;
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}
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p->regs = of_ioremap(&op->resource[0], 0,
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resource_size(&op->resource[0]),
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"uctrl");
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if (!p->regs) {
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printk(KERN_ERR "uctrl: Unable to map registers.\n");
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goto out_free;
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}
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p->irq = op->archdata.irqs[0];
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err = request_irq(p->irq, uctrl_interrupt, 0, "uctrl", p);
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if (err) {
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printk(KERN_ERR "uctrl: Unable to register irq.\n");
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goto out_iounmap;
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}
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err = misc_register(&uctrl_dev);
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if (err) {
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printk(KERN_ERR "uctrl: Unable to register misc device.\n");
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goto out_free_irq;
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}
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sbus_writel(UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK, &p->regs->uctrl_intr);
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printk(KERN_INFO "%pOF: uctrl regs[0x%p] (irq %d)\n",
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op->dev.of_node, p->regs, p->irq);
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uctrl_get_event_status(p);
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uctrl_get_external_status(p);
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dev_set_drvdata(&op->dev, p);
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global_driver = p;
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out:
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return err;
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out_free_irq:
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free_irq(p->irq, p);
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out_iounmap:
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of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
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out_free:
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kfree(p);
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goto out;
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}
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static int uctrl_remove(struct platform_device *op)
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{
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struct uctrl_driver *p = dev_get_drvdata(&op->dev);
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if (p) {
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misc_deregister(&uctrl_dev);
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free_irq(p->irq, p);
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of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
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kfree(p);
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}
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return 0;
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}
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static const struct of_device_id uctrl_match[] = {
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{
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.name = "uctrl",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, uctrl_match);
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static struct platform_driver uctrl_driver = {
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.driver = {
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.name = "uctrl",
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.of_match_table = uctrl_match,
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},
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.probe = uctrl_probe,
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.remove = uctrl_remove,
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};
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module_platform_driver(uctrl_driver);
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MODULE_LICENSE("GPL");
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