672 lines
16 KiB
C
672 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/**
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* PCIe SERDES driver for AM654x SoC
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*
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* Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <dt-bindings/phy/phy.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mux/consumer.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#define CMU_R07C 0x7c
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#define COMLANE_R138 0xb38
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#define VERSION 0x70
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#define COMLANE_R190 0xb90
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#define COMLANE_R194 0xb94
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#define SERDES_CTRL 0x1fd0
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#define WIZ_LANEXCTL_STS 0x1fe0
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#define TX0_DISABLE_STATE 0x4
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#define TX0_SLEEP_STATE 0x5
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#define TX0_SNOOZE_STATE 0x6
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#define TX0_ENABLE_STATE 0x7
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#define RX0_DISABLE_STATE 0x4
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#define RX0_SLEEP_STATE 0x5
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#define RX0_SNOOZE_STATE 0x6
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#define RX0_ENABLE_STATE 0x7
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#define WIZ_PLL_CTRL 0x1ff4
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#define PLL_DISABLE_STATE 0x4
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#define PLL_SLEEP_STATE 0x5
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#define PLL_SNOOZE_STATE 0x6
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#define PLL_ENABLE_STATE 0x7
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#define PLL_LOCK_TIME 100000 /* in microseconds */
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#define SLEEP_TIME 100 /* in microseconds */
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#define LANE_USB3 0x0
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#define LANE_PCIE0_LANE0 0x1
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#define LANE_PCIE1_LANE0 0x0
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#define LANE_PCIE0_LANE1 0x1
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#define SERDES_NUM_CLOCKS 3
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#define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4)
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#define AM654_SERDES_CTRL_CLKSEL_SHIFT 4
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struct serdes_am654_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
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unsigned int reg;
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int clk_id;
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struct clk_init_data clk_data;
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};
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#define to_serdes_am654_clk_mux(_hw) \
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container_of(_hw, struct serdes_am654_clk_mux, hw)
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static struct regmap_config serdes_am654_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.fast_io = true,
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};
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static const struct reg_field cmu_master_cdn_o = REG_FIELD(CMU_R07C, 24, 24);
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static const struct reg_field config_version = REG_FIELD(COMLANE_R138, 16, 23);
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static const struct reg_field l1_master_cdn_o = REG_FIELD(COMLANE_R190, 9, 9);
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static const struct reg_field cmu_ok_i_0 = REG_FIELD(COMLANE_R194, 19, 19);
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static const struct reg_field por_en = REG_FIELD(SERDES_CTRL, 29, 29);
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static const struct reg_field tx0_enable = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31);
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static const struct reg_field rx0_enable = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15);
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static const struct reg_field pll_enable = REG_FIELD(WIZ_PLL_CTRL, 29, 31);
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static const struct reg_field pll_ok = REG_FIELD(WIZ_PLL_CTRL, 28, 28);
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struct serdes_am654 {
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struct regmap *regmap;
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struct regmap_field *cmu_master_cdn_o;
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struct regmap_field *config_version;
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struct regmap_field *l1_master_cdn_o;
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struct regmap_field *cmu_ok_i_0;
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struct regmap_field *por_en;
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struct regmap_field *tx0_enable;
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struct regmap_field *rx0_enable;
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struct regmap_field *pll_enable;
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struct regmap_field *pll_ok;
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struct device *dev;
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struct mux_control *control;
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bool busy;
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u32 type;
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struct device_node *of_node;
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struct clk_onecell_data clk_data;
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struct clk *clks[SERDES_NUM_CLOCKS];
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};
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static int serdes_am654_enable_pll(struct serdes_am654 *phy)
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{
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int ret;
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u32 val;
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ret = regmap_field_write(phy->pll_enable, PLL_ENABLE_STATE);
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if (ret)
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return ret;
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return regmap_field_read_poll_timeout(phy->pll_ok, val, val, 1000,
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PLL_LOCK_TIME);
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}
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static void serdes_am654_disable_pll(struct serdes_am654 *phy)
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{
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struct device *dev = phy->dev;
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int ret;
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ret = regmap_field_write(phy->pll_enable, PLL_DISABLE_STATE);
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if (ret)
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dev_err(dev, "Failed to disable PLL\n");
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}
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static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
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{
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int ret;
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/* Enable TX */
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ret = regmap_field_write(phy->tx0_enable, TX0_ENABLE_STATE);
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if (ret)
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return ret;
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/* Enable RX */
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ret = regmap_field_write(phy->rx0_enable, RX0_ENABLE_STATE);
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if (ret)
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return ret;
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return 0;
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}
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static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
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{
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int ret;
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/* Disable TX */
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ret = regmap_field_write(phy->tx0_enable, TX0_DISABLE_STATE);
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if (ret)
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return ret;
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/* Disable RX */
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ret = regmap_field_write(phy->rx0_enable, RX0_DISABLE_STATE);
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if (ret)
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return ret;
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return 0;
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}
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static int serdes_am654_power_on(struct phy *x)
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{
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struct serdes_am654 *phy = phy_get_drvdata(x);
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struct device *dev = phy->dev;
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int ret;
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u32 val;
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ret = serdes_am654_enable_pll(phy);
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if (ret) {
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dev_err(dev, "Failed to enable PLL\n");
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return ret;
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}
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ret = serdes_am654_enable_txrx(phy);
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if (ret) {
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dev_err(dev, "Failed to enable TX RX\n");
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return ret;
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}
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return regmap_field_read_poll_timeout(phy->cmu_ok_i_0, val, val,
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SLEEP_TIME, PLL_LOCK_TIME);
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}
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static int serdes_am654_power_off(struct phy *x)
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{
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struct serdes_am654 *phy = phy_get_drvdata(x);
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serdes_am654_disable_txrx(phy);
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serdes_am654_disable_pll(phy);
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return 0;
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}
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static int serdes_am654_init(struct phy *x)
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{
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struct serdes_am654 *phy = phy_get_drvdata(x);
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int ret;
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ret = regmap_field_write(phy->config_version, VERSION);
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if (ret)
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return ret;
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ret = regmap_field_write(phy->cmu_master_cdn_o, 0x1);
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if (ret)
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return ret;
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ret = regmap_field_write(phy->l1_master_cdn_o, 0x1);
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if (ret)
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return ret;
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return 0;
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}
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static int serdes_am654_reset(struct phy *x)
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{
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struct serdes_am654 *phy = phy_get_drvdata(x);
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int ret;
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ret = regmap_field_write(phy->por_en, 0x1);
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if (ret)
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return ret;
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mdelay(1);
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ret = regmap_field_write(phy->por_en, 0x0);
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if (ret)
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return ret;
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return 0;
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}
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static void serdes_am654_release(struct phy *x)
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{
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struct serdes_am654 *phy = phy_get_drvdata(x);
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phy->type = PHY_NONE;
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phy->busy = false;
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mux_control_deselect(phy->control);
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}
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static struct phy *serdes_am654_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct serdes_am654 *am654_phy;
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struct phy *phy;
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int ret;
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phy = of_phy_simple_xlate(dev, args);
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if (IS_ERR(phy))
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return phy;
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am654_phy = phy_get_drvdata(phy);
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if (am654_phy->busy)
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return ERR_PTR(-EBUSY);
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ret = mux_control_select(am654_phy->control, args->args[1]);
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if (ret) {
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dev_err(dev, "Failed to select SERDES Lane Function\n");
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return ERR_PTR(ret);
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}
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am654_phy->busy = true;
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am654_phy->type = args->args[0];
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return phy;
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}
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static const struct phy_ops ops = {
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.reset = serdes_am654_reset,
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.init = serdes_am654_init,
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.power_on = serdes_am654_power_on,
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.power_off = serdes_am654_power_off,
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.release = serdes_am654_release,
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.owner = THIS_MODULE,
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};
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#define SERDES_NUM_MUX_COMBINATIONS 16
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#define LICLK 0
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#define EXT_REFCLK 1
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#define RICLK 2
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static const int
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serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = {
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/*
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* Each combination maps to one of
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* "Figure 12-1986. SerDes Reference Clock Distribution"
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* in TRM.
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*/
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/* Parent of CMU refclk, Left output, Right output
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* either of EXT_REFCLK, LICLK, RICLK
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*/
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{ EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */
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{ RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */
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{ EXT_REFCLK, RICLK, LICLK }, /* 0010 */
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{ RICLK, RICLK, EXT_REFCLK }, /* 0011 */
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{ LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */
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{ EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */
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{ LICLK, RICLK, LICLK }, /* 0110 */
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{ EXT_REFCLK, RICLK, LICLK }, /* 0111 */
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{ EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */
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{ RICLK, EXT_REFCLK, LICLK }, /* 1001 */
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{ EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */
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{ RICLK, RICLK, EXT_REFCLK }, /* 1011 */
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{ LICLK, EXT_REFCLK, LICLK }, /* 1100 */
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{ EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */
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{ LICLK, RICLK, EXT_REFCLK }, /* 1110 */
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{ EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */
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};
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static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
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struct regmap *regmap = mux->regmap;
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unsigned int reg = mux->reg;
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unsigned int val;
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regmap_read(regmap, reg, &val);
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val &= AM654_SERDES_CTRL_CLKSEL_MASK;
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val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
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return serdes_am654_mux_table[val][mux->clk_id];
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}
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static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
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struct regmap *regmap = mux->regmap;
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const char *name = clk_hw_get_name(hw);
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unsigned int reg = mux->reg;
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int clk_id = mux->clk_id;
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int parents[SERDES_NUM_CLOCKS];
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const int *p;
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u32 val;
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int found, i;
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int ret;
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/* get existing setting */
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regmap_read(regmap, reg, &val);
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val &= AM654_SERDES_CTRL_CLKSEL_MASK;
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val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
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for (i = 0; i < SERDES_NUM_CLOCKS; i++)
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parents[i] = serdes_am654_mux_table[val][i];
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/* change parent of this clock. others left intact */
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parents[clk_id] = index;
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/* Find the match */
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for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) {
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p = serdes_am654_mux_table[val];
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found = 1;
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for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
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if (parents[i] != p[i]) {
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found = 0;
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break;
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}
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}
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if (found)
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break;
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}
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if (!found) {
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/*
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* This can never happen, unless we missed
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* a valid combination in serdes_am654_mux_table.
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*/
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WARN(1, "Failed to find the parent of %s clock\n", name);
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return -EINVAL;
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}
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val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT;
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ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK,
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val);
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return ret;
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}
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static const struct clk_ops serdes_am654_clk_mux_ops = {
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.set_parent = serdes_am654_clk_mux_set_parent,
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.get_parent = serdes_am654_clk_mux_get_parent,
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};
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static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
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const char *clock_name, int clock_num)
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{
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struct device_node *node = am654_phy->of_node;
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struct device *dev = am654_phy->dev;
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struct serdes_am654_clk_mux *mux;
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struct device_node *regmap_node;
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const char **parent_names;
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struct clk_init_data *init;
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unsigned int num_parents;
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struct regmap *regmap;
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const __be32 *addr;
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unsigned int reg;
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struct clk *clk;
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int ret = 0;
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return -ENOMEM;
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init = &mux->clk_data;
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regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0);
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if (!regmap_node) {
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dev_err(dev, "Fail to get serdes-clk node\n");
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ret = -ENODEV;
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goto out_put_node;
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}
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regmap = syscon_node_to_regmap(regmap_node->parent);
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if (IS_ERR(regmap)) {
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dev_err(dev, "Fail to get Syscon regmap\n");
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ret = PTR_ERR(regmap);
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goto out_put_node;
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}
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 2) {
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dev_err(dev, "SERDES clock must have parents\n");
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ret = -EINVAL;
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goto out_put_node;
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}
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parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
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GFP_KERNEL);
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if (!parent_names) {
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ret = -ENOMEM;
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goto out_put_node;
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}
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of_clk_parent_fill(node, parent_names, num_parents);
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addr = of_get_address(regmap_node, 0, NULL, NULL);
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if (!addr) {
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ret = -EINVAL;
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goto out_put_node;
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}
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reg = be32_to_cpu(*addr);
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init->ops = &serdes_am654_clk_mux_ops;
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init->flags = CLK_SET_RATE_NO_REPARENT;
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init->parent_names = parent_names;
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init->num_parents = num_parents;
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init->name = clock_name;
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mux->regmap = regmap;
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mux->reg = reg;
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mux->clk_id = clock_num;
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mux->hw.init = init;
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clk = devm_clk_register(dev, &mux->hw);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto out_put_node;
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}
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am654_phy->clks[clock_num] = clk;
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out_put_node:
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of_node_put(regmap_node);
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return ret;
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}
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static const struct of_device_id serdes_am654_id_table[] = {
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{
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.compatible = "ti,phy-am654-serdes",
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, serdes_am654_id_table);
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static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy)
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{
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struct regmap *regmap = am654_phy->regmap;
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struct device *dev = am654_phy->dev;
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am654_phy->cmu_master_cdn_o = devm_regmap_field_alloc(dev, regmap,
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cmu_master_cdn_o);
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if (IS_ERR(am654_phy->cmu_master_cdn_o)) {
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dev_err(dev, "CMU_MASTER_CDN_O reg field init failed\n");
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return PTR_ERR(am654_phy->cmu_master_cdn_o);
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}
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am654_phy->config_version = devm_regmap_field_alloc(dev, regmap,
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config_version);
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if (IS_ERR(am654_phy->config_version)) {
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dev_err(dev, "CONFIG_VERSION reg field init failed\n");
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return PTR_ERR(am654_phy->config_version);
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}
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am654_phy->l1_master_cdn_o = devm_regmap_field_alloc(dev, regmap,
|
|
l1_master_cdn_o);
|
|
if (IS_ERR(am654_phy->l1_master_cdn_o)) {
|
|
dev_err(dev, "L1_MASTER_CDN_O reg field init failed\n");
|
|
return PTR_ERR(am654_phy->l1_master_cdn_o);
|
|
}
|
|
|
|
am654_phy->cmu_ok_i_0 = devm_regmap_field_alloc(dev, regmap,
|
|
cmu_ok_i_0);
|
|
if (IS_ERR(am654_phy->cmu_ok_i_0)) {
|
|
dev_err(dev, "CMU_OK_I_0 reg field init failed\n");
|
|
return PTR_ERR(am654_phy->cmu_ok_i_0);
|
|
}
|
|
|
|
am654_phy->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
|
|
if (IS_ERR(am654_phy->por_en)) {
|
|
dev_err(dev, "POR_EN reg field init failed\n");
|
|
return PTR_ERR(am654_phy->por_en);
|
|
}
|
|
|
|
am654_phy->tx0_enable = devm_regmap_field_alloc(dev, regmap,
|
|
tx0_enable);
|
|
if (IS_ERR(am654_phy->tx0_enable)) {
|
|
dev_err(dev, "TX0_ENABLE reg field init failed\n");
|
|
return PTR_ERR(am654_phy->tx0_enable);
|
|
}
|
|
|
|
am654_phy->rx0_enable = devm_regmap_field_alloc(dev, regmap,
|
|
rx0_enable);
|
|
if (IS_ERR(am654_phy->rx0_enable)) {
|
|
dev_err(dev, "RX0_ENABLE reg field init failed\n");
|
|
return PTR_ERR(am654_phy->rx0_enable);
|
|
}
|
|
|
|
am654_phy->pll_enable = devm_regmap_field_alloc(dev, regmap,
|
|
pll_enable);
|
|
if (IS_ERR(am654_phy->pll_enable)) {
|
|
dev_err(dev, "PLL_ENABLE reg field init failed\n");
|
|
return PTR_ERR(am654_phy->pll_enable);
|
|
}
|
|
|
|
am654_phy->pll_ok = devm_regmap_field_alloc(dev, regmap, pll_ok);
|
|
if (IS_ERR(am654_phy->pll_ok)) {
|
|
dev_err(dev, "PLL_OK reg field init failed\n");
|
|
return PTR_ERR(am654_phy->pll_ok);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serdes_am654_probe(struct platform_device *pdev)
|
|
{
|
|
struct phy_provider *phy_provider;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct clk_onecell_data *clk_data;
|
|
struct serdes_am654 *am654_phy;
|
|
struct mux_control *control;
|
|
const char *clock_name;
|
|
struct regmap *regmap;
|
|
void __iomem *base;
|
|
struct phy *phy;
|
|
int ret;
|
|
int i;
|
|
|
|
am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL);
|
|
if (!am654_phy)
|
|
return -ENOMEM;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config);
|
|
if (IS_ERR(regmap)) {
|
|
dev_err(dev, "Failed to initialize regmap\n");
|
|
return PTR_ERR(regmap);
|
|
}
|
|
|
|
control = devm_mux_control_get(dev, NULL);
|
|
if (IS_ERR(control))
|
|
return PTR_ERR(control);
|
|
|
|
am654_phy->dev = dev;
|
|
am654_phy->of_node = node;
|
|
am654_phy->regmap = regmap;
|
|
am654_phy->control = control;
|
|
am654_phy->type = PHY_NONE;
|
|
|
|
ret = serdes_am654_regfield_init(am654_phy);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize regfields\n");
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, am654_phy);
|
|
|
|
for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
|
|
ret = of_property_read_string_index(node, "clock-output-names",
|
|
i, &clock_name);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to get clock name\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = serdes_am654_clk_register(am654_phy, clock_name, i);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize clock %s\n",
|
|
clock_name);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
clk_data = &am654_phy->clk_data;
|
|
clk_data->clks = am654_phy->clks;
|
|
clk_data->clk_num = SERDES_NUM_CLOCKS;
|
|
ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
phy = devm_phy_create(dev, NULL, &ops);
|
|
if (IS_ERR(phy)) {
|
|
ret = PTR_ERR(phy);
|
|
goto clk_err;
|
|
}
|
|
|
|
phy_set_drvdata(phy, am654_phy);
|
|
phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate);
|
|
if (IS_ERR(phy_provider)) {
|
|
ret = PTR_ERR(phy_provider);
|
|
goto clk_err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
clk_err:
|
|
of_clk_del_provider(node);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int serdes_am654_remove(struct platform_device *pdev)
|
|
{
|
|
struct serdes_am654 *am654_phy = platform_get_drvdata(pdev);
|
|
struct device_node *node = am654_phy->of_node;
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
of_clk_del_provider(node);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver serdes_am654_driver = {
|
|
.probe = serdes_am654_probe,
|
|
.remove = serdes_am654_remove,
|
|
.driver = {
|
|
.name = "phy-am654",
|
|
.of_match_table = serdes_am654_id_table,
|
|
},
|
|
};
|
|
module_platform_driver(serdes_am654_driver);
|
|
|
|
MODULE_AUTHOR("Texas Instruments Inc.");
|
|
MODULE_DESCRIPTION("TI AM654x SERDES driver");
|
|
MODULE_LICENSE("GPL v2");
|