471 lines
11 KiB
C
471 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Wondermedia I2C Master Mode Driver
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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*
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* Derived from GPLv2+ licensed source:
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* - Copyright (C) 2008 WonderMedia Technologies, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#define REG_CR 0x00
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#define REG_TCR 0x02
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#define REG_CSR 0x04
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#define REG_ISR 0x06
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#define REG_IMR 0x08
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#define REG_CDR 0x0A
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#define REG_TR 0x0C
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#define REG_MCR 0x0E
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#define REG_SLAVE_CR 0x10
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#define REG_SLAVE_SR 0x12
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#define REG_SLAVE_ISR 0x14
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#define REG_SLAVE_IMR 0x16
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#define REG_SLAVE_DR 0x18
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#define REG_SLAVE_TR 0x1A
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/* REG_CR Bit fields */
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#define CR_TX_NEXT_ACK 0x0000
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#define CR_ENABLE 0x0001
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#define CR_TX_NEXT_NO_ACK 0x0002
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#define CR_TX_END 0x0004
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#define CR_CPU_RDY 0x0008
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#define SLAV_MODE_SEL 0x8000
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/* REG_TCR Bit fields */
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#define TCR_STANDARD_MODE 0x0000
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#define TCR_MASTER_WRITE 0x0000
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#define TCR_HS_MODE 0x2000
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#define TCR_MASTER_READ 0x4000
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#define TCR_FAST_MODE 0x8000
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#define TCR_SLAVE_ADDR_MASK 0x007F
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/* REG_ISR Bit fields */
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#define ISR_NACK_ADDR 0x0001
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#define ISR_BYTE_END 0x0002
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#define ISR_SCL_TIMEOUT 0x0004
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#define ISR_WRITE_ALL 0x0007
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/* REG_IMR Bit fields */
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#define IMR_ENABLE_ALL 0x0007
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/* REG_CSR Bit fields */
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#define CSR_RCV_NOT_ACK 0x0001
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#define CSR_RCV_ACK_MASK 0x0001
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#define CSR_READY_MASK 0x0002
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/* REG_TR */
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#define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
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#define TR_STD 0x0064
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#define TR_HS 0x0019
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/* REG_MCR */
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#define MCR_APB_96M 7
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#define MCR_APB_166M 12
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#define I2C_MODE_STANDARD 0
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#define I2C_MODE_FAST 1
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#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
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struct wmt_i2c_dev {
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struct i2c_adapter adapter;
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struct completion complete;
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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int mode;
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int irq;
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u16 cmd_status;
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};
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static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
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{
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unsigned long timeout;
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timeout = jiffies + WMT_I2C_TIMEOUT;
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while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
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if (time_after(jiffies, timeout)) {
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dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
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return -EBUSY;
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}
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msleep(20);
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}
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return 0;
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}
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static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
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{
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int ret = 0;
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if (i2c_dev->cmd_status & ISR_NACK_ADDR)
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ret = -EIO;
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if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
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ret = -ETIMEDOUT;
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return ret;
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}
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static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
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int last)
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{
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struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
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u16 val, tcr_val;
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int ret;
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unsigned long wait_result;
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int xfer_len = 0;
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if (!(pmsg->flags & I2C_M_NOSTART)) {
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ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
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if (ret < 0)
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return ret;
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}
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if (pmsg->len == 0) {
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/*
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* We still need to run through the while (..) once, so
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* start at -1 and break out early from the loop
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*/
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xfer_len = -1;
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writew(0, i2c_dev->base + REG_CDR);
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} else {
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writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
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}
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if (!(pmsg->flags & I2C_M_NOSTART)) {
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val = readw(i2c_dev->base + REG_CR);
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val &= ~CR_TX_END;
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writew(val, i2c_dev->base + REG_CR);
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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}
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reinit_completion(&i2c_dev->complete);
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if (i2c_dev->mode == I2C_MODE_STANDARD)
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tcr_val = TCR_STANDARD_MODE;
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else
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tcr_val = TCR_FAST_MODE;
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tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
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writew(tcr_val, i2c_dev->base + REG_TCR);
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if (pmsg->flags & I2C_M_NOSTART) {
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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}
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while (xfer_len < pmsg->len) {
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wait_result = wait_for_completion_timeout(&i2c_dev->complete,
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msecs_to_jiffies(500));
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if (wait_result == 0)
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return -ETIMEDOUT;
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ret = wmt_check_status(i2c_dev);
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if (ret)
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return ret;
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xfer_len++;
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val = readw(i2c_dev->base + REG_CSR);
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if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
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dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
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return -EIO;
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}
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if (pmsg->len == 0) {
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val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
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writew(val, i2c_dev->base + REG_CR);
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break;
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}
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if (xfer_len == pmsg->len) {
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if (last != 1)
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writew(CR_ENABLE, i2c_dev->base + REG_CR);
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} else {
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writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
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REG_CDR);
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writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
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}
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}
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return 0;
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}
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static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
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int last)
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{
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struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
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u16 val, tcr_val;
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int ret;
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unsigned long wait_result;
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u32 xfer_len = 0;
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if (!(pmsg->flags & I2C_M_NOSTART)) {
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ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
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if (ret < 0)
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return ret;
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}
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val = readw(i2c_dev->base + REG_CR);
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val &= ~CR_TX_END;
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writew(val, i2c_dev->base + REG_CR);
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val = readw(i2c_dev->base + REG_CR);
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val &= ~CR_TX_NEXT_NO_ACK;
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writew(val, i2c_dev->base + REG_CR);
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if (!(pmsg->flags & I2C_M_NOSTART)) {
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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}
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if (pmsg->len == 1) {
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_TX_NEXT_NO_ACK;
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writew(val, i2c_dev->base + REG_CR);
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}
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reinit_completion(&i2c_dev->complete);
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if (i2c_dev->mode == I2C_MODE_STANDARD)
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tcr_val = TCR_STANDARD_MODE;
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else
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tcr_val = TCR_FAST_MODE;
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tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
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writew(tcr_val, i2c_dev->base + REG_TCR);
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if (pmsg->flags & I2C_M_NOSTART) {
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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}
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while (xfer_len < pmsg->len) {
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wait_result = wait_for_completion_timeout(&i2c_dev->complete,
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msecs_to_jiffies(500));
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if (!wait_result)
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return -ETIMEDOUT;
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ret = wmt_check_status(i2c_dev);
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if (ret)
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return ret;
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pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
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xfer_len++;
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if (xfer_len == pmsg->len - 1) {
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val = readw(i2c_dev->base + REG_CR);
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val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
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writew(val, i2c_dev->base + REG_CR);
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} else {
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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}
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}
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return 0;
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}
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static int wmt_i2c_xfer(struct i2c_adapter *adap,
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struct i2c_msg msgs[],
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int num)
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{
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struct i2c_msg *pmsg;
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int i, is_last;
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int ret = 0;
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for (i = 0; ret >= 0 && i < num; i++) {
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is_last = ((i + 1) == num);
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pmsg = &msgs[i];
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if (pmsg->flags & I2C_M_RD)
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ret = wmt_i2c_read(adap, pmsg, is_last);
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else
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ret = wmt_i2c_write(adap, pmsg, is_last);
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}
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return (ret < 0) ? ret : i;
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}
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static u32 wmt_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
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}
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static const struct i2c_algorithm wmt_i2c_algo = {
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.master_xfer = wmt_i2c_xfer,
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.functionality = wmt_i2c_func,
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};
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static irqreturn_t wmt_i2c_isr(int irq, void *data)
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{
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struct wmt_i2c_dev *i2c_dev = data;
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/* save the status and write-clear it */
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i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
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writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
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complete(&i2c_dev->complete);
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return IRQ_HANDLED;
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}
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static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
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{
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int err;
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err = clk_prepare_enable(i2c_dev->clk);
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if (err) {
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dev_err(i2c_dev->dev, "failed to enable clock\n");
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return err;
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}
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err = clk_set_rate(i2c_dev->clk, 20000000);
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if (err) {
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dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
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clk_disable_unprepare(i2c_dev->clk);
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return err;
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}
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writew(0, i2c_dev->base + REG_CR);
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writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
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writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
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writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
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writew(CR_ENABLE, i2c_dev->base + REG_CR);
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readw(i2c_dev->base + REG_CSR); /* read clear */
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writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
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if (i2c_dev->mode == I2C_MODE_STANDARD)
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writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
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else
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writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
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return 0;
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}
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static int wmt_i2c_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct wmt_i2c_dev *i2c_dev;
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struct i2c_adapter *adap;
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struct resource *res;
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int err;
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u32 clk_rate;
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i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
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if (!i2c_dev)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(i2c_dev->base))
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return PTR_ERR(i2c_dev->base);
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i2c_dev->irq = irq_of_parse_and_map(np, 0);
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if (!i2c_dev->irq) {
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dev_err(&pdev->dev, "irq missing or invalid\n");
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return -EINVAL;
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}
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i2c_dev->clk = of_clk_get(np, 0);
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if (IS_ERR(i2c_dev->clk)) {
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dev_err(&pdev->dev, "unable to request clock\n");
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return PTR_ERR(i2c_dev->clk);
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}
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i2c_dev->mode = I2C_MODE_STANDARD;
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err = of_property_read_u32(np, "clock-frequency", &clk_rate);
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if ((!err) && (clk_rate == 400000))
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i2c_dev->mode = I2C_MODE_FAST;
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i2c_dev->dev = &pdev->dev;
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err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
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"i2c", i2c_dev);
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if (err) {
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dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
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return err;
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}
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adap = &i2c_dev->adapter;
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i2c_set_adapdata(adap, i2c_dev);
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strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
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adap->owner = THIS_MODULE;
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adap->algo = &wmt_i2c_algo;
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adap->dev.parent = &pdev->dev;
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adap->dev.of_node = pdev->dev.of_node;
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init_completion(&i2c_dev->complete);
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err = wmt_i2c_reset_hardware(i2c_dev);
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if (err) {
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dev_err(&pdev->dev, "error initializing hardware\n");
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return err;
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}
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err = i2c_add_adapter(adap);
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if (err)
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return err;
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platform_set_drvdata(pdev, i2c_dev);
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return 0;
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}
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static int wmt_i2c_remove(struct platform_device *pdev)
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{
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struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
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/* Disable interrupts, clock and delete adapter */
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writew(0, i2c_dev->base + REG_IMR);
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clk_disable_unprepare(i2c_dev->clk);
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i2c_del_adapter(&i2c_dev->adapter);
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return 0;
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}
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static const struct of_device_id wmt_i2c_dt_ids[] = {
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{ .compatible = "wm,wm8505-i2c" },
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{ /* Sentinel */ },
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};
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static struct platform_driver wmt_i2c_driver = {
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.probe = wmt_i2c_probe,
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.remove = wmt_i2c_remove,
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.driver = {
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.name = "wmt-i2c",
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.of_match_table = wmt_i2c_dt_ids,
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},
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};
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module_platform_driver(wmt_i2c_driver);
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MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
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MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
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