168 lines
3.7 KiB
C
168 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Trusted Foundations support for ARM CPUs
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*
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* Copyright (c) 2013, NVIDIA Corporation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/firmware/trusted_foundations.h>
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#include <asm/firmware.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/outercache.h>
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#define TF_CACHE_MAINT 0xfffff100
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#define TF_CACHE_ENABLE 1
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#define TF_CACHE_DISABLE 2
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#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
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#define TF_CPU_PM 0xfffffffc
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#define TF_CPU_PM_S3 0xffffffe3
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#define TF_CPU_PM_S2 0xffffffe6
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#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
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#define TF_CPU_PM_S1 0xffffffe4
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#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
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static unsigned long cpu_boot_addr;
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static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
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{
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register u32 r0 asm("r0") = type;
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register u32 r1 asm("r1") = arg1;
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register u32 r2 asm("r2") = arg2;
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asm volatile(
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".arch_extension sec\n\t"
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"stmfd sp!, {r4 - r11}\n\t"
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__asmeq("%0", "r0")
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__asmeq("%1", "r1")
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__asmeq("%2", "r2")
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"mov r3, #0\n\t"
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"mov r4, #0\n\t"
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"smc #0\n\t"
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"ldmfd sp!, {r4 - r11}\n\t"
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:
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: "r" (r0), "r" (r1), "r" (r2)
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: "memory", "r3", "r12", "lr");
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}
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static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
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{
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cpu_boot_addr = boot_addr;
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tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
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return 0;
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}
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static int tf_prepare_idle(unsigned long mode)
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{
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switch (mode) {
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case TF_PM_MODE_LP0:
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tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
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break;
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case TF_PM_MODE_LP1:
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tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
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break;
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case TF_PM_MODE_LP1_NO_MC_CLK:
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tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
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cpu_boot_addr);
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break;
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case TF_PM_MODE_LP2:
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tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
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break;
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case TF_PM_MODE_LP2_NOFLUSH_L2:
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tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
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cpu_boot_addr);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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#ifdef CONFIG_CACHE_L2X0
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static void tf_cache_write_sec(unsigned long val, unsigned int reg)
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{
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u32 l2x0_way_mask = 0xff;
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switch (reg) {
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case L2X0_CTRL:
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if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
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l2x0_way_mask = 0xffff;
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if (val == L2X0_CTRL_EN)
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tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
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l2x0_saved_regs.aux_ctrl);
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else
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tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
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l2x0_way_mask);
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break;
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default:
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break;
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}
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}
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static int tf_init_cache(void)
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{
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outer_cache.write_sec = tf_cache_write_sec;
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return 0;
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}
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#endif /* CONFIG_CACHE_L2X0 */
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static const struct firmware_ops trusted_foundations_ops = {
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.set_cpu_boot_addr = tf_set_cpu_boot_addr,
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.prepare_idle = tf_prepare_idle,
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#ifdef CONFIG_CACHE_L2X0
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.l2x0_init = tf_init_cache,
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#endif
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};
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void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
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{
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/*
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* we are not using version information for now since currently
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* supported SMCs are compatible with all TF releases
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*/
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register_firmware_ops(&trusted_foundations_ops);
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}
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void of_register_trusted_foundations(void)
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{
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struct device_node *node;
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struct trusted_foundations_platform_data pdata;
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int err;
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node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
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if (!node)
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return;
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err = of_property_read_u32(node, "tlm,version-major",
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&pdata.version_major);
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if (err != 0)
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panic("Trusted Foundation: missing version-major property\n");
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err = of_property_read_u32(node, "tlm,version-minor",
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&pdata.version_minor);
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if (err != 0)
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panic("Trusted Foundation: missing version-minor property\n");
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register_trusted_foundations(&pdata);
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}
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bool trusted_foundations_registered(void)
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{
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return firmware_ops == &trusted_foundations_ops;
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}
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