387 lines
10 KiB
C
387 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/berlin2q.h>
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#include "berlin2-div.h"
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#include "berlin2-pll.h"
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#include "common.h"
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#define REG_PINMUX0 0x0018
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#define REG_PINMUX5 0x002c
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#define REG_SYSPLLCTL0 0x0030
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#define REG_SYSPLLCTL4 0x0040
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#define REG_CLKENABLE 0x00e8
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#define REG_CLKSELECT0 0x00ec
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#define REG_CLKSELECT1 0x00f0
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#define REG_CLKSELECT2 0x00f4
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#define REG_CLKSWITCH0 0x00f8
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#define REG_CLKSWITCH1 0x00fc
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#define REG_SW_GENERIC0 0x0110
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#define REG_SW_GENERIC3 0x011c
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#define REG_SDIO0XIN_CLKCTL 0x0158
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#define REG_SDIO1XIN_CLKCTL 0x015c
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#define MAX_CLKS 28
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static struct clk_hw_onecell_data *clk_data;
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static DEFINE_SPINLOCK(lock);
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static void __iomem *gbase;
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static void __iomem *cpupll_base;
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enum {
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REFCLK,
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SYSPLL, CPUPLL,
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AVPLL_B1, AVPLL_B2, AVPLL_B3, AVPLL_B4,
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AVPLL_B5, AVPLL_B6, AVPLL_B7, AVPLL_B8,
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};
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static const char *clk_names[] = {
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[REFCLK] = "refclk",
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[SYSPLL] = "syspll",
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[CPUPLL] = "cpupll",
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[AVPLL_B1] = "avpll_b1",
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[AVPLL_B2] = "avpll_b2",
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[AVPLL_B3] = "avpll_b3",
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[AVPLL_B4] = "avpll_b4",
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[AVPLL_B5] = "avpll_b5",
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[AVPLL_B6] = "avpll_b6",
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[AVPLL_B7] = "avpll_b7",
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[AVPLL_B8] = "avpll_b8",
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};
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static const struct berlin2_pll_map bg2q_pll_map __initconst = {
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.vcodiv = {1, 0, 2, 0, 3, 4, 0, 6, 8},
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.mult = 1,
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.fbdiv_shift = 7,
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.rfdiv_shift = 2,
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.divsel_shift = 9,
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};
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static const u8 default_parent_ids[] = {
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SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL
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};
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static const struct berlin2_div_data bg2q_divs[] __initconst = {
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{
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.name = "sys",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 0),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = CLK_IGNORE_UNUSED,
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},
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{
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.name = "drmfigo",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 17),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 6),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 7),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 8),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "cfg",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 1),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 12),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 15),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 9),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 10),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 11),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "gfx2d",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 4),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 18),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 21),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 12),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 13),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 14),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "zsp",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 6),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 24),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 27),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 15),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 16),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 17),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "perif",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 7),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 0),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 3),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 19),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 20),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = CLK_IGNORE_UNUSED,
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},
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{
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.name = "pcube",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 2),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 6),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 9),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 22),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 23),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "vscope",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 3),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 12),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 15),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 24),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 25),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 26),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "nfc_ecc",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 19),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 18),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 21),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 27),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 28),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 29),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "vpp",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 21),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 24),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 27),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 30),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 31),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 0),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "app",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 20),
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BERLIN2_PLL_SELECT(REG_CLKSELECT2, 0),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 3),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 1),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 2),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 3),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "sdio0xin",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_SDIO0XIN_CLKCTL),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "sdio1xin",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_SDIO1XIN_CLKCTL),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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};
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static const struct berlin2_gate_data bg2q_gates[] __initconst = {
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{ "gfx2daxi", "perif", 5 },
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{ "geth0", "perif", 8 },
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{ "sata", "perif", 9 },
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{ "ahbapb", "perif", 10, CLK_IGNORE_UNUSED },
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{ "usb0", "perif", 11 },
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{ "usb1", "perif", 12 },
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{ "usb2", "perif", 13 },
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{ "usb3", "perif", 14 },
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{ "pbridge", "perif", 15, CLK_IGNORE_UNUSED },
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{ "sdio", "perif", 16 },
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{ "nfc", "perif", 18 },
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{ "pcie", "perif", 22 },
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};
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static void __init berlin2q_clock_setup(struct device_node *np)
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{
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struct device_node *parent_np = of_get_parent(np);
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const char *parent_names[9];
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struct clk *clk;
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struct clk_hw **hws;
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int n, ret;
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clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
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if (!clk_data) {
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of_node_put(parent_np);
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return;
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}
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clk_data->num = MAX_CLKS;
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hws = clk_data->hws;
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gbase = of_iomap(parent_np, 0);
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if (!gbase) {
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of_node_put(parent_np);
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pr_err("%pOF: Unable to map global base\n", np);
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return;
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}
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/* BG2Q CPU PLL is not part of global registers */
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cpupll_base = of_iomap(parent_np, 1);
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of_node_put(parent_np);
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if (!cpupll_base) {
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pr_err("%pOF: Unable to map cpupll base\n", np);
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iounmap(gbase);
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return;
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}
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/* overwrite default clock names with DT provided ones */
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clk = of_clk_get_by_name(np, clk_names[REFCLK]);
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if (!IS_ERR(clk)) {
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clk_names[REFCLK] = __clk_get_name(clk);
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clk_put(clk);
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}
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/* simple register PLLs */
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ret = berlin2_pll_register(&bg2q_pll_map, gbase + REG_SYSPLLCTL0,
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clk_names[SYSPLL], clk_names[REFCLK], 0);
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if (ret)
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goto bg2q_fail;
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ret = berlin2_pll_register(&bg2q_pll_map, cpupll_base,
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clk_names[CPUPLL], clk_names[REFCLK], 0);
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if (ret)
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goto bg2q_fail;
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/* TODO: add BG2Q AVPLL */
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/*
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* TODO: add reference clock bypass switches:
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* memPLLSWBypass, cpuPLLSWBypass, and sysPLLSWBypass
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*/
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/* clock divider cells */
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for (n = 0; n < ARRAY_SIZE(bg2q_divs); n++) {
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const struct berlin2_div_data *dd = &bg2q_divs[n];
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int k;
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for (k = 0; k < dd->num_parents; k++)
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parent_names[k] = clk_names[dd->parent_ids[k]];
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hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
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dd->name, dd->div_flags, parent_names,
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dd->num_parents, dd->flags, &lock);
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}
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/* clock gate cells */
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for (n = 0; n < ARRAY_SIZE(bg2q_gates); n++) {
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const struct berlin2_gate_data *gd = &bg2q_gates[n];
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hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name,
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gd->parent_name, gd->flags, gbase + REG_CLKENABLE,
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gd->bit_idx, 0, &lock);
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}
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/* cpuclk divider is fixed to 1 */
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hws[CLKID_CPU] =
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clk_hw_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],
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0, 1, 1);
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/* twdclk is derived from cpu/3 */
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hws[CLKID_TWD] =
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clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
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/* check for errors on leaf clocks */
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for (n = 0; n < MAX_CLKS; n++) {
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if (!IS_ERR(hws[n]))
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continue;
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pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
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goto bg2q_fail;
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}
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/* register clk-provider */
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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return;
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bg2q_fail:
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iounmap(cpupll_base);
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iounmap(gbase);
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}
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CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
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berlin2q_clock_setup);
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