89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Setting up the clock on MSP SOCs. No RTC typically.
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* ########################################################################
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*/
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/ptrace.h>
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#include <asm/cevt-r4k.h>
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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#include <msp_prom.h>
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#include <msp_int.h>
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#include <msp_regs.h>
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#define get_current_vpe() \
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((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
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static struct irqaction timer_vpe1;
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static int tim_installed;
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void __init plat_time_init(void)
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{
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char *endp, *s;
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unsigned long cpu_rate = 0;
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if (cpu_rate == 0) {
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s = prom_getenv("clkfreqhz");
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cpu_rate = simple_strtoul(s, &endp, 10);
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if (endp != NULL && *endp != 0) {
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printk(KERN_ERR
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"Clock rate in Hz parse error: %s\n", s);
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cpu_rate = 0;
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}
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}
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if (cpu_rate == 0) {
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s = prom_getenv("clkfreq");
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cpu_rate = 1000 * simple_strtoul(s, &endp, 10);
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if (endp != NULL && *endp != 0) {
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printk(KERN_ERR
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"Clock rate in MHz parse error: %s\n", s);
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cpu_rate = 0;
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}
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}
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if (cpu_rate == 0) {
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#if defined(CONFIG_PMC_MSP7120_EVAL) \
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|| defined(CONFIG_PMC_MSP7120_GW)
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cpu_rate = 400000000;
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#elif defined(CONFIG_PMC_MSP7120_FPGA)
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cpu_rate = 25000000;
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#else
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cpu_rate = 150000000;
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#endif
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printk(KERN_ERR
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"Failed to determine CPU clock rate, "
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"assuming %ld hz ...\n", cpu_rate);
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}
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printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate);
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/* timer frequency is 1/2 clock rate */
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mips_hpt_frequency = cpu_rate/2;
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}
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unsigned int get_c0_compare_int(void)
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{
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/* MIPS_MT modes may want timer for second VPE */
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if ((get_current_vpe()) && !tim_installed) {
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memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1));
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setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1);
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tim_installed++;
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}
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return get_current_vpe() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER;
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}
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