134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/lib/copypage-xscale.S
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*
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* Copyright (C) 1995-2005 Russell King
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*
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* This handles the mini data cache, as found on SA11x0 and XScale
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* processors. When we copy a user page page, we map it in such a way
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* that accesses to this page will not touch the main data cache, but
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* will be cached in the mini data cache. This prevents us thrashing
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* the main data cache on page faults.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include "mm.h"
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#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
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L_PTE_MT_MINICACHE)
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static DEFINE_RAW_SPINLOCK(minicache_lock);
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/*
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* XScale mini-dcache optimised copy_user_highpage
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*
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* We flush the destination cache lines just before we write the data into the
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* corresponding address. Since the Dcache is read-allocate, this removes the
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* Dcache aliasing issue. The writes will be forwarded to the write buffer,
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* and merged as appropriate.
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*/
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static void mc_copy_user_page(void *from, void *to)
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{
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int tmp;
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/*
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* Strangely enough, best performance is achieved
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* when prefetching destination as well. (NP)
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*/
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asm volatile ("\
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.arch xscale \n\
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pld [%0, #0] \n\
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pld [%0, #32] \n\
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pld [%1, #0] \n\
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pld [%1, #32] \n\
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1: pld [%0, #64] \n\
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pld [%0, #96] \n\
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pld [%1, #64] \n\
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pld [%1, #96] \n\
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2: ldrd r2, r3, [%0], #8 \n\
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ldrd r4, r5, [%0], #8 \n\
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mov ip, %1 \n\
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strd r2, r3, [%1], #8 \n\
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ldrd r2, r3, [%0], #8 \n\
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strd r4, r5, [%1], #8 \n\
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ldrd r4, r5, [%0], #8 \n\
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strd r2, r3, [%1], #8 \n\
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strd r4, r5, [%1], #8 \n\
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mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
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ldrd r2, r3, [%0], #8 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
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ldrd r4, r5, [%0], #8 \n\
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mov ip, %1 \n\
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strd r2, r3, [%1], #8 \n\
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ldrd r2, r3, [%0], #8 \n\
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strd r4, r5, [%1], #8 \n\
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ldrd r4, r5, [%0], #8 \n\
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strd r2, r3, [%1], #8 \n\
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strd r4, r5, [%1], #8 \n\
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mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
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subs %2, %2, #1 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
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bgt 1b \n\
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beq 2b "
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: "+&r" (from), "+&r" (to), "=&r" (tmp)
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: "2" (PAGE_SIZE / 64 - 1)
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: "r2", "r3", "r4", "r5", "ip");
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}
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void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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void *kto = kmap_atomic(to);
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if (!test_and_set_bit(PG_dcache_clean, &from->flags))
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__flush_dcache_page(page_mapping_file(from), from);
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raw_spin_lock(&minicache_lock);
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set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot));
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mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
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raw_spin_unlock(&minicache_lock);
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kunmap_atomic(kto);
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}
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/*
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* XScale optimised clear_user_page
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*/
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void
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xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
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{
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void *ptr, *kaddr = kmap_atomic(page);
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asm volatile("\
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.arch xscale \n\
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mov r1, %2 \n\
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mov r2, #0 \n\
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mov r3, #0 \n\
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1: mov ip, %0 \n\
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strd r2, r3, [%0], #8 \n\
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strd r2, r3, [%0], #8 \n\
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strd r2, r3, [%0], #8 \n\
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strd r2, r3, [%0], #8 \n\
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mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
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subs r1, r1, #1 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
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bne 1b"
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: "=r" (ptr)
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: "0" (kaddr), "I" (PAGE_SIZE / 32)
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: "r1", "r2", "r3", "ip");
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kunmap_atomic(kaddr);
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}
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struct cpu_user_fns xscale_mc_user_fns __initdata = {
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.cpu_clear_user_highpage = xscale_mc_clear_user_highpage,
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.cpu_copy_user_highpage = xscale_mc_copy_user_highpage,
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};
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