218 lines
13 KiB
C
218 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* OMAP44xx CM1 instance offset macros
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*
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* Copyright (C) 2009-2011 Texas Instruments, Inc.
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Paul Walmsley (paul@pwsan.com)
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* Rajendra Nayak (rnayak@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
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* or "OMAP4430".
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
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/* CM1 base address */
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#define OMAP4430_CM1_BASE 0x4a004000
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#define OMAP44XX_CM1_REGADDR(inst, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
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/* CM1 instances */
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#define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
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#define OMAP4430_CM1_CKGEN_INST 0x0100
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#define OMAP4430_CM1_MPU_INST 0x0300
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#define OMAP4430_CM1_TESLA_INST 0x0400
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#define OMAP4430_CM1_ABE_INST 0x0500
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#define OMAP4430_CM1_RESTORE_INST 0x0e00
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#define OMAP4430_CM1_INSTR_INST 0x0f00
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/* CM1 clockdomain register offsets (from instance start) */
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#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
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#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
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#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
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/* CM1 */
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/* CM1.OCP_SOCKET_CM1 register offsets */
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#define OMAP4_REVISION_CM1_OFFSET 0x0000
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#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
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#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
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#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
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/* CM1.CKGEN_CM1 register offsets */
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#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
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#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
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#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
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#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
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#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
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#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
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#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
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#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
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#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
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#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
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#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
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#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
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#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
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#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
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#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
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#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
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#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
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#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
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#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
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#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
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#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
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#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
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#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
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#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
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#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
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#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
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#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
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#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
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#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
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#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
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#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
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#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
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#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
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#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
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#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
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#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
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#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
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#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
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#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
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#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
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#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
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#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
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#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
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#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
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#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
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#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
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#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
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#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
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#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
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#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
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#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
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#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
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#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
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#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
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#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
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#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
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#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
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#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
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#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
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#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
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#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
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#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
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#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
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#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
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#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
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#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
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#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
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#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
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#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
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#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
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#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
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#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
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#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
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#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
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#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
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#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
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#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
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#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
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#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
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#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
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#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
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#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
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#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
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#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
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#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
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#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
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#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
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#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
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#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
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#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
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#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
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#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
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#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
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#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
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#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
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#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
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#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
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#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
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#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
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#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
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/* CM1.MPU_CM1 register offsets */
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#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
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#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
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#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
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#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
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#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
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#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
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#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
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#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
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/* CM1.TESLA_CM1 register offsets */
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#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
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#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
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#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
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#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
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#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
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#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
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#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
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#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
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/* CM1.ABE_CM1 register offsets */
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#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
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#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
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#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
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#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
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#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
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#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
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#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
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#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
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#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
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#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
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#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
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#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
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#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
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#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
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#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
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#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
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#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
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#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
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#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
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#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
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#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
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#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
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#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
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#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
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#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
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#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
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#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
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#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
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#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
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#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
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#endif
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