416 lines
10 KiB
C
416 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP1/OMAP7xx - specific DMA driver
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*
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* Copyright (C) 2003 - 2008 Nokia Corporation
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
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* Graphics DMA and LCD DMA graphics tranformations
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* by Imre Deak <imre.deak@nokia.com>
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* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
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* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Converted DMA library into platform driver
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* - G, Manjunath Kondaiah <manjugk@ti.com>
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*/
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/omap-dma.h>
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#include <mach/tc.h>
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#include "soc.h"
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#define OMAP1_DMA_BASE (0xfffed800)
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static u32 enable_1510_mode;
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static const struct omap_dma_reg reg_map[] = {
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[GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
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[GSCR] = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
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[GRST1] = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
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[HW_ID] = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
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[PCH2_ID] = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
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[PCH0_ID] = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
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[PCH1_ID] = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
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[PCHG_ID] = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
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[PCHD_ID] = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
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[CAPS_0] = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
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[CAPS_1] = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
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[CAPS_2] = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
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[CAPS_3] = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
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[CAPS_4] = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
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[PCH2_SR] = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
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[PCH0_SR] = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
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[PCH1_SR] = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
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[PCHD_SR] = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
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/* Common Registers */
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[CSDP] = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
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[CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
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[CICR] = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
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[CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
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[CEN] = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
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[CFN] = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
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[CSFI] = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
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[CSEI] = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
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[CPC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
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[CSAC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
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[CDAC] = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
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[CDEI] = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
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[CDFI] = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
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[CLNK_CTRL] = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
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/* Channel specific register offsets */
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[CSSA] = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
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[CDSA] = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
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[COLOR] = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
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[CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
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[LCH_CTRL] = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
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};
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static struct resource res[] __initdata = {
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[0] = {
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.start = OMAP1_DMA_BASE,
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.end = OMAP1_DMA_BASE + SZ_2K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.name = "0",
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.start = INT_DMA_CH0_6,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.name = "1",
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.start = INT_DMA_CH1_7,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.name = "2",
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.start = INT_DMA_CH2_8,
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.flags = IORESOURCE_IRQ,
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},
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[4] = {
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.name = "3",
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.start = INT_DMA_CH3,
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.flags = IORESOURCE_IRQ,
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},
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[5] = {
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.name = "4",
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.start = INT_DMA_CH4,
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.flags = IORESOURCE_IRQ,
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},
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[6] = {
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.name = "5",
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.start = INT_DMA_CH5,
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.flags = IORESOURCE_IRQ,
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},
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/* Handled in lcd_dma.c */
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[7] = {
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.name = "6",
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.start = INT_1610_DMA_CH6,
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.flags = IORESOURCE_IRQ,
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},
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/* irq's for omap16xx and omap7xx */
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[8] = {
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.name = "7",
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.start = INT_1610_DMA_CH7,
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.flags = IORESOURCE_IRQ,
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},
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[9] = {
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.name = "8",
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.start = INT_1610_DMA_CH8,
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.flags = IORESOURCE_IRQ,
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},
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[10] = {
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.name = "9",
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.start = INT_1610_DMA_CH9,
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.flags = IORESOURCE_IRQ,
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},
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[11] = {
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.name = "10",
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.start = INT_1610_DMA_CH10,
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.flags = IORESOURCE_IRQ,
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},
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[12] = {
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.name = "11",
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.start = INT_1610_DMA_CH11,
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.flags = IORESOURCE_IRQ,
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},
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[13] = {
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.name = "12",
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.start = INT_1610_DMA_CH12,
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.flags = IORESOURCE_IRQ,
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},
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[14] = {
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.name = "13",
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.start = INT_1610_DMA_CH13,
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.flags = IORESOURCE_IRQ,
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},
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[15] = {
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.name = "14",
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.start = INT_1610_DMA_CH14,
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.flags = IORESOURCE_IRQ,
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},
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[16] = {
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.name = "15",
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.start = INT_1610_DMA_CH15,
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.flags = IORESOURCE_IRQ,
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},
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[17] = {
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.name = "16",
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.start = INT_DMA_LCD,
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.flags = IORESOURCE_IRQ,
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},
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};
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static void __iomem *dma_base;
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static inline void dma_write(u32 val, int reg, int lch)
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{
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void __iomem *addr = dma_base;
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addr += reg_map[reg].offset;
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addr += reg_map[reg].stride * lch;
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__raw_writew(val, addr);
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if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
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__raw_writew(val >> 16, addr + 2);
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}
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static inline u32 dma_read(int reg, int lch)
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{
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void __iomem *addr = dma_base;
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uint32_t val;
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addr += reg_map[reg].offset;
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addr += reg_map[reg].stride * lch;
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val = __raw_readw(addr);
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if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
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val |= __raw_readw(addr + 2) << 16;
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return val;
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}
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static void omap1_clear_lch_regs(int lch)
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{
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int i;
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for (i = CPC; i <= COLOR; i += 1)
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dma_write(0, i, lch);
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}
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static void omap1_clear_dma(int lch)
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{
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u32 l;
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l = dma_read(CCR, lch);
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l &= ~OMAP_DMA_CCR_EN;
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dma_write(l, CCR, lch);
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/* Clear pending interrupts */
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l = dma_read(CSR, lch);
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}
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static void omap1_show_dma_caps(void)
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{
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if (enable_1510_mode) {
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printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
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} else {
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u16 w;
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printk(KERN_INFO "OMAP DMA hardware version %d\n",
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dma_read(HW_ID, 0));
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printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
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dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
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dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
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dma_read(CAPS_4, 0));
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/* Disable OMAP 3.0/3.1 compatibility mode. */
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w = dma_read(GSCR, 0);
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w |= 1 << 3;
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dma_write(w, GSCR, 0);
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}
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}
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static unsigned configure_dma_errata(void)
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{
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unsigned errata = 0;
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/*
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* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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if (!cpu_is_omap15xx())
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SET_DMA_ERRATA(DMA_ERRATA_3_3);
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return errata;
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}
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static const struct platform_device_info omap_dma_dev_info = {
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.name = "omap-dma-engine",
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.id = -1,
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.dma_mask = DMA_BIT_MASK(32),
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.res = res,
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.num_res = 1,
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};
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/* OMAP730, OMAP850 */
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static const struct dma_slave_map omap7xx_sdma_map[] = {
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{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
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{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
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{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) },
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{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) },
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{ "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
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{ "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
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{ "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
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{ "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
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{ "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
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{ "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
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{ "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
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{ "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
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};
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/* OMAP1510, OMAP1610*/
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static const struct dma_slave_map omap1xxx_sdma_map[] = {
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{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
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{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
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{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(10) },
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{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(11) },
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{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(16) },
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{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(17) },
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{ "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
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{ "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
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{ "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
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{ "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
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{ "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
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{ "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
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{ "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
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{ "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
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{ "mmci-omap.1", "tx", SDMA_FILTER_PARAM(54) },
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{ "mmci-omap.1", "rx", SDMA_FILTER_PARAM(55) },
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};
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static struct omap_system_dma_plat_info dma_plat_info __initdata = {
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.reg_map = reg_map,
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.channel_stride = 0x40,
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.show_dma_caps = omap1_show_dma_caps,
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.clear_lch_regs = omap1_clear_lch_regs,
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.clear_dma = omap1_clear_dma,
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.dma_write = dma_write,
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.dma_read = dma_read,
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};
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static int __init omap1_system_dma_init(void)
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{
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struct omap_system_dma_plat_info p;
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struct omap_dma_dev_attr *d;
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struct platform_device *pdev, *dma_pdev;
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int ret;
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pdev = platform_device_alloc("omap_dma_system", 0);
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if (!pdev) {
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pr_err("%s: Unable to device alloc for dma\n",
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__func__);
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return -ENOMEM;
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}
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dma_base = ioremap(res[0].start, resource_size(&res[0]));
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if (!dma_base) {
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pr_err("%s: Unable to ioremap\n", __func__);
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ret = -ENODEV;
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goto exit_device_put;
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}
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ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_iounmap;
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}
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d = kzalloc(sizeof(*d), GFP_KERNEL);
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if (!d) {
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ret = -ENOMEM;
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goto exit_iounmap;
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}
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/* Valid attributes for omap1 plus processors */
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if (cpu_is_omap15xx())
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d->dev_caps = ENABLE_1510_MODE;
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enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
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if (cpu_is_omap16xx())
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d->dev_caps = ENABLE_16XX_MODE;
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d->dev_caps |= SRC_PORT;
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d->dev_caps |= DST_PORT;
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d->dev_caps |= SRC_INDEX;
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d->dev_caps |= DST_INDEX;
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d->dev_caps |= IS_BURST_ONLY4;
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d->dev_caps |= CLEAR_CSR_ON_READ;
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d->dev_caps |= IS_WORD_16;
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/* available logical channels */
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if (cpu_is_omap15xx()) {
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d->lch_count = 9;
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} else {
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if (d->dev_caps & ENABLE_1510_MODE)
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d->lch_count = 9;
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else
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d->lch_count = 16;
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}
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p = dma_plat_info;
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p.dma_attr = d;
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p.errata = configure_dma_errata();
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if (cpu_is_omap7xx()) {
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p.slave_map = omap7xx_sdma_map;
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p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map);
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} else {
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p.slave_map = omap1xxx_sdma_map;
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p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
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}
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ret = platform_device_add_data(pdev, &p, sizeof(p));
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_release_d;
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}
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ret = platform_device_add(pdev);
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_release_d;
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}
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dma_pdev = platform_device_register_full(&omap_dma_dev_info);
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if (IS_ERR(dma_pdev)) {
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ret = PTR_ERR(dma_pdev);
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goto exit_release_pdev;
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}
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return ret;
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exit_release_pdev:
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platform_device_del(pdev);
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exit_release_d:
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kfree(d);
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exit_iounmap:
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iounmap(dma_base);
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exit_device_put:
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platform_device_put(pdev);
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return ret;
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}
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arch_initcall(omap1_system_dma_init);
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