70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Original code:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* Mostly rewritten in C by Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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/**
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* Flush per-VMID TLBs
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*
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* __kvm_tlb_flush_vmid(struct kvm *kvm);
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*
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* We rely on the hardware to broadcast the TLB invalidation to all CPUs
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* inside the inner-shareable domain (which is the case for all v7
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* implementations). If we come across a non-IS SMP implementation, we'll
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* have to use an IPI based mechanism. Until then, we stick to the simple
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* hardware assisted version.
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*
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* As v7 does not support flushing per IPA, just nuke the whole TLB
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* instead, ignoring the ipa value.
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*/
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void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm_get_vttbr(kvm), VTTBR);
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isb();
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write_sysreg(0, TLBIALLIS);
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dsb(ish);
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isb();
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write_sysreg(0, VTTBR);
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}
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void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
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{
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__kvm_tlb_flush_vmid(kvm);
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}
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void __hyp_text __kvm_flush_cpu_context(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
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/* Switch to requested VMID */
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write_sysreg(kvm_get_vttbr(kvm), VTTBR);
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isb();
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write_sysreg(0, TLBIALL);
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write_sysreg(0, ICIALLU);
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dsb(nsh);
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isb();
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write_sysreg(0, VTTBR);
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}
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void __hyp_text __kvm_flush_vm_context(void)
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{
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write_sysreg(0, TLBIALLNSNHIS);
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write_sysreg(0, ICIALLUIS);
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dsb(ish);
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}
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