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507 Commits

Author SHA1 Message Date
Linus Torvalds e6b5be2be4 Driver core patches for 3.19-rc1
Here's the set of driver core patches for 3.19-rc1.
 
 They are dominated by the removal of the .owner field in platform
 drivers.  They touch a lot of files, but they are "simple" changes, just
 removing a line in a structure.
 
 Other than that, a few minor driver core and debugfs changes.  There are
 some ath9k patches coming in through this tree that have been acked by
 the wireless maintainers as they relied on the debugfs changes.
 
 Everything has been in linux-next for a while.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core

Pull driver core update from Greg KH:
 "Here's the set of driver core patches for 3.19-rc1.

  They are dominated by the removal of the .owner field in platform
  drivers.  They touch a lot of files, but they are "simple" changes,
  just removing a line in a structure.

  Other than that, a few minor driver core and debugfs changes.  There
  are some ath9k patches coming in through this tree that have been
  acked by the wireless maintainers as they relied on the debugfs
  changes.

  Everything has been in linux-next for a while"

* tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits)
  Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries"
  fs: debugfs: add forward declaration for struct device type
  firmware class: Deletion of an unnecessary check before the function call "vunmap"
  firmware loader: fix hung task warning dump
  devcoredump: provide a one-way disable function
  device: Add dev_<level>_once variants
  ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries
  ath: use seq_file api for ath9k debugfs files
  debugfs: add helper function to create device related seq_file
  drivers/base: cacheinfo: remove noisy error boot message
  Revert "core: platform: add warning if driver has no owner"
  drivers: base: support cpu cache information interface to userspace via sysfs
  drivers: base: add cpu_device_create to support per-cpu devices
  topology: replace custom attribute macros with standard DEVICE_ATTR*
  cpumask: factor out show_cpumap into separate helper function
  driver core: Fix unbalanced device reference in drivers_probe
  driver core: fix race with userland in device_add()
  sysfs/kernfs: make read requests on pre-alloc files use the buffer.
  sysfs/kernfs: allow attributes to request write buffer be pre-allocated.
  fs: sysfs: return EGBIG on write if offset is larger than file size
  ...
2014-12-14 16:10:09 -08:00
Krzysztof Kozlowski c31844ffdb clk: samsung: Fix double add of syscore ops after driver rebind
During driver unbind the syscore ops were not unregistered which lead to
double add on syscore list:

$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind
$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind
[ 1463.044061] ------------[ cut here ]------------
[ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0()
[ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84.
[ 1463.061625] Modules linked in:
[ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G        W      3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022
[ 1463.075338] [<c0014e2c>] (unwind_backtrace) from [<c0011d80>] (show_stack+0x10/0x14)
[ 1463.083046] [<c0011d80>] (show_stack) from [<c048bb70>] (dump_stack+0x70/0xbc)
[ 1463.090236] [<c048bb70>] (dump_stack) from [<c00233d4>] (warn_slowpath_common+0x74/0xb0)
[ 1463.098295] [<c00233d4>] (warn_slowpath_common) from [<c00234a4>] (warn_slowpath_fmt+0x30/0x40)
[ 1463.106962] [<c00234a4>] (warn_slowpath_fmt) from [<c020fe80>] (__list_add+0x8c/0xc0)
[ 1463.114760] [<c020fe80>] (__list_add) from [<c0282094>] (register_syscore_ops+0x30/0x3c)
[ 1463.122819] [<c0282094>] (register_syscore_ops) from [<c0392f20>] (exynos_audss_clk_probe+0x36c/0x460)
[ 1463.132091] [<c0392f20>] (exynos_audss_clk_probe) from [<c0283084>] (platform_drv_probe+0x48/0xa4)
[ 1463.141013] [<c0283084>] (platform_drv_probe) from [<c0281a14>] (driver_probe_device+0x13c/0x37c)
[ 1463.149852] [<c0281a14>] (driver_probe_device) from [<c0280560>] (bind_store+0x90/0xe0)
[ 1463.157822] [<c0280560>] (bind_store) from [<c027fd10>] (drv_attr_store+0x20/0x2c)
[ 1463.165363] [<c027fd10>] (drv_attr_store) from [<c0143898>] (sysfs_kf_write+0x4c/0x50)
[ 1463.173252] [<c0143898>] (sysfs_kf_write) from [<c0142c80>] (kernfs_fop_write+0xbc/0x198)
[ 1463.181395] [<c0142c80>] (kernfs_fop_write) from [<c00e2be0>] (vfs_write+0xa0/0x1a8)
[ 1463.189104] [<c00e2be0>] (vfs_write) from [<c00e2f00>] (SyS_write+0x40/0x8c)
[ 1463.196122] [<c00e2f00>] (SyS_write) from [<c000f2a0>] (ret_fast_syscall+0x0/0x48)
[ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]---
[ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Fixes: 1241ef94cc ("clk: samsung: register audio subsystem clocks using common clock framework")
Cc: <stable@vger.kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:22:59 +01:00
Andrzej Hajda df019a5c0f clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock.
The patch models this dependency using parent/child hirerarchy.

The patch fixes issue with system hangs during mixer device access, mixer uses
sclk_hdmiphy descendant clock.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:22:58 +01:00
Krzysztof Kozlowski b5f56e14c1 clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
Fix following build errors when PM_SLEEP is disabled (e.g. by disabling
SUSPEND and HIBERNATION):

drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_init’:
drivers/clk/samsung/clk-exynos4415.c:982:2: error: ‘exynos4415_ctx’ undeclared (first use in this function)
drivers/clk/samsung/clk-exynos4415.c:982:2: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_dmc_init’:
drivers/clk/samsung/clk-exynos4415.c:1123:2: error: ‘exynos4415_dmc_ctx’ undeclared (first use in this function)
make[3]: *** [drivers/clk/samsung/clk-exynos4415.o] Error 1

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:22:58 +01:00
Pankaj Dubey 8b2f63606a clk: samsung: remove unnecessary inclusion of header files from clk.h
Let's remove unnecessary include of header files from clk.h and add
required one in clk.c

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
[s.nawrocki@samsung.com: dropped removal of '#include <linux/syscore_ops.h>']
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:21:37 +01:00
Pankaj Dubey 7882857e98 clk: samsung: remove unnecessary CONFIG_OF from clk.c
Remove unnecessary CONFIG_OF from samsung/clk.c.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 12:28:24 +01:00
Pankaj Dubey 2e41b9fc11 clk: samsung: Spelling s/bwtween/between/
Fix a typo in comment section of "struct samsung_clk_provider".

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 12:28:20 +01:00
Pankaj Dubey 5e6473f422 clk: exynos5440: move restart code into clock driver
Let's register restart handler for Exynos5440 from it's clock driver
for restart functionality. So that we can cleanup restart hooks from
machine specific file.

CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22 23:07:21 +09:00
Abhilash Kesavan 932e98224d clk: samsung: exynos7: add gate clock for ADC block
Add clock support for the ADC interface in Exynos7.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:54 +01:00
Naveen Krishna Ch 2ab2dfe5d4 clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:53 +01:00
Naveen Krishna Ch f5e127cd5e clk: samsung: exynos7: add clocks for RTC block
Add clock support for the RTC block in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:52 +01:00
Naveen Krishna Ch 6d0c8c723f clk: samsung: exynos7: add clocks for MMC block
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:51 +01:00
Naveen Krishna Ch 57a2b485fa clk: samsung: exynos7: add clocks for I2C block
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:51 +01:00
Naveen Krishna Ch 532abc3a4a clk: samsung: add initial clock support for Exynos7 SoC
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:47 +01:00
Naveen Krishna Ch 0e5af27008 clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info
Add the fields "fixed_factor_clks" and "nr_fixed_factor_clks" to
"struct exynos_cmu_info" to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:46 +01:00
Naveen Krishna Ch 16a9013b83 clk: samsung: Factor out the common code to clk.c
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:45 +01:00
Naveen Krishna Ch 0c23e2af67 clk: samsung: add support for 145xx and 1460x PLLs
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:35 +01:00
Chanwoo Choi 384cb2ce81 clk: samsung: exynos4415: Add clocks using common clock framework
This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using
common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU,
busses and function clocks for individual IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-30 19:53:04 +01:00
Wolfram Sang c8da4a0ec6 clk: samsung: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:22 +02:00
Mike Turquette a797900950 Allow parent rate changes for i2s on rk3288
and rockchip as well as s3c24xx restart handlers.
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Merge tag 'v3.18-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Allow parent rate changes for i2s on rk3288
and rockchip as well as s3c24xx restart handlers.
2014-10-01 11:19:10 -07:00
Heiko Stübner e317c19470 clk: samsung: register restart handlers for s3c2412 and s3c2443
S3C2412, S3C2443 and their derivatives contain a special software-reset
register in their system-controller.

Therefore register a restart handler for those.

Tested on a s3c2416-based board, s3c2412 compile-tested.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-10-01 14:14:46 +02:00
Mike Turquette 24afc3852e Samsung clock patches for v3.18
1) non-critical fixes (without the need to push to stable)
 
 fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
 b511593d71 clk: samsung: exynos4: fix g3d clocks
 c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
 22842d244a clk: samsung: exynos5260: fix typo in clock name
 e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
 59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
 5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list
 
 2) Clock driver extensions
 
 07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
 d0e73eaf19 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
 e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
 4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
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Merge tag 'for_3.18/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next

Samsung clock patches for v3.18

1) non-critical fixes (without the need to push to stable)

fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
b511593d71 clk: samsung: exynos4: fix g3d clocks
c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
22842d244a clk: samsung: exynos5260: fix typo in clock name
e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list

2) Clock driver extensions

07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
d0e73eaf19 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
2014-09-29 23:43:12 -07:00
Kiran Padwal 59c0621d4d clk: Remove .owner field for driver
There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."

Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 17:43:31 -07:00
Thomas Abraham fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
The 'div_core2' clock and the 'arm_clk' divider clocks are instances of
the same divider clock. So remove the 'arm_clk' clock instance.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 12:41:33 +02:00
Marek Szyprowski b511593d71 clk: samsung: exynos4: fix g3d clocks
sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because
it does not make any sense and most likely has been added by mistake.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[tomasz.figa@gmail.com: Adjusted commit message.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:31:19 +02:00
Marek Szyprowski 4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
This patch adds support for exporting mout_hdmi and mout_mixer to device
tree. Access to those clocks is required to correctly setup HDMI module
on Exynos 4210 and 4x12 SoCs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
CC: Mike Turquette <mturquette@linaro.org>
CC: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:31:14 +02:00
Marek Szyprowski c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
This patch adds missing smmu_g2d clock implementation and updates
comment about Exynos4 clocks from 278-282 range. Those clocks are
available on all Exynos4 SoC series, so the misleading comment has been
removed.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:31:06 +02:00
Krzysztof Kozlowski e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.

The DMC clock domain uses different address space (0x105C0000) than
standard clock domain (0x10030000 - 0x10050000). The difference is huge
enough to add new DT node for the clock provider, rather than extending
existing address space.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:49 +02:00
Chander Kashyap 22842d244a clk: samsung: exynos5260: fix typo in clock name
The parent name added in parent list as
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
than the defined parent due to typo.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Chander Kashyap <k.chander@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:45 +02:00
Pankaj Dubey e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:38 +02:00
Pankaj Dubey 59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
Update shift and width field of div_spi0_isp clock as per Exynos3250
user manual.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:35 +02:00
Pankaj Dubey 5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list
As per user manual of Exynos3250 SRC_CAM can select
div_cam_blk_320 if it's value is 0xC, so placing
div_cam_blk_320 at proper index in parent list of mout_cam_blk.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:28 +02:00
Linus Torvalds b3345d7c57 ARM: SoC platform changes for 3.17
This is the bulk of new SoC enablement and other platform changes for 3.17:
 
 * Samsung S5PV210 has been converted to DT and multiplatform
 * Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
 * Kirkwood, one of the popular Marvell platforms, is folded into the
   mvebu platform code, removing mach-kirkwood.
 * Hwmod data for TI AM43xx and DRA7 platforms.
 * More additions of Renesas shmobile platform support
 * Removal of plat-samsung contents that can be removed with S5PV210 being
   multiplatform/DT-enabled and the other two old platforms being removed.
 
 New platforms (most with only basic support right now):
 
 * Hisilicon X5HD2 settop box chipset is introduced
 * Mediatek MT6589 (mobile chipset) is introduced
 * Broadcom BCM7xxx settop box chipset is introduced
 
 + as usual a lot other pieces all over the platform code.
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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
2014-08-08 11:14:29 -07:00
Linus Torvalds e4ca4308c0 The clock framework changes for 3.17 are mostly additions of new clock
drivers and fixes/enhancements to existing clock drivers. There are also
 some non-critical fixes and improvements to the framework core.
 
 Changes to the clock framework core include:
 * improvements to printks on errors
 * flattening the previously hierarchal structure of per-clock entries
   in debugfs
 * allow per-clock debugfs entries that are specific to a particular
   clock driver
 * configure initial clock parent and/or initial clock rate from Device
   Tree
 * several feature enhancements to the composite clock type
 * misc fixes
 
 New clock drivers added include:
 * TI Palmas PMIC
 * Allwinner A23 SoC
 * Qualcomm APQ8084 and IPQ8064 SoCs
 * Rockchip rk3188, rk3066 and rk3288 SoCs
 * STMicroelectronics STiH407 SoC
 * Cirrus Logic CLPS711X SoC
 
 Many fixes, feature enhancements and further clock tree support for
 existing clock drivers also were merged, such as Samsung's "ARMCLK down"
 power saving feature for their Exynos4 & Exynos5 SoCs.
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Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.17 are mostly additions of new clock
  drivers and fixes/enhancements to existing clock drivers.  There are
  also some non-critical fixes and improvements to the framework core.

  Changes to the clock framework core include:
   - improvements to printks on errors
   - flattening the previously hierarchal structure of per-clock entries
     in debugfs
   - allow per-clock debugfs entries that are specific to a particular
     clock driver
   - configure initial clock parent and/or initial clock rate from
     Device Tree
   - several feature enhancements to the composite clock type
   - misc fixes

  New clock drivers added include:
   - TI Palmas PMIC
   - Allwinner A23 SoC
   - Qualcomm APQ8084 and IPQ8064 SoCs
   - Rockchip rk3188, rk3066 and rk3288 SoCs
   - STMicroelectronics STiH407 SoC
   - Cirrus Logic CLPS711X SoC

  Many fixes, feature enhancements and further clock tree support for
  existing clock drivers also were merged, such as Samsung's "ARMCLK
  down" power saving feature for their Exynos4 & Exynos5 SoCs"

* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: Add missing of_clk_set_defaults export
  clk: checking wrong variable in __set_clk_parents()
  clk: Propagate any error return from debug_init()
  clk: clps711x: Add DT bindings documentation
  clk: Add CLPS711X clk driver
  clk: st: Use round to closest divider flag
  clk: st: Update frequency tables for fs660c32 and fs432c65
  clk: st: STiH407: Support for clockgenA9
  clk: st: STiH407: Support for clockgenD0/D2/D3
  clk: st: STiH407: Support for clockgenC0
  clk: st: Add quadfs reset handling
  clk: st: Add polarity bit indication
  clk: st: STiH407: Support for clockgenA0
  clk: st: STiH407: Support for A9 MUX Clocks
  clk: st: STiH407: Support for Flexgen Clocks
  clk: st: Adds Flexgen clock binding
  clk: st: Remove uncessary (void *) cast
  clk: st: use static const for clkgen_pll_data tables
  clk: st: use static const for stm_fs tables
  clk: st: Update ST clock binding documentation
  ...
2014-08-04 11:44:20 -07:00
Thomas Abraham ca5b402938 clk: samsung: register exynos5420 apll/kpll configuration data
Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: Arjun K.V <arjun.kv@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:50:15 +02:00
Vikas Sajjan e9d529562a clk: samsung: exynos5420: Setup clocks before system suspend
Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.

while at it, add these clks to save/restore list also.

Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:50:06 +02:00
Krzysztof Kozlowski 305cfab0ba clk: samsung: Make of_device_id array const
Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:49:58 +02:00
Krzysztof Kozlowski 45c5b0a690 clk: samsung: exynos3250: Enable ARMCLK down feature
Enable ARMCLK down feature on Exynos3250 SoC. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).

The feature behaves like very fast cpufreq ondemand governor.

The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:49:34 +02:00
Krzysztof Kozlowski 42773b28e7 clk: samsung: exynos4: Enable ARMCLK down feature
Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).

The feature behaves like very fast cpufreq ondemand governor. In idle
mode this reduces energy consumption on full frequency chosen by
cpufreq governor by approximately:
 - Trats2:  6.5% (153 mA -> 143 mA)
 - Trats:  33.0% (180 mA -> 120 mA)
 - Gear1:  27.0% (180 mA -> 130 mA)

The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature and on Exynos4412 ARMCLK down is
enabled for all 4 cores.

Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and
Samsung Gear 1 (Exynos4212).

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Daniel Drake <drake@endlessm.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:49:31 +02:00
Tomasz Figa 1e832e5101 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:47:10 +02:00
Tomasz Figa 01f7ec260a clk: samsung: exynos4: Add CLKOUT clock hierarchy
This patch adds definitions of clocks that are used to drive clock
output signals of particular CMU sub-blocks that are then fed to PMU and
handled by Exynos CLKOUT driver added in further patch.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:47:10 +02:00
Tomasz Figa 800c9797ad clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy
This patch adds missing definitions of clocks from CPU and DMC clock
domains, which are necessary to properly represent CLKOUT clock hierarchy
added in further patch.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 02:42:36 +02:00
Tomasz Figa f1ff47454b clk: samsung: s5pv210: Remove legacy board support
Since there is no more support for board files, this patch removes
legacy non-DT support from the clock driver as well, including
unnecessary clkdev aliases.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-19 04:32:19 +09:00
Tomasz Figa 9978f28f69 clk: samsung: Add S5PV210 Audio Subsystem clock driver
This patch adds a driver for clock controller being a part of Audio
Subsystem present on S5PV210 and compatible SoCs. It is used to provide
clocks for other IP blocks of this subsystem.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-19 04:25:08 +09:00
Mateusz Krawczuk 841586082d clk: samsung: Add clock driver for S5PV210 and compatible SoCs
This patch adds new, Common Clock Framework-based clock driver for Samsung
S5PV210 and compatible SoCs. The driver is just added, without enabling it yet.

Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[t.figa: Added support for other SoC variants and clock output. Fixed
remaining minor issues.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-19 04:24:42 +09:00
Linus Torvalds 502fde1a0a This batch of fixes is for a handful of clock drivers from Allwinner,
Samsung, ST & TI. Most of them are of the "this hardware won't work
 without this fix" variety, including patches that fix platforms that did
 not boot under certain configurations. Other fixes are the result of
 changes to the clock core introduced in 3.15 that had subtle impacts on
 the clock drivers.
 
 There are no fixes to the clock framework core in this pull request.
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Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux

Pull clock driver fixes from Mike Turquette:
 "This batch of fixes is for a handful of clock drivers from Allwinner,
  Samsung, ST & TI.  Most of them are of the "this hardware won't work
  without this fix" variety, including patches that fix platforms that
  did not boot under certain configurations.  Other fixes are the result
  of changes to the clock core introduced in 3.15 that had subtle
  impacts on the clock drivers.

  There are no fixes to the clock framework core in this pull request"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk: spear3xx: Set proper clock parent of uart1/2
  clk: spear3xx: Use proper control register offset
  clk: qcom: HDMI source sel is 3 not 2
  clk: sunxi: fix devm_ioremap_resource error detection code
  clk: s2mps11: Fix double free corruption during driver unbind
  clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
  clk: exynos5420: Remove aclk66_peric from the clock tree description
  clk/exynos5250: fix bit number for tv sysmmu clock
  clk: s3c64xx: Hookup SPI clocks correctly
  clk: samsung: exynos4: Remove SRC_MASK_ISP gates
  clk: samsung: add more aliases for s3c24xx
  clk: samsung: fix several typos to fix boot on s3c2410
  clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock
  clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
  clk: ti: dra7: return error code in failure case
  clk: ti: apll: not allocating enough data
2014-07-13 12:21:04 -07:00
Arun Kumar K c0fb262bf2 clk: exynos5420: Add IDs for clocks used in PD mfc
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-11 08:03:59 +09:00
Jonghwa Lee 17d3f1d27c clk: exynos4: Add PPMU IP block source clocks.
Exynos4 has saveral PPMUs and each of them has operation clock which
can be gated through CMU's SFR control.

New clocks are listed below. All clocks are added as a gate-typed clock.

CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L,
CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1,
CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU,
CLK_PPMUACP,

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30 15:07:56 +02:00
Sylwester Nawrocki d5e136a21b clk: samsung: Register clk provider only after registering its all clocks
Ensure the clock provider is not registered until after all its related
clocks were created and are ready to use. Currently there are races
possible and any (of_)clk_get() call right after a clock provider's
clk_init_cb callback call may fail.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30 15:07:55 +02:00
Doug Anderson 44ff0254b8 clk: exynos5420: Remove aclk66_peric from the clock tree description
The "aclk66_peric" clock is a gate clock with a whole bunch of gates
underneath it.  This big gate isn't very useful to include in our
clock tree.  If any of the children need to be turned on then the big
gate will need to be on anyway.  ...and there are plenty of other "big
gates" that aren't described in our clock tree, some of which shut off
collections of clocks that have no relationship in the hierarchy so
are hard to model.

"aclk66_peric" is causing earlyprintk problems since it gets disabled
as part of the boot process, so let's just remove it.

Strangely (and for no good reason) this clock is exported as part of
the common clock bindings.  Remove it since there are no in-kernel
device trees using it and no reason anyone out of tree should refer to
it either.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30 14:47:33 +02:00
Rahul Sharma 0b1643b39d clk/exynos5250: fix bit number for tv sysmmu clock
Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30 14:46:36 +02:00
Charles Keepax a92dda4bfa clk: s3c64xx: Hookup SPI clocks correctly
In the move to this clock driver the hookups for the SPI clocks were
dropped, which causes my system Cragganmore (s3c6410 based) to be unable
to locate any spibus clocks. This patch adds them back in.

When taking the clock from the epll clock (SCLK) the rates on the SPI
bus are incorrect, this needs further debugging but the hookup here
should be correct and the problem should be else where.

The USBCLK case has been dropped because this requires the USB PHY to be
enabled.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30 14:46:26 +02:00
Tomasz Figa a37c82a3b3 clk: samsung: exynos4: Remove SRC_MASK_ISP gates
ISP special clocks have dedicated gating registers and so MUX SRC_MASK
register should not be used. This patch fixes the problem of
Exynos4x12-based boards freezing on system suspend, because those
mux outputs need not to be masked while suspending.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
2014-06-30 14:46:03 +02:00
Vasily Khoruzhick 34ece9e610 clk: samsung: add more aliases for s3c24xx
Without these aliases clock lookup fails in s3c2410fb,
s3cmci, s3c2410-nand, s3c24xx-i2s, and i2c-s3c2410 drivers.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30 14:45:56 +02:00
Vasily Khoruzhick cec1cdea6f clk: samsung: fix several typos to fix boot on s3c2410
There's a several typos in a driver: 2410 instead of S3C2410
and wrong argument to ARRAY_SIZE(). They prevent s3c2410
from properly booting.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30 14:44:16 +02:00
Linus Torvalds 1a5700bc2d The clock framework changes for 3.16 are pretty typical: mostly clock
driver additions and fixes. There are additions to the clock core code
 for some of the basic types (e.g. the common divider type has some fixes
 and featured added to it).
 
 One minor annoyance is a last-minute dependency that wasn't handled
 quite right. ba0fae3 in this pull request depends on
 include/dt-bindings/clock/berlin2.h, which is already in your tree via
 the arm-soc pull request. Building for the berlin platform will break
 when the clk tree is built on it's own, but merged into your master
 branch everything should be fine.
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Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux into next

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.16 are pretty typical: mostly clock
  driver additions and fixes.  There are additions to the clock core
  code for some of the basic types (e.g. the common divider type has
  some fixes and featured added to it).

  One minor annoyance is a last-minute dependency that wasn't handled
  quite right.  Commit ba0fae3b06 ("clk: berlin: add core clock driver
  for BG2/BG2CD") in this pull request depends on
  include/dt-bindings/clock/berlin2.h, which is already in your tree via
  the arm-soc pull request.  Building for the berlin platform will break
  when the clk tree is built on it's own, but merged into your master
  branch everything should be fine"

* tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits)
  mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
  clk: export __clk_round_rate for providers
  clk: versatile: free icst on error return
  clk: qcom: Return error pointers for unimplemented clocks
  clk: qcom: Support msm8974pro global clock control hardware
  clk: qcom: Properly support display clocks on msm8974
  clk: qcom: Support display RCG clocks
  clk: qcom: Return highest rate when round_rate() exceeds plan
  clk: qcom: Fix mmcc-8974's PLL configurations
  clk: qcom: Fix clk_rcg2_is_enabled() check
  clk: berlin: add core clock driver for BG2Q
  clk: berlin: add core clock driver for BG2/BG2CD
  clk: berlin: add driver for BG2x complex divider cells
  clk: berlin: add driver for BG2x simple PLLs
  clk: berlin: add driver for BG2x audio/video PLL
  clk: st: Terminate of match table
  clk/exynos4: Fix compilation warning
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  clk: divider: Fix overflow in clk_divider_bestdiv
  clk: u300: Terminate of match table
  ...
2014-06-07 20:27:30 -07:00
Linus Torvalds a727eaf64f ARM: SoC driver changes
SoC-near driver changes that we're merging through our tree. Mostly
 because they depend on other changes we have staged, but in some cases
 because the driver maintainers preferred that we did it this way.
 
 This contains a largeish cleanup series of the omap_l3_noc bus driver,
 cpuidle rework for Exynos, some reset driver conversions and a long
 branch of TI EDMA fixes and cleanups, with more to come next release.
 
 The TI EDMA cleanups is a shared branch with the dmaengine tree, with
 a handful of Davinci-specific fixes on top.
 
 After discussion at last year's KS (and some more on the mailing lists),
 we are here adding a drivers/soc directory. The purpose of this is
 to keep per-vendor shared code that's needed by different drivers but
 that doesn't fit into the MFD (nor drivers/platform) model. We expect
 to keep merging contents for this hierarchy through arm-soc so we can
 keep an eye on what the vendors keep adding here and not making it a
 free-for-all to shove in crazy stuff.
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Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull ARM SoC driver changes from Olof Johansson:
 "SoC-near driver changes that we're merging through our tree.  Mostly
  because they depend on other changes we have staged, but in some cases
  because the driver maintainers preferred that we did it this way.

  This contains a largeish cleanup series of the omap_l3_noc bus driver,
  cpuidle rework for Exynos, some reset driver conversions and a long
  branch of TI EDMA fixes and cleanups, with more to come next release.

  The TI EDMA cleanups is a shared branch with the dmaengine tree, with
  a handful of Davinci-specific fixes on top.

  After discussion at last year's KS (and some more on the mailing
  lists), we are here adding a drivers/soc directory.  The purpose of
  this is to keep per-vendor shared code that's needed by different
  drivers but that doesn't fit into the MFD (nor drivers/platform)
  model.  We expect to keep merging contents for this hierarchy through
  arm-soc so we can keep an eye on what the vendors keep adding here and
  not making it a free-for-all to shove in crazy stuff"

* tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  tty: serial: msm: Remove direct access to GSBI
  power: reset: keystone-reset: introduce keystone reset driver
  Documentation: dt: add bindings for keystone pll control controller
  Documentation: dt: add bindings for keystone reset driver
  soc: qcom: fix of_device_id table
  ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
  ARM: EXYNOS: Move the driver to drivers/cpuidle directory
  ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
  ARM: EXYNOS: Pass the AFTR callback to the platform_data
  ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
  ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
  ARM: EXYNOS: Move the AFTR state function into pm.c
  ARM: EXYNOS: Encapsulate the AFTR code into a function
  ARM: EXYNOS: Disable cpuidle for exynos5440
  ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
  ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
  ARM: EXYNOS: Remove ifdef for scu_enable in pm
  ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
  ARM: EXYNOS: Use the cpu_pm notifier for pm
  ...
2014-06-02 16:35:49 -07:00
Linus Torvalds 825f4e0271 ARM: SoC updates for 3.16 (part 1)
A quite large set of SoC updates this cycle. In no particular order:
 
 - Multi-cluster power management for Samsung Exynos, adding support for
   big.LITTLE CPU switching on EXYNOS5
 - SMP support for Marvell Armada 375 and 38x
 - SMP rework on Allwinner A31
 - Xilinx Zynq support for SOC_BUS, big endian
 - Marvell orion5x platform cleanup, modernizing the implementation and
   moving to DT.
 - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
   that their platform can be enabled in the same kernel binary as most
   of the other v7 platforms in the tree. \o/ The work isn't quite complete,
   there's some driver fixes still needed, but the basics now work.
 
 New SoC support added:
 - Freescale i.MX6SX
 - LSI Axxia AXM55xx SoCs
 - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
 - STi STIH407
 
 Plus a large set of various smaller updates for different platforms. I'm
 probably missing some important one here.
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Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull part one of ARM SoC updates from Olof Johansson:
 "A quite large set of SoC updates this cycle.  In no particular order:

   - Multi-cluster power management for Samsung Exynos, adding support
     for big.LITTLE CPU switching on EXYNOS5

   - SMP support for Marvell Armada 375 and 38x

   - SMP rework on Allwinner A31

   - Xilinx Zynq support for SOC_BUS, big endian

   - Marvell orion5x platform cleanup, modernizing the implementation
     and moving to DT.

   - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
     that their platform can be enabled in the same kernel binary as
     most of the other v7 platforms in the tree.  \o/

     The work isn't quite complete, there's some driver fixes still
     needed, but the basics now work.

  New SoC support added:

   - Freescale i.MX6SX

   - LSI Axxia AXM55xx SoCs

   - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800

   - STi STIH407

  plus a large set of various smaller updates for different platforms.
  I'm probably missing some important one here"

* tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits)
  ARM: exynos: don't run exynos4 l2x0 setup on other platforms
  ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug
  ARM: EXYNOS: mcpm rename the power_down_finish
  ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC
  ARM: EXYNOS: Enable multi-platform build support
  ARM: EXYNOS: Consolidate Kconfig entries
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add 5800 SoC support
  ARM: EXYNOS: initial board support for exynos5260 SoC
  clk: exynos5410: register clocks using common clock framework
  ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084
  ARM: sunxi: allow building without reset controller
  Documentation: devicetree: arm: sort enable-method entries
  ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE
  clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
  ARM: dts: axxia: Add reset controller
  power: reset: Add Axxia system reset driver
  ARM: axxia: Adding defconfig for AXM55xx
  ...
2014-06-02 16:15:12 -07:00
Olof Johansson 45e70b7d48 Samsung 2nd drivers for 3.16
This is including fix exynos cpufreq driver compilation with
 ARCH_MULTIPLATFORM. Even though this is a work around, this
 is required for support exynos multiplatform for a while and
 will be updated in near future.
 
 This is based on tags/samsung-exynos.
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Merge tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

Merge "Samsung 2nd drivers for 3.16" from Kukjin Kim:

This is including fix exynos cpufreq driver compilation with
ARCH_MULTIPLATFORM. Even though this is a work around, this
is required for support exynos multiplatform for a while and
will be updated in near future.

This is based on tags/samsung-exynos.

* tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (24 commits)
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  ARM: EXYNOS: Enable multi-platform build support
  ARM: EXYNOS: Consolidate Kconfig entries
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add 5800 SoC support
  ARM: EXYNOS: initial board support for exynos5260 SoC
  clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
  cpufreq: exynos: Fix the compile error
  ARM: S3C24XX: move debug-macro.S into the common space
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: trim down debug uart handling
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
  ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
  ARM: EXYNOS: Remove exynos_subsys registration
  ARM: EXYNOS: Remove duplicate lines in Makefile
  ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
  ARM: dts: Remove g2d_pd node for exynos5420
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-30 21:48:39 -07:00
Tarek Dakhran e7ef0b632e clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.

Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-31 02:13:16 +09:00
Sachin Kamat 8f213af2c0 clk/exynos4: Fix compilation warning
Fixes the following warning:
WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown)
   The function exynos4_clk_sleep_init() references
   the (unknown reference) __initdata (unknown).
   This is often because exynos4_clk_sleep_init lacks a __initdata
   annotation or the annotation of (unknown) is wrong.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-28 00:56:45 -07:00
Olof Johansson 708cec6642 clk: samsung: fix build error
"clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares
__initdata" had a typo in it which caused build failure. Trivial fix.

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-26 14:19:39 -07:00
Heiko Stübner 5a3babfcd2 clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares __initdata
The originally used PNAME macro from the core samsung clock infrastructure
declares the created array as initdata, creating section mismatch warnings
in the dclk driver.

Thus declare them directly, removing these warning.

Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-26 12:09:45 -07:00
Cho KyongHo bfed1074f2 clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
This patch adds the missing sysmmu clocks for Display and
ISP blocks.

Signed-off-by: Cho KyongHo <pullip.cho@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-26 06:48:10 +09:00
Amit Daniel Kachhap 9a8f39950d ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock
Now with common clock support added for exynos5250 it is necessary to
move this code to exynos5250 common clock driver as clock registers
should be handled there. This change is tested in exynos5250 based
arndale platform.

Cc: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsugn.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
[t.figa: Rebased onto current kernel sources.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-26 05:21:06 +09:00
Alim Akhtar 6520e968ee clk: exynos5420: Add 5800 specific clocks
Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-19 22:15:08 +09:00
Tomasz Figa 2ce16c5342 clk: samsung: exynos3250: Add clocks using common clock framework
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual IPs.

The CMU of Exynos3250 includes following clock doamins:
- CPU block for Cortex-A7 MPCore processor
- LEFTBUS/RIGHTBUS block
- TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Karol Wrona <k.wrona@samsung.com>
Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
2014-05-14 19:41:32 +02:00
Pankaj Dubey 1f4f2cfdb7 ARM: S3C24XX: move S3C24XX clock Kconfig options to Samsung clock Kconfig file
This patch moves S3C24XX specific clock Kconfig options into
"clk/samsung/Kconfig" and also removes COMMON_CLK selection from
"mach-s3c24xx/Kconfig" as S3C24XX_COMMON_CLK is selecting it's dependency.

CC: Ben Dooks <ben-linux@fluff.org>
CC: Kukjin Kim <kgene.kim@samsung.com>
CC: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:41:15 +02:00
Pankaj Dubey 4ce9b85e48 clk: samsung: add new Kconfig for Samsung common clock option
This patch adds new Kconfig file for adding new COMMON_CLK_SAMSUNG option.
Samsung platforms can select this for using common clock infrastructure.

CC: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:41:14 +02:00
Shaik Ameer Basha 773424326b clk: samsung: exynos5420: add more registers to restore list
This patch adds more register offsets to the list for
preserving their values during S2R.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:24 +02:00
Shaik Ameer Basha b31ca2a017 clk: samsung: exynos5420: add misc clocks
This patch adds some missing miscellaneous clocks specific
to exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:23 +02:00
Shaik Ameer Basha 31116a642b clk: samsung: exynos5420: update clocks for MAU Block
This patch adds the missing MAU block specific clocks.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:23 +02:00
Shaik Ameer Basha 58ff8d0383 clk: samsung: exynos5420: fix register offset for sclk_bpll
This patch fixes the wrong register offset for sclk_bpll clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:22 +02:00
Shaik Ameer Basha 1d87db4d4e clk: samsung: exynos5420: correct sysmmu-mfc parent clocks
This patch corrects the wrong parent-child relationship
between sysmmu-mfc clocks.

Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:22 +02:00
Shaik Ameer Basha 6b5ae463e4 clk: samsung: exynos5420: update clocks for FSYS and FSYS2 blocks
This patch adds more clocks from FSYS and FSYS2 blocks
and uses GATE_IP_* registers for gating IPs.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:21 +02:00
Shaik Ameer Basha 6575fa76c3 clk: samsung: exynos5420: update clocks for WCORE block
This patch adds missing clocks for WCORE block.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:21 +02:00
Shaik Ameer Basha 0a22c30653 clk: samsung: exynos5420: update clocks for PERIS and GEN blocks
This patch fixes some parent-child relationships according
to the latest datasheet and adds more clocks related to
PERIS and GEN blocks.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:20 +02:00
Shaik Ameer Basha faec151b50 clk: samsung: exynos5420: update clocks for PERIC block
This patch includes,
    1] renaming of the HSI2C clocks
    2] renaming of spi clocks according to the datasheet
    3] fixes for child-parent relationships
    4] adding of more clocks related to PERIC block
    5] use GATE_IP_* offsets instead of GATE_BUS_*

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:20 +02:00
Shaik Ameer Basha 424b673a05 clk: samsung: exynos5420: update clocks for DISP1 block
This patch corrects some child-parent clock relationships,
and updates the clocks according to the latest datasheet.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:19 +02:00
Shaik Ameer Basha 3fac5941da clk: samsung: exynos5420: update clocks for G2D and G3D blocks
This patch adds missing clocks of G2D block. It also removes
the aclkg3d alias from G3D block clocks.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:19 +02:00
Shaik Ameer Basha 4549d93d9c clk: samsung: exynos5420: fix parent clocks for mscl sysmmu
This patch fixes the parent clocks for mscl sysmmu.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:18 +02:00
Shaik Ameer Basha 02932381ca clk: samsung: exynos5420: update clocks for GSCL and MSCL blocks
This patch adds the missing GSCL and MSCL block clocks
and corrects some wrong parent-child relationships.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:18 +02:00
Shaik Ameer Basha 3a767b35c6 clk: samsung: exynos5420: add clocks for ISP block
This patch adds minimum set of clocks to gate ISP block for
power saving.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:17 +02:00
Shaik Ameer Basha dbd713bb90 clk: samsung: exynos5420: Rename mux parent arrays
This patch renames the mux parent arrays as per the naming
convension followed by the other exynos specific clock drivers.
And it also renames "mout_cpu_kfc" clock to "mout_kfc".

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:17 +02:00
Arun Kumar K 2ce262f456 clk: samsung: exynos5420: Add clock IDs needed by GPU
Adds IDs for the clocks needed by the ARM Mali GPU
in exynos5420.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:16 +02:00
Tomasz Stanislawski a5b219b40c clk: samsung: exynos4: export sclk_hdmiphy clock
Export sclk_hdmiphy clock to be usable from DT.

Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:15 +02:00
Arun Kumar K 20b82ae27e clk: samsung: exynos5250: Add clocks for G3D
This patch adds the required clocks for ARM Mali IP
in Exynos5250.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
[t.figa: Changed clock ID to avoid conflict with CLK_SSS]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:15 +02:00
Sylwester Nawrocki 04bc7d96fb clk: samsung: exynos4: Use single clock ID for CLK_MDMA gate clocks
Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock
defined exactly in same way in documentation. Using different
names for these clocks is a bit misleading. Since there is no users
of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and
replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA
has correct clock assigned on Exynos4x12 SoCs.

Suggested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:14 +02:00
Pankaj Dubey 42fb57c008 clk: samsung: fixed compiler warning [-Wpointer-to-int-cast]
When compiled using ARM64 cross compiler, gcc complains as

drivers/clk/samsung/clk.c:293:18:
warning: cast from pointer to integer of different size
[-Wpointer-to-int-cast]

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:05 +02:00
Sachin Kamat 53cb6342de clk: samsung: exynos5420: Fix VPLL lock offset
Set it as per the user manual.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:23:37 +02:00
Naveen Krishna Chatradhi 5b73721b60 clk: samsung: exynos5250/5420: Add gate clock for SSS module
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:23:26 +02:00
Tomasz Figa 91a1263fd2 clk: samsung: Initialize clock table with error pointers
Before this patch, the driver was simply zeroing the clock table, which
is incorrect, because invalid clock numbers returned NULL instead of
error pointers. This patch fixes this by changing the driver to
initialize the array with PTR_ERR(-ENOENT).

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
2014-05-14 19:23:25 +02:00
Rahul Sharma d39e55e063 clk/exynos5260: add clock file for exynos5260
Add support for exynos5260 clocks in clock driver.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:16:55 +02:00
Rahul Sharma eefe119b81 clk/samsung: add support for pll2650xx
Add support for pll2650xx in samsung pll file. This PLL variant
is close to pll36xx but uses CON2 registers instead of CON1.

Aud_pll in Exynos5260 is pll2650xx and uses this code.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:16:54 +02:00
Pankaj Dubey 8432984732 clk/samsung: add support for pll2550xx
exynos5260 use pll2550xx and it has different bit fields
for P,M,S values as compared to pll2550. Support for
pll2550xx is added here.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:16:54 +02:00
Rahul Sharma 976face4b4 clk/samsung: add support for multiple clock providers
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation, SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.

This layer is modified accordingly to enable the support
for multiple clock providers.

Clock file for exynos4, exynos5250, exynos5420, exynos5440,
S3c64xx, S3c24xx are also modified as per changed helper functions.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
[t.figa: Modified s3c2410 clock driver as well]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:15:38 +02:00
Heiko Stuebner 3f7c01ade2 clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442
This driver can handle the clock controllers of the socs mentioned above,
as they share a common clock tree with only small differences.

The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure.

As pll-rate-tables only the 12mhz variants are currently included.
The original code was wrongly checking for 169mhz xti values [a 0 to much
at the end], so the original 16mhz pll table would have never been
included and its values are so obscure that I have no possibility to
at least check their sane-ness. When using the formula from the manual
the resulting frequency is near the table value but still slightly off.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-13 08:00:40 +09:00
Heiko Stuebner 5799ea12a4 clk: samsung: add clock driver for external clock outputs
This adds a driver for controlling the external clock outputs of
s3c24xx architectures including the dclk muxes and dividers.

The driver at the moment only supports the legacy non-dt boards using these
clock outputs. The clock-output control itself is part of the system-controller
mainly controlled by the pinctrl drivers. So it should most likely be
integrated there for dt platforms.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-09 05:48:51 +09:00
Heiko Stuebner ca2e90ac18 clk: samsung: add clock controller driver for s3c2412
This driver can handle the clock controller in the s3c2412 soc.

The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-04-15 02:11:36 +09:00
Heiko Stuebner ea5d6a8d3e clk: samsung: add plls used by the early s3c24xx cpus
The manuals do not give them explicit names like in later socs, so more
generic names with a s3c2410-prefix were used for them.

As it was common to do so in the previous implementation, functionality
to change the pll rate is already included.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-04-15 02:11:36 +09:00
Heiko Stuebner 61fbb1d278 clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
The three SoCs share a common clock tree which only differs in the
existence of some special clocks.

As with all parts common to these three SoCs the driver is named
after the s3c2443, as it was the first SoC introducing this structure
and there exists no other label to describe this s3c24xx epoch.

The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure. As an example the sclk_uart gate was never handled previously
and the div_uart was made to be the clock used by the serial driver.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-04-15 02:11:08 +09:00
Heiko Stuebner a951b1d91d clk: samsung: add plls used by the s3c2443
The s3c2443 uses different plls that are not present yet. Therefore
add the two needed types.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-04-15 02:11:07 +09:00
Heiko Stuebner 06654acb66 clk: samsung: add pll_6552 variant for s3c2416
According to the manual s3c2416 and s3c2450 use a pll 6552 and 6553
and while the pll_6553 matches exactly the one already implemented
the pll_6552 differs to the one from the s3c64xx series.

The change is solely in the bit locations of the mdiv and pdiv values.
All calculations are the same for both implementatons and even the
proposed divider-values for specific frequencies in the manuals are
the same.

Therefore implement a variant that simply uses the changed bit
locations if necessary.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-04-15 02:11:07 +09:00
Arnd Bergmann 9e0c42ea3d Exynos cleanup for v3.15
- reorganize code for
 - add support reserve memory for mfc-v7
 - consolidate exynos4 and exynos5 machine codes
 - add generic compatible strings for exynos4 and exynos5
 - update DT with generic compatible strings
 - move clk related dt-binding header file in dt-bindings/clock
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Merge tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Exynos cleanup for v3.15" from Kukjin Kim:

- reorganize code for
- add support reserve memory for mfc-v7
- consolidate exynos4 and exynos5 machine codes
- add generic compatible strings for exynos4 and exynos5
- update DT with generic compatible strings
- move clk related dt-binding header file in dt-bindings/clock

* tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
  ARM: dts: Update Exynos DT files with generic compatible strings
  ARM: EXYNOS: Add generic compatible strings
  ARM: EXYNOS: Consolidate exynos4 and exynos5 machine files
  ARM: EXYNOS: Consolidate CPU init code
  ARM: SAMSUNG: Introduce generic Exynos4 and 5 helpers
  ARM: EXYNOS: Add support to reserve memory for MFC-v7
  ARM: SAMSUNG: Reorganize calls to reserve memory for MFC

Conflicts:
	arch/arm/mach-exynos/exynos.c

Signed-off-by; Arnd Bergmann <arnd@arndb.de>
2014-03-29 02:03:39 +01:00
Tushar Behera 602408e3de dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
Most of the clock related dt-binding header files are located in
dt-bindings/clock folder. It would be good to keep all the similar
header files at a single location.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Reviewed-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-03-21 04:31:30 +09:00
Tomasz Figa 4fcf47e2db clk: samsung: exynos4: Add remaining suspend/resume handling
As of now, part of Exynos4 clock suspend/resume handling is located
in mach-exynos/pm.c, which is not where code accessing CMU registers
should reside.

This patch implements all the necessary suspend/resume handling code
in Exynos4 clock driver to allow dropping that old code.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:01 +09:00
Tomasz Figa 3efb251167 clk: samsung: Drop old suspend/resume code
Since all SoC drivers have been moved to local suspend/resume handling,
the old code can be safely dropped.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:01 +09:00
Tomasz Figa 08c0d829d8 clk: samsung: s3c64xx: Move suspend/resume handling to SoC driver
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:01 +09:00
Tomasz Figa 388c78851e clk: samsung: exynos5420: Move suspend/resume handling to SoC driver
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:00 +09:00
Tomasz Figa c3b6c1d701 clk: samsung: exynos5250: Move suspend/resume handling to SoC driver
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:00 +09:00
Tomasz Figa b7b647be15 clk: samsung: exynos4: Move suspend/resume handling to SoC driver
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:00 +09:00
Tomasz Figa 3ccefbd229 clk: samsung: Provide common helpers for register save/restore
As suspend/resume handlers are being moved to SoC specific code, due to
differencies in suspend/resume handling of particular SoCs, to minimize
code duplication this patch provides common register save/restore
helpers that save/restore given list of registers of clock controller.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:00 +09:00
Tomasz Figa 442f4948e5 clk: exynos4: Remove remnants of non-DT support
This patch simplifies a bit clock initialization code by removing
remnants of non-DT clock initialization, such as reg_base and xom values
passed in function parameters.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:00 +09:00
Linus Torvalds d30492adea The second half of the clock framework pull requeust for 3.14 is
dominated by platform support for Qualcomm's MSM SoCs, DT binding
 updates for TI's OMAP-ish processors and additional support for Samsung
 chips. Additionally there are other smaller clock driver changes and
 several last minute fixes. This pull request also includes the HiSilicon
 support that depends on the already-merged arm-soc pull request.
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Merge tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux

Pull more clock framework changes from Mike Turquette:
 "The second half of the clock framework pull requeust for 3.14 is
  dominated by platform support for Qualcomm's MSM SoCs, DT binding
  updates for TI's OMAP-ish processors and additional support for
  Samsung chips.

  Additionally there are other smaller clock driver changes and several
  last minute fixes.  This pull request also includes the HiSilicon
  support that depends on the already-merged arm-soc pull request"

[ Fix up stupid compile error in the source tree with evil merge  - Grumpy Linus ]

* tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux: (49 commits)
  clk: sort Makefile
  clk: sunxi: fix overflow when setting up divided factors
  clk: Export more clk-provider functions
  dt-bindings: qcom: Fix warning with duplicate dt define
  clk: si5351: remove variant from platform_data
  clk: samsung: Remove unneeded semicolon
  clk: qcom: Fix modular build
  ARM: OMAP3: use DT clock init if DT data is available
  ARM: AM33xx: remove old clock data and link in new clock init code
  ARM: AM43xx: Enable clock init
  ARM: OMAP: DRA7: Enable clock init
  ARM: OMAP4: remove old clock data and link in new clock init code
  ARM: OMAP2+: io: use new clock init API
  ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
  ARM: OMAP3: hwmod: initialize clkdm from clkdm_name
  ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm
  ARM: OMAP2+: clock: use driver API instead of direct memory read/write
  ARM: OMAP2+: clock: add support for indexed memmaps
  ARM: dts: am43xx clock data
  ARM: dts: AM35xx: use DT clock data
  ...
2014-01-28 18:44:53 -08:00
Linus Torvalds 7e21774db5 The first half of the clk framework pull request is made up almost
entirely of new platform/driver support. There are some conversions of
 existing drivers to the common-clock Device Tree binding, and a few
 non-critical fixes to the framework.
 
 Due to an entirely unnecessary cyclical dependency with the arm-soc tree
 this pull request is broken into two pieces. The second piece will be
 sent out after arm-soc sends you the pull request that merged in core
 support for the HiSilicon 3620 platform. That same pull request from
 arm-soc depends on this pull request to merge in those HiSilicon bits
 without causing build failures.
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Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux

Pull clk framework changes from Mike Turquette:
 "The first half of the clk framework pull request is made up almost
  entirely of new platform/driver support.  There are some conversions
  of existing drivers to the common-clock Device Tree binding, and a few
  non-critical fixes to the framework.

  Due to an entirely unnecessary cyclical dependency with the arm-soc
  tree this pull request is broken into two pieces.  The second piece
  will be sent out after arm-soc sends you the pull request that merged
  in core support for the HiSilicon 3620 platform.  That same pull
  request from arm-soc depends on this pull request to merge in those
  HiSilicon bits without causing build failures"

[ Just did the ARM SoC merges, so getting ready for the second clk tree
  pull request   - Linus ]

* tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits)
  devicetree: bindings: Document qcom,mmcc
  devicetree: bindings: Document qcom,gcc
  clk: qcom: Add support for MSM8660's global clock controller (GCC)
  clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8974's global clock controller (GCC)
  clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8960's global clock controller (GCC)
  clk: qcom: Add reset controller support
  clk: qcom: Add support for branches/gate clocks
  clk: qcom: Add support for root clock generators (RCGs)
  clk: qcom: Add support for phase locked loops (PLLs)
  clk: qcom: Add a regmap type clock struct
  clk: Add set_rate_and_parent() op
  reset: Silence warning in reset-controller.h
  clk: sirf: re-arch to make the codes support both prima2 and atlas6
  clk: composite: pass mux_hw into determine_rate
  clk: shmobile: Fix MSTP clock array initialization
  clk: shmobile: Fix MSTP clock index
  ARM: dts: Add clock provider specific properties to max77686 node
  clk: max77686: Register OF clock provider
  ...
2014-01-23 18:56:08 -08:00
Linus Torvalds 93abdb7785 ARM: SoC non-critical fixes for 3.14
As usual, we have a batch of fixes that weren't considered significant
 enough to warrant going into the later -rcs for previous release, so
 they are queued up on this branch.
 
 A handful of these are for various DT fixups for Samsung platforms,
 and a handful of other minor things.
 
 There are also a couple of stable-marked patches for mvebu -- they came in
 quite late and we decided to keep them deferred until the first -stable
 release to get more coverage instead of squeezing them into 3.13.
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Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical fixes from Olof Johansson:
 "As usual, we have a batch of fixes that weren't considered significant
  enough to warrant going into the later -rcs for previous release, so
  they are queued up on this branch.

  A handful of these are for various DT fixups for Samsung platforms,
  and a handful of other minor things.

  There are also a couple of stable-marked patches for mvebu -- they
  came in quite late and we decided to keep them deferred until the
  first -stable release to get more coverage instead of squeezing them
  into 3.13"

* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits)
  ARM: at91: smc: bug fix in sam9_smc_cs_read()
  i2c: mv64xxx: Document the newly introduced Armada XP A0 compatible
  i2c: mv64xxx: Fix bus hang on A0 version of the Armada XP SoCs
  ARM: mvebu: Add quirk for i2c for the OpenBlocks AX3-4 board
  ARM: mvebu: Add support to get the ID and the revision of a SoC
  ARM: dts: msm: Fix gpio interrupt and reg length
  irqchip: sirf: set IRQ_LEVEL status_flags
  ARM: OMAP2+: gpmc: Move legacy GPMC width setting
  ARM: OMAP2+: gpmc: Introduce gpmc_set_legacy()
  ARM: OMAP2+: gpmc: Move initialization outside the gpmc_t condition
  ARM: OMAP2+: board-generic: update SoC compatibility strings
  Documentation: dt: OMAP: explicitly state SoC compatible strings
  ARM: OMAP2+: enable AM33xx SOC EVM audio
  ARM: OMAP2+: Select USB PHY for AM335x SoC
  ARM: bcm2835: Fix grammar in help message
  ARM: msm: trout: fix uninit var warning
  ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2
  ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12
  ARM: dts: add clock provider for mshc node for Exynos4412 SOC
  clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
  ...
2014-01-23 18:36:01 -08:00
Takashi Iwai 2587533615 Merge branch 'for-next' into for-linus 2014-01-20 10:20:14 +01:00
Sachin Kamat 8e31d19b93 clk: samsung: Remove unneeded semicolon
Semicolon not needed after switch statement.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-17 15:00:25 -08:00
Andrew Bresticker 3538a2cf0e clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:43 +01:00
Andrew Bresticker 35399dda01 clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:42 +01:00
Andrew Bresticker 547f33509c clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings.  Default names will be used
when an input clock is not given.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:41 +01:00
Andrew Bresticker b37a422410 clk: exynos-audss: convert to platform device
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs.  This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed.  Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:41 +01:00
Andrzej Hajda ad3ab455d3 clk: exynos5440: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:40 +01:00
Andrzej Hajda cba9d2fa8b clk: exynos5420: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:39 +01:00
Andrzej Hajda 2fe8f00c49 clk: exynos5250: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:38 +01:00
Andrzej Hajda 2d73823750 clk: exynos4: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:38 +01:00
Andrew Bresticker f521ac8b39 clk: exynos5250: register APLL rate table
Register the APLL rate table so that we can set the APLL rate from
the cpufreq driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:01:49 +01:00
Sachin Kamat e86ffc4199 clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apll
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the
clock rate in the cpufreq driver.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:43:28 +01:00
Tomasz Figa 96987ded8f clk: samsung: exynos5250: Fix parents of gate clocks from MFC domain
This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:49 +01:00
Tomasz Figa bfeb9f274b clk: samsung: exynos5250: Correct parent list of audio muxes
According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:49 +01:00
Tomasz Figa 256dd646a3 clk: samsung: exynos5250: Add missing unpopulated mux parents
This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:48 +01:00
Tomasz Figa 3818f11740 clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:48 +01:00
Tomasz Figa 796d1f4cd6 clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domain
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions
of GSCL domain gate clocks to use it as their parent, as specified in
SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:47 +01:00
Tomasz Figa 38ee37540f clk: samsung: exynos5250: Make names of mux and div clocks consistent
This patch renames all mux clocks to start with mout_ prefix and all div
clocks to start with div_ prefix for consistency with other clocks
already defined this way.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:47 +01:00
Tomasz Figa 2786c9622e clk: samsung: exynos5250: Sort definitions by registers and bitfield
This patch reorders clock definitions, so they are sorted by register
addresses and bitfield shifts. When at it, blank lines are added to
separate definitions of clocks from different registers.

Overall this should make the driver more readable and reduce the number
of potential conflicts when adding new entries.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:46 +01:00
Tomasz Figa 2bb00c68e0 Merge branch 'samsung-fixes' into samsung-next-base 2013-12-30 18:15:23 +01:00
Krzysztof Kozlowski 3fd68c99f3 clk: exynos: File scope reg_save array should depend on PM_SLEEP
Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only
by suspend and resume functions.

This fixes the warning on CONFIG_PM_SLEEP=n:
drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable]

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:01:09 +01:00
Abhilash Kesavan 2feed5aecf clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:59:25 +01:00
Abhilash Kesavan 8fb9aeb7a7 clk: samsung: exynos5250: Add MDMA0 clocks
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:55:52 +01:00
Abhilash Kesavan 3bf34666a0 clk: samsung: exynos5250: Fix ACP gate register offset
The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:53:26 +01:00
Andrew Bresticker 97c3557c3e clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:53:22 +01:00
Seung-Woo Kim 5fdd1b56be clk: samsung: exynos4: Correct SRC_MFC register
The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:53:18 +01:00
Tomasz Figa 86576fbe20 clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
The clock was missing CLK_SET_RATE_PARENT flag, which caused rate
setting failures due to inability of reconfiguration of second
divider behind it.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-12-21 07:58:38 +09:00
Chander Kashyap cdf64eeeb0 clk: exynos5420: fix cpll clock register offsets
Fixes cpll control and lock register offset values for Exynos5420 SoC.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-04 10:46:45 -08:00
Tomasz Figa a7a996d192 clk: samsung: s3c64xx: Remove clock aliases of old DMA driver
Since the old DMA driver got removed, these aliases are no longer
necessary.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2013-11-24 14:38:25 +00:00
Tomasz Figa d37f7617bd clk: samsung: s3c64xx: Add aliases for DMA clocks
This patch adds clkdev aliases for clocks used by PL08x DMA driver.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2013-11-24 14:38:24 +00:00
Tomasz Figa b69f460dc1 ARM: S3C64XX: Migrate clock handling to Common Clock Framework
This patch migrates the s3c64xx platform to use the new clock driver
using Common Clock Framework.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-09-17 06:47:36 +09:00
Linus Torvalds bef4a0ab98 The common clk framework changes for 3.12 are dominated by clock driver
patches, both new drivers and fixes to existing. A high percentage of
 these are for Samsung platforms like Exynos. Core framework fixes and
 some new features like automagical clock re-parenting round out the
 patches.
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Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...
2013-09-09 15:49:04 -07:00
Tomasz Figa 22e9e7589e clk: samsung: exynos5250: Simplify registration of PLL rate tables
Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:34:05 -07:00
Tomasz Figa efb19a85cb clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:34:01 -07:00
Tomasz Figa 5fadfc7ed3 clk: samsung: exynos4: Register PLL rate tables for Exynos4210
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:57 -07:00
Tomasz Figa 4f7641f588 clk: samsung: exynos4: Reorder registration of mout_vpllsrc
Since PLL input frequency must be known before PLL registration,
mout_vpllsrc clock which is a reference clock of VPLL must be registered
before VPLL.

This patch reorders clock registration to register mout_vpllsrc before
VPLL.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:52 -07:00
Tomasz Figa 5c89658a2e clk: samsung: pll: Add support for rate configuration of PLL46xx
This patch implements round_rate and set_rate callbacks of PLL46xx
driver to allow reconfiguration of PLL at runtime.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:47 -07:00
Tomasz Figa c50d11f35a clk: samsung: pll: Use new registration method for PLL46xx
This patch modifies PLL46xx support code and its users to use the
recently introduced common PLL registration helper.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:43 -07:00
Tomasz Figa b4054ac6a2 clk: samsung: pll: Add support for rate configuration of PLL45xx
This patch implements round_rate and set_rate callbacks of PLL45xx
driver to allow reconfiguration of PLL at runtime.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:39 -07:00
Tomasz Figa 52b0601637 clk: samsung: pll: Use new registration method for PLL45xx
This patch modifies PLL45xx support code and its users to use the
recently introduced common PLL registration helper.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:35 -07:00
Tomasz Figa c641596300 clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
This array defines PLLs specific to Exynos 4x12 SoCs and not for all
Exynos 4 SoCs, so the name should represent that.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:30 -07:00
Tomasz Figa 336c18bd33 clk: samsung: exynos4: Remove checks for DT node
Exynos 4 supports only DT based bootup, so non-DT cases does not need to
be handled anymore.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:25 -07:00
Tomasz Figa a11a2f8f25 clk: samsung: exynos4: Remove unused static clkdev aliases
Since Exynos does not support legacy non-DT boot anymore, most of clock
lookups happen using device tree, so most of static clkdev aliases are no
longer necessary. This patch removes them.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:19 -07:00
Tomasz Figa 3a64789568 clk: samsung: Modify _get_rate() helper to use __clk_lookup()
There is no need to use clkdev inside the clock driver to retrieve the
clocks for internal use. Instead __clk_lookup() helper can be used to
look up clocks by their platform name.

This patch modifies the behavior of _get_rate() helper to look up clocks
by platform name and adjusts all users of it to pass platform names
instead of clkdev aliases.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:15 -07:00
Tomasz Figa e6c3e730a7 clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
Exynos cpufreq driver is the only remaining piece of code that needs
static clkdev aliases for operation, because it can not do device tree
based clock lookups yet.

This patch moves clock alias definitions for those clocks to separate
arrays that can be used with samsung_clk_register_alias() helper.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06 13:33:10 -07:00
Rahul Sharma 0044cbcd66 clk/exynos5420: assign dout_pixel id to pixel clock divider
dout_pixel is a new ID allocated for pixel clock divider. It is
queried in the driver to pass as the parent to hdmi clock while
switching between parents.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:48:12 -07:00
Rahul Sharma 4625f1b5d4 clk/exynos5420: add hdmi mux to change parents in hdmi driver
hdmi driver needs to change the parent of hdmi clock
to pixel clock or hdmiphy clock, based on the stability
of hdmiphy. This patch is exposing the mux for changing
the parent.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:48:06 -07:00
Rahul Sharma 14d87cda8d clk/exynos5420: fix the order of parents of hdmi mux
Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:48:00 -07:00
Rahul Sharma 9b229d8b04 clk/exynos5420: add gate clock for mixer sysmmu
Adding sysmmu clock for mixer for exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:47:45 -07:00
Rahul Sharma c9f3f08159 clk/exynos5420: add sclk_hdmiphy to the list of special clocks
Add sclk_hdmiphy to the list of exposed clocks. This is required
by hdmi driver to change the parent of hdmi clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:46:57 -07:00
Rahul Sharma e2815b048a clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem
parent of hdmi and mixer block is mentioned as aclk200 which is
not correct. It is clocked by the ouput of aclk200_disp1. Hence
parent for mixer and hdmi clocks is changed to aclk200_disp1.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-28 19:23:40 -07:00
Sachin Kamat 5b0dde99e8 clk: s3c64xx: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 18:36:20 -07:00
Mike Turquette 29f79cb713 Merge branch 'clk-next-s3c64xx-delta' into clk-next 2013-08-27 16:20:35 -07:00
Tomasz Figa 40ef723c8b clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
This patch modifies PLL6552 and PLL6553 clock drivers to use recently
added common Samsung PLL registration method.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-26 18:09:56 -07:00
James Hogan 819c1de344 clk: add CLK_SET_RATE_NO_REPARENT flag
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-19 12:27:17 -07:00
Sylwester Nawrocki a701fe3851 clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocks
The ISP clock registers belong to the ISP power domain and may change
their values if this power domain is switched off/on. Add
CLK_GET_RATE_NOCACHE flags to ensure we do not rely on invalid cached
data when setting or getting frequency of those clocks.

Without this fix the FIMC-IS Cortex-A5 core and AXI bus clocks have
incorrect frequencies, which breaks the ISP operation and starting the
video pipeline fails with timeouts reported by the FIMC-IS firmware.

See related commit 722a860ecb "[media]
exynos4-is: Fix FIMC-IS clocks initialization" for more details.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-13 10:01:56 -07:00
Sachin Kamat 4d1b5e73b9 clk: exynos5440: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:37 -07:00
Sachin Kamat 202e5ae945 clk: exynos5420: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:36 -07:00
Sachin Kamat b6993ecb87 clk: exynos5250: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:35 -07:00
Sachin Kamat 3c701c51ef clk: exynos4: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:34 -07:00
Sachin Kamat a9381b3f9b clk: exynos5420: Make exynos5420_plls static
'exynos5420_plls' is used only in this file. Make is static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:32 -07:00
Sachin Kamat ae2329f790 clk: exynos5250: Make exynos5250_plls static
exynos5250_plls is used only in this file. Make it static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:31 -07:00
Sachin Kamat 680681aee8 clk: exynos4: Make exynos4_plls static
'exynos4_plls' is used only in this file. Make it static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:29 -07:00
Mike Turquette 5cfe9614f3 Merge branch 'clk-next-s3c64xx' into clk-next 2013-08-08 15:57:26 -07:00
Tomasz Figa 06dda9d770 clk: samsung: Add clock driver for S3C64xx SoCs
This patch adds new, Common Clock Framework-based clock driver for Samsung
S3C64xx SoCs. The driver is just added, without actually letting the
platforms use it yet, since this requires more intermediate steps.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-05 11:58:37 -07:00
Tomasz Figa eb5271215b clk: samsung: pll: Add support for PLL6552 and PLL6553
This patch adds support for PLL6552 and PLL6553 PLLs present on Samsung
S3C64xx SoCs.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-05 11:58:30 -07:00
Vikas Sajjan d2127ac451 clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC
Adds the EPLL and VPLL freq table for exynos5250 SoC.

Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:24:18 -07:00
Vikas Sajjan 8bc2eeb83e clk: samsung: Reorder MUX registration for mout_vpllsrc
While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the
"fout_vpll" (child), we found get rate was failing.

So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:28 -07:00
Vikas Sajjan bb4278dc9a clk: samsung: Add set_rate() clk_ops for PLL36xx
This patch adds set_rate and round_rate clk_ops for PLL36xx

Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:10 -07:00
Yadwinder Singh Brar dfa893190d clk: samsung: Add set_rate() clk_ops for PLL35xx
This patch add set_rate() and round_rate() for PLL35xx

Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:10 -07:00
Yadwinder Singh Brar 3ff6e0d8d6 clk: samsung: Add support to register rate_table for samsung plls
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.

Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:09 -07:00
Yadwinder Singh Brar 5ca8fbd8d1 clk: samsung: Remove unused pll registeration code for pll35xx and pll36xx
This patch removes samsung_clk_register_pll35xx() and
samsung_clk_register_pll36xx() registaration functions as users migrated to
new samsung_clk_register_pll().

Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:09 -07:00
Yadwinder Singh Brar c898c6b7cb clk: samsung: Migrate exynos5420 to use common samsung_clk_register_pll()
This patch migrates exynos5420 pll registeration to use common
samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to
unique id list of clocks.

Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:08 -07:00
Yadwinder Singh Brar 160641e718 clk: samsung: Migrate exynos4 to use common samsung_clk_register_pll()
This patch migrates exynos4 pll registeration to use common
samsung_clk_register_pll() by intialising table of PLLs.

Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:21:48 -07:00
Yadwinder Singh Brar 8dac3530c7 clk: samsung: Migrate exynos5250 to use common samsung_clk_register_pll()
This patch migrates exynos5250 pll registeration to use common
samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to
unique id list of clocks.

Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:21:27 -07:00
Yadwinder Singh Brar 07dc76fa61 clk: samsung: Define a common samsung_clk_register_pll()
This patch defines a common samsung_clk_register_pll()
Since pll2550 & pll35xx and pll2650 & pll36xx have exactly same clk ops
implementation, added pll2550 and pll2650 also.

Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:19:18 -07:00
Yadwinder Singh Brar 079dbead49 clk: samsung: Introduce a common samsung_clk_pll struct
This patch unifies clk strutures used for PLL35xx & PLL36xx and
adding an extra member lock_reg, so that common code can be factored out.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:19:17 -07:00
Sachin Kamat 9f271369f5 clk: exynos4: Add clock entries for TMU
Added clock entries for thermal management unit (TMU) for
Exynos4 SoCs.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-30 20:40:48 -07:00
Rahul Sharma b38a5040a6 clk/exynos5250: add sclk_hdmiphy in the list of special clocks
hdmi driver needs hdmiphy clock which is one of the parent
for hdmi mux clock. This is required while changing the parent
of mux clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-30 14:12:34 -07:00
Rahul Sharma 4a45331488 clk/exynos5250: add mout_hdmi mux clock for hdmi
hdmi driver needs to change the parent of hdmi clock
frequently between pixel clock and hdmiphy clock. hdmiphy is
not stable after power on and for a short interval while changing
the phy configuration. For this duration pixel clock is used to
clock hdmi.

This patch is exposing the mux for changing parent.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-30 14:09:41 -07:00
Sachin Kamat 406c598927 clk: exynos5250: Add G2D gate clock
Adds gate clock for G2D IP for Exynos5250 SoC.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-29 23:40:21 -07:00
Sachin Kamat 1190338f50 clk: exynos-audss: Staticize exynos_audss_clk_init
exynos_audss_clk_init() is used only in this file. Make it
static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25 14:18:40 -07:00
Sachin Kamat 901f857605 clk: exynos5440: Staticize local symbols
Symbols referenced only in this file are made static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25 14:18:36 -07:00
Sachin Kamat c7306229d3 clk: exynos5420: Staticize local symbols
Symbols referenced only in this file are made static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25 14:18:32 -07:00
Sachin Kamat b95e71c608 clk: exynos5250: Staticize local symbols
Symbols referenced only in this file are made static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25 14:18:27 -07:00
Sachin Kamat 0ffc767f76 clk: exynos4: Remove unused function
Subsequent to the cleanup in commit 3c70348c7c ("ARM: EXYNOS:
Remove legacy timer initialization code"), this function has no more
users. Hence remove it.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25 14:18:24 -07:00
Sachin Kamat d75f306378 clk: exynos4: Staticize local symbols
Symbols referenced only in this file are made static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25 14:18:13 -07:00
Linus Torvalds 92295f632c The common clock framework changes for 3.11 include new clock drivers
across several different platforms and architectures, fixes to existing
 drivers, a MAINTAINERS file fix and improvements to the basic clock
 types that allow them to be of use to more platforms than before. Only a
 few fixes to the core framework are included with most all of the
 changes landing in the various clock drivers themselves.
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Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux

Pull clock framework updates from Mike Turquette:
 "The common clock framework changes for 3.11 include new clock drivers
  across several different platforms and architectures, fixes to
  existing drivers, a MAINTAINERS file fix and improvements to the basic
  clock types that allow them to be of use to more platforms than before.

  Only a few fixes to the core framework are included with most all of
  the changes landing in the various clock drivers themselves."

* tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux: (55 commits)
  clk: tegra: fix ifdef for tegra_periph_reset_assert inline
  clk: tegra: provide tegra_periph_reset_assert alternative
  clk: exynos4: Fix clock aliases for cpufreq related clocks
  clk: samsung: Add MUX_FA macro to pass flag and alias
  clk: add support for Rockchip gate clocks
  clk: vexpress: Make the clock drivers directly available for arm64
  clk: vexpress: Use full node name to identify individual clocks
  clk: tegra: T114: add DFLL DVCO reset control
  clk: tegra: T114: add DFLL source clocks
  clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
  clk: gate: add CLK_GATE_HIWORD_MASK
  clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
  clk: mux: add CLK_MUX_HIWORD_MASK
  clk: Always notify whole subtree when reparenting
  MAINTAINERS: make drivers/clk entry match subdirs
  clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate
  clk: use clk_get_rate() for debugfs
  clk: tegra: Use override bits when needed
  clk: tegra: override bits for Tegra30 PLLM
  clk: tegra: override bits for Tegra114 PLLM
  ...
2013-07-03 11:54:50 -07:00
Linus Torvalds 42daabf62b ARM SoC late changes
These are changes that arrived a little late before the merge
 window or that have multiple dependencies on previous branches
 so they did not fit into one of the earlier ones. There
 are 10 branches merged here, a total of 39 non-merge commits.
 Contents are a mixed bag for the above reasons:
 
 * Two new SoC platforms: ST microelectronics stixxxx and
   the TI 'Nspire' graphing calculator. These should have
   been in the 'soc' branch but were a little late
 * Support for the Exynos 5420 variant in mach-exynos,
   which is based on the other exynos branches to avoid
   conflicts.
 * Various small changes for sh-mobile, ux500 and davinci
 * Common clk support for MSM
 
 Conflicts:
 * In Kconfig.debug, various additions trivially conflict,
   the list should be kept in alphabetical order when
   resolving.
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Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late changes from Arnd Bergmann:
 "These are changes that arrived a little late before the merge window
  or that have multiple dependencies on previous branches so they did
  not fit into one of the earlier ones.  There are 10 branches merged
  here, a total of 39 non-merge commits.  Contents are a mixed bag for
  the above reasons:

   * Two new SoC platforms: ST microelectronics stixxxx and the TI
     'Nspire' graphing calculator.  These should have been in the 'soc'
     branch but were a little late
   * Support for the Exynos 5420 variant in mach-exynos, which is based
     on the other exynos branches to avoid conflicts.
   * Various small changes for sh-mobile, ux500 and davinci
   * Common clk support for MSM"

* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
  ARM: ux500: bail out on alien cpus
  ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins
  serial: sh-sci: Initialise variables before access in sci_set_termios()
  ARM: stih41x: Add B2020 board support
  ARM: stih41x: Add B2000 board support
  ARM: sti: Add DEBUG_LL console support
  ARM: sti: Add STiH416 SOC support
  ARM: sti: Add STiH415 SOC support
  ARM: msm: Migrate to common clock framework
  ARM: msm: Make proc_comm clock control into a platform driver
  ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver
  ARM: msm: Remove clock-7x30.h include file
  ARM: msm: Remove custom clk_set_{max,min}_rate() API
  ARM: msm: Remove custom clk_set_flags() API
  msm: iommu: Use clk_set_rate() instead of clk_set_min_rate()
  msm: iommu: Convert to clk_prepare/unprepare
  msm_sdcc: Convert to clk_prepare/unprepare
  usb: otg: msm: Convert to clk_prepare/unprepare
  msm_serial: Use devm_clk_get() and properly return errors
  msm_serial: Convert to clk_prepare/unprepare
  ...
2013-07-02 14:42:51 -07:00
Linus Torvalds 0bf6a210a4 ARM SoC driver specific changes
These changes are all driver specific and cross over between arm-soc
 contents and some other subsystem, in these cases cpufreq, crypto,
 dma, pinctrl, mailbox and usb, and the subsystem owners agreed to
 have these changes merged through arm-soc. As we proceed to untangle
 the dependencies between platform code and driver code, the amount of
 changes in this category is fortunately shrinking, for 3.11 we have
 16 branches here and 101 non-merge changesets, the majority of which
 are for the stedma40 dma engine driver used in the ux500 platform.
 Cleaning up that code touches multiple subsystems, but gets rid
 of the dependency in the end.
 
 The mailbox code moved out from mach-omap2 to drivers/mailbox
 is an intermediate step and is still omap specific at the moment.
 Patches exist to generalize the subsystem and add other drivers
 with the same API, but those did not make it for 3.11.
 
 Conflicts:
 * In cpu-db8500.c results from the removal of the u8500_of_init_devices
   function in combination with the split of u8500_auxdata_lookup.
 
 * In arch/arm/mach-omap2/devices.c, the includes got reshuffled.
   we need to keep linux/wl12xx.h and linux/platform_data/mailbox-omap.h.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver specific changes from Arnd Bergmann:
 "These changes are all driver specific and cross over between arm-soc
  contents and some other subsystem, in these cases cpufreq, crypto,
  dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have
  these changes merged through arm-soc.

  As we proceed to untangle the dependencies between platform code and
  driver code, the amount of changes in this category is fortunately
  shrinking, for 3.11 we have 16 branches here and 101 non-merge
  changesets, the majority of which are for the stedma40 dma engine
  driver used in the ux500 platform.  Cleaning up that code touches
  multiple subsystems, but gets rid of the dependency in the end.

  The mailbox code moved out from mach-omap2 to drivers/mailbox is an
  intermediate step and is still omap specific at the moment.  Patches
  exist to generalize the subsystem and add other drivers with the same
  API, but those did not make it for 3.11."

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
  crypto: ux500: use dmaengine_submit API
  crypto: ux500: use dmaengine_prep_slave_sg API
  crypto: ux500: use dmaengine_device_control API
  crypto: ux500/crypt: add missing __iomem qualifiers
  crypto: ux500/hash: add missing static qualifiers
  crypto: ux500/hash: use readl on iomem addresses
  dmaengine: ste_dma40: Declare memcpy config as static
  ARM: ux500: Remove mop500_snowball_ethernet_clock_enable()
  ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO
  ARM: ux500: Provide a AB8500 GPIO Device Tree node
  gpio: rcar: fix gpio_rcar_of_table
  gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections
  gpio-rcar: Reference core gpio documentation in the DT bindings
  clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
  ARM: dts: Update Samsung I2S documentation
  ARM: dts: add clock provider information for i2s controllers in Exynos5250
  ARM: dts: add Exynos audio subsystem clock controller node
  clk: samsung: register audio subsystem clocks using common clock framework
  ARM: dts: use #include for all device trees for Samsung
  pinctrl: s3c24xx: use correct header for chained_irq functions
  ...
2013-07-02 14:33:21 -07:00
Linus Torvalds ee1a8d402e ARM SoC device tree changes
These changes from 30 individual branches for the most part update device
 tree files, but there are also a few source code changes that have crept
 in this time, usually in order to atomically move over a driver from
 using hardcoded data to DT probing.
 
 A number of platforms change their DT files to use the C preprocessor,
 which is causing a bit of churn, but that is hopefully only this once.
 
 There are a few conflicts with the other branches unfortunately:
 
 * in exynos5440.dtsi and kirkwood-6281.dtsi, device nodes are added
   from multiple branches. Need to be careful to have the right
   set of closing braces as git gets this one wrong.
 
 * In kirkwood.dtsi, one 'ranges' line got split into two lines, while
   another line got added. Order of the lines does not matter.
 
 * in sama5d3.dtsi, some cleanup was merged the wrong way, causing
   a bogus conflict. We want the 'dmas' and 'dma-names' properties
   to get added here.
 
 * Two lines got removed independently in arch/arm/mach-mxs/mach-mxs.c
 
 * Contents get added independently in arch/arm/mach-omap2/cclock33xx_data.c
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree changes from Arnd Bergmann:
 "These changes from 30 individual branches for the most part update
  device tree files, but there are also a few source code changes that
  have crept in this time, usually in order to atomically move over a
  driver from using hardcoded data to DT probing.

  A number of platforms change their DT files to use the C preprocessor,
  which is causing a bit of churn, but that is hopefully only this once"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
  ARM: at91: dt: rm9200ek: add spi support
  ARM: at91: dt: rm9200: add spi support
  ARM: at91/DT: at91sam9n12: add SPI DMA client infos
  ARM: at91/DT: sama5d3: add SPI DMA client infos
  ARM: at91/DT: fix SPI compatibility string
  ARM: Kirkwood: Fix the internal register ranges translation
  ARM: dts: bcm281xx: change comment to C89 style
  ARM: mmc: bcm281xx SDHCI driver (dt mods)
  ARM: nomadik: add the new clocks to the device tree
  clk: nomadik: implement the Nomadik clocks properly
  ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
  ARM: dts: omap4-panda: Fix DVI EDID reads
  ARM: dts: omap4-panda: Add USB Host support
  arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
  ARM: shmobile: irqpin: add a DT property to enable masking on parent
  ARM: dts: AM43x EPOS EVM support
  ARM: dts: OMAP5: Add bandgap DT entry
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ...
2013-07-02 14:23:01 -07:00
Tushar Behera 82ba93b27c clk: exynos4: Fix clock aliases for cpufreq related clocks
cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence
we cannot currently pass the clock names through a device tree node.
Instead, we need to make them available through a global alias.

Clock alias modifications for EXYNOS4 specific clocks are as below.

Alias for clock 'arm_clk' is 'armclk'.
Alias for clock 'mout_apll' is 'mout_apll'.
Alias for clock 'mout_core' is 'moutcore'.

For EXYNOS4210, alias for clock 'sclk_mpll' is 'mout_mpll'.
For EXYNOS4412, alias for clock 'mout_mpll_user_c' is 'mout_mpll'.

Some of the clock aliases are newly defined and some are fixed up.

While at it, also modify the debug messages to print the clock
values appropriately.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-22 10:50:54 -07:00
Tushar Behera 41ccf7f2d3 clk: samsung: Add MUX_FA macro to pass flag and alias
Cpufreq driver for some Samsung platforms have not yet been designed as
a platform driver, thereby they can only access clocks with an alias
name.

For EXYNOS4210, one such clock also requires a flag to be set, hence
there is a need to create another macro that can handle both flag and
alias.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-22 10:50:41 -07:00
Chander Kashyap 1609027fc2 clk: exynos5420: register clocks using common clock framework
The EXYNOS5420 clocks are statically listed and registered using
the Samsung specific common clock helper functions.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19 04:09:34 +09:00
Padmavathi Venna 79d743c177 clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19 03:28:43 +09:00
Padmavathi Venna 1241ef94cc clk: samsung: register audio subsystem clocks using common clock framework
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19 03:28:41 +09:00
Tushar Behera 346f372f7b clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clock
Currently 'pmu' clock is not handled by any of the drivers.
Also before the introduction of CCF, this clock was not defined,
hence was left enabled always.

When this clock is disabled, software reset register becomes
inaccessible and system reboot doesn't work.

Upon restoring the default behaviour, system reboot starts working.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11 20:05:48 -07:00
Sachin Kamat 5cd644d837 clk: exynos4: Add additional G2D clocks
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
IP.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-12 04:54:49 +09:00
Doug Anderson 071ff9a36c clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly
The KDIV value is often listed as unsigned but it needs to be treated
as a 16-bit signed value when using it in calculations.  Fix our rate
recalculation to do this correctly.

Before doing this, I tried setting EPLL on exynos5250 to:
  rate, m, p, s, k = 80000000, 107, 2, 4, 43691

This rate is exactly from the table in the exynos5250 user manual.

I read this back as 80750003 with:
  cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate

After this patch, it reads back as 80000003

Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11 09:51:26 -07:00
Tushar Behera 589c603b2c clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock
'mout_mpll' is added the list of parent clocks for 'mout_cpu'.
'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll'
should be added to the list of parent clocks.

This results in an error when cpufreq driver for EXYNOS5250 tries to
set 'mout_mpll' as a parent for 'mout_cpu'.

clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10 15:14:17 -07:00
Tushar Behera 39b72d89eb clk: exynos5250: Update cpufreq related clocks for EXYNOS5250
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot
currently pass the clock names through a device tree node. Instead, we
need to make them available through a global alias.

cpufreq driver for EXYNOS5250 requires four clocks - 'armclk',
'mout_cpu', 'mout_mpll' and 'mout_apll'.

'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll'
and 'mout_apll' are now defined with an alias.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10 15:14:07 -07:00
Tushar Behera 0e56523fd7 clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock
'mout_mpll' is added the list of parent clocks for 'mout_cpu'.
'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll'
should be added to the list of parent clocks.

This results in an error when cpufreq driver for EXYNOS5250 tries to
set 'mout_mpll' as a parent for 'mout_cpu'.

clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29 15:39:28 -07:00
Tushar Behera 37351fd562 clk: exynos5250: Update cpufreq related clocks for EXYNOS5250
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot
currently pass the clock names through a device tree node. Instead, we
need to make them available through a global alias.

cpufreq driver for EXYNOS5250 requires four clocks - 'armclk',
'mout_cpu', 'mout_mpll' and 'mout_apll'.

'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll'
and 'mout_apll' are now defined with an alias.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29 15:39:17 -07:00
Sylwester Nawrocki 056f3d58db clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks
Currently no driver *) handles the sysreg clock, with an assumption
that this clock is always left in its default state (enabled).

Before commit 6e6aac7590
ARM: EXYNOS: Migrate clock support to common clock framework

the sysreg clock was not even defined and hence wasn't handled
explicitly in the kernel.

To restore the previous behaviour disable masking the sysreg clock
off in the clock core by default.

*) Except the Exynos4x12 FIMC-IS driver, which will be modified
   to not touch the sysreg clock.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29 11:52:19 -07:00
Linus Torvalds bb9055b274 ARM: late Exynos multiplatform changes
These continue the multiplatform support for exynos, adding support
 for building most of the essential drivers (clocksource, clk, irqchip)
 when combined with other platforms. As a result, it should become
 really easy to add full multiplatform exynos support in 3.11, although
 we don't yet enable it for 3.10.
 
 The changes were not included in the earlier multiplatform series
 in order to avoid clashes with the other Exynos updates.
 
 This also includes work from Tomasz Figa to fix the pwm clocksource
 code on Exynos, which is not strictly required for multiplatform,
 but related to the other patches in this set and needed as a bug
 fix for at least one board.
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Merge tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull late ARM Exynos multiplatform changes from Arnd Bergmann:
 "These continue the multiplatform support for exynos, adding support
  for building most of the essential drivers (clocksource, clk, irqchip)
  when combined with other platforms.  As a result, it should become
  really easy to add full multiplatform exynos support in 3.11, although
  we don't yet enable it for 3.10.

  The changes were not included in the earlier multiplatform series in
  order to avoid clashes with the other Exynos updates.

  This also includes work from Tomasz Figa to fix the pwm clocksource
  code on Exynos, which is not strictly required for multiplatform, but
  related to the other patches in this set and needed as a bug fix for
  at least one board."

* tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
  ARM: dts: exynops4210: really add universal_c210 dts
  ARM: dts: exynos4210: Add basic dts file for universal_c210 board
  ARM: dts: exynos4: Add node for PWM device
  ARM: SAMSUNG: Do not register legacy timer interrupts on Exynos
  clocksource: samsung_pwm_timer: Work around rounding errors in clockevents core
  clocksource: samsung_pwm_timer: Correct programming of clock events
  clocksource: samsung_pwm_timer: Use proper clockevents max_delta
  clocksource: samsung_pwm_timer: Add support for non-DT platforms
  clocksource: samsung_pwm_timer: Drop unused samsung_pwm struct
  clocksource: samsung_pwm_timer: Keep all driver data in a structure
  clocksource: samsung_pwm_timer: Make PWM spinlock global
  clocksource: samsung_pwm_timer: Let platforms select the driver
  Documentation: Add device tree bindings for Samsung PWM timers
  clocksource: add samsung pwm timer driver
  irqchip: exynos: look up irq using irq_find_mapping
  irqchip: exynos: pass irq_base from platform
  irqchip: exynos: localize irq lookup for ATAGS
  irqchip: exynos: allocate combiner_data dynamically
  irqchip: exynos: pass max combiner number to combiner_init
  ARM: exynos: add missing properties for combiner IRQs
  ...
2013-05-07 11:28:42 -07:00
Tushar Behera 37746c9a2d clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
commit 688f7d8c9f ("clk: exynos5250: Fix divider values for
sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3}
to fix the wrong clock value. Though this fixed issue with Arndale,
it created regressions for other boards like Snow.

On Exynos5250, sclk_mmc<n> is generated like below (as per the clock
names in drivers/clk/samsung/clk-exynos5250.c)

mout_group1_p ==> mout_mmc<n> ==>
		div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n>

Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence
div_mmc_pre<n> was not getting referred in kernel code and depending
on its value set during preboot, sclk_mmc<n> value was different for
various boards.

Setting the correct clock generation path should fix the issues
reported in above referenced commit. The changes committed during the
earlier patch has also been reverted here.

Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-23 19:51:30 -07:00
Arnd Bergmann 25e56eba0a clk: exynos: prepare for multiplatform
The new common clock drivers for exynos are using compile
time constants and soc_is_exynos* macros to provide backwards
compatibility for pre-DT systems, which is not possible with
multiplatform kernels. This moves all the necessary
information back into platform code and removes the mach/*
header inclusions.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Mike Turquette <mturquette@linaro.org>
2013-04-19 23:00:38 +02:00
Tushar Behera 688f7d8c9f clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.

With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.

dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08 23:43:55 +09:00
Sylwester Nawrocki cdbf618ab8 clk: exynos4: export clocks required for fimc-is
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1,
ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1,
DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are
available to the consumers (Exynos4x12 FIMC-IS subsystem).
While at it, indentation of the mux clocks table is
corrected.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08 23:43:54 +09:00
Sachin Kamat 6cec90826e clk: samsung: Fix compilation error
Fixes the below compilation error during non-dt build.
drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext':
drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration]
drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08 23:43:12 +09:00
Leela Krishna Amudala 17d4caccef clk: exynos5250: register display block gate clocks to common clock framework
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi.
Register it to common clock framework.

Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:23 +09:00
Tomasz Figa 6b5756e8bd clk: exynos4: Add support for SoC-specific register save list
This patch extends suspend/resume support for SoC-specific registers to
handle differences in register sets on particular SoCs.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:22 +09:00
Tomasz Figa fb948f74ce clk: exynos4: Add missing registers to suspend save list
This patch adds missing clock control registers to the list of registers
that should be saved across system suspend.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:22 +09:00
Tomasz Figa b950622bdd clk: exynos4: Remove E4X12 prefix from SRC_DMC register
This register is present on all Exynos4 SoCs and so the prefix is
misleading.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:22 +09:00
Tomasz Figa 1f1f326763 clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:16 +09:00
Tomasz Figa 7406ee7c2a clk: exynos4: Add E4210 prefix to LCD1 clock registers
This patch adds E4210 prefix to all registers related to LCD1 clock
domain, because they are present only on Exynos4210.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:16 +09:00
Tomasz Figa 0f1fce908e clk: exynos4: Remove SoC-specific registers from save list
Current clock save list is shared for all Exynos4 SoCs, so it must
contain only registers present in all supported SoCs, because accessing
unavailable registers might have undefined effect.

This patch removes registers specific for particular SoCs from shared
save list, as they should be supported by separate SoC-specific lists.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:16 +09:00
Tomasz Figa 017ab64bdb clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers,
but they are not used for clock definitions. This patch modifies related
clock definitions to use defined macros instead of numeric offsets.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:15 +09:00
Tomasz Figa 6d7190f846 clk: exynos4: Define {E,V}PLL registers
This patch adds preprocessor definitions of EPLL and VPLL registers and
replaces all occurences of offsets of related registers with new
definitions.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:15 +09:00
Tomasz Figa 8e79561c41 clk: exynos4: Add missing mout_sata on Exynos4210
This patch adds missing mout_sata that is a parent of div_sata clock.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:15 +09:00
Andrzej Hajda 1554701528 clk: exynos4: Add missing CMU_TOP and ISP clocks
The patch adds missing clocks to TOP and ISP clock domains.
It also adds clock gates for ISP sub-blocks.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:15 +09:00
Tomasz Figa 8e1ce8393e clk: exynos4: Add G3D clocks
This patch adds clocks needed for G3D block present on Exynos 4 SoCs.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:15 +09:00
Sylwester Nawrocki 1e25810bbb clk: exynos4: Add camera related clock definitions
This patch adds several gate and mux clocks related to camera and ISP
blocks.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:14 +09:00
Tomasz Figa fba79e32a7 clk: exynos4: Export mout_core clock of Exynos4210
This patch enables clock lookup registration for mout_core clock used in
Exynos4210 cpufreq driver.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:14 +09:00
Tomasz Figa a8b5a39ecb clk: samsung: Remove unimplemented ops for pll
Unimplemented clock operations should be simply omitted instead of returning
error values.

This patch removes unimplemented PLL operations to fix problems caused
by returning error code in round_rate callback.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:09 +09:00
Lukasz Majewski e77ba804c1 clk: exynos4: Export clocks used by exynos cpufreq drivers
This patch exports clocks used by Exynos cpufreq drivers to allow lookup
using device tree. (Support to cpufreq drivers will be added in further
patches.)

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:09 +09:00
Tomasz Figa 7bc1d2da0a clk: exynos4: Move dac and mixer to Exynos4210-specific clocks
The sclk_dac and sclk_mixer clocks are not present on Exynos4x12.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:09 +09:00
Tomasz Figa 6976d27415 clk: exynos4: Export sclk_pcm0
This clock is used by PCM interface 0.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:08 +09:00
Tomasz Figa 69aff2fd1d clk: exynos4: Add missing sclk_audio0 clock
This clock is a parent of mout_spdif and sclk_pcm0.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:08 +09:00
Tomasz Figa 4c3cc72cc7 clk: exynos4: Add missing mout_mipihsi clock
This patch adds missing output of mux MIPIHSI which is needed for
div_mipihsi clock.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:08 +09:00
Tomasz Figa 74f7f8ba50 clk: exynos4: Use mout_mpll_user_* on Exynos4x12
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of
sclk_mpll as one of their parents.

This patch moves such clocks from common array into SoC-specific arrays
and adjusts their parent lists respectively.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:08 +09:00
Sylwester Nawrocki 36fc09722d clk: exynos4: Correct sclk_mfc clock definition
This clock must be exported to allow lookup using device tree.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 15:51:07 +09:00
Heiko Stuebner 5e2e0195ec clk: samsung: add infrastructure to add separate aliases
The current code adds aliases, if necessary, directly when adding
the clock, limiting the number of possible aliases to one.

Some platforms need more than one alias, like the hsmmc pclocks on
s3c2416 which need a "hsmmc" and "mmc_busclk.0" alias for the s3c-
sdhci driver.

Therefore add the possibility to separately add clock aliases for
previously created clocks.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-28 14:46:33 +09:00
Heiko Stuebner 6e92bf5a01 clk: samsung: always allocate the clk_table
This is needed to allow looking up previous created clocks when
adding separate aliases to them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-28 14:46:26 +09:00
Heiko Stueber 2466196d3e clk: samsung: fix pm init on non-dt platforms
The clock_init function checked for a dt node, returning immediately
for non-dt machines. This let to the suspend init never being reached
on those non-DT machines.

So fix this by moving the pm init code above the check.

Signed-off-by: Heiko Stueber <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-28 14:46:18 +09:00
Heiko Stuebner 798ed613f5 clk: samsung: register clk_div_tables for divider clocks
On some Samsung platforms divider clocks only use specific divider
combinations like the armdiv on s3c2443 and s3c2416. For these
usecases the generic divider clock already provides the option of
providing a lookup table mapping register values to divider values.

Therefore add a new field to samsung_div_clock and if filled with a
table, use clk_register_divider_table instead of clk_register_divider
to register a divider clock

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-28 14:46:03 +09:00
Thomas Abraham f2585b1cce clk: exynos5440: register clocks using common clock framework
The Exynos5440 clocks are statically listed and registered using the
Samsung specific common clock helper functions.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-25 18:17:05 +09:00
Thomas Abraham 6e3ad26816 clk: exynos5250: register clocks using common clock framework
The Exynos5250 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are supported.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-25 18:16:56 +09:00
Thomas Abraham e062b57177 clk: exynos4: register clocks using common clock framework
The Exynos4 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree
based clock lookup and clkdev based clock lookups are supported.

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-25 18:16:47 +09:00
Thomas Abraham 1c4c5fe0b7 clk: samsung: add pll clock registration helper functions
There are several types of pll clocks used in Samsung SoC's and these
pll clocks can be represented as Samsung specific pll clock types and
registered with the common clock framework. Add support for pll35xx,
pll36xx, pll45xx, pll46xx and pll2550x clock types and helper functions
to register them.

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-25 18:16:37 +09:00
Thomas Abraham 721c42a351 clk: samsung: add common clock framework helper functions for Samsung platforms
All Samsung platforms include different types of clock including
fixed-rate, mux, divider and gate clock types. There are typically
hundreds of such clocks on each of the Samsung platforms. To enable
Samsung platforms to register these clocks using the common clock
framework, a bunch of utility functions are introduced here which
simplify the clock registration process. The clocks are usually
statically instantiated and registered with common clock framework.

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-25 18:16:09 +09:00