Commit Graph

607 Commits

Author SHA1 Message Date
Ben Skeggs a261a20c01 drm/nouveau/fault/gv100-: expose VoltaFaultBufferA
This nvclass exposes the replayable fault buffer, which will be used
by SVM to manage GPU page faults.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:01 +10:00
Ben Skeggs 13e9572906 drm/nouveau/fault/gp100: expose MaxwellFaultBufferA
This nvclass exposes the replayable fault buffer, which will be used
by SVM to manage GPU page faults.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs ab2ee9ffa3 drm/nouveau/mmu/gp100-: support vmms with gcc/tex replayable faults enabled
Some GPU units are capable of supporting "replayable" page faults, where
the execution unit will wait for SW to fixup GPU page tables rather than
triggering a channel-fatal fault.

This feature isn't useful (it's harmful, even) unless something like HMM
is being used to manage events appearing in the replayable fault buffer,
so, it's disabled by default.

This commit allows a client to request it be enabled.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 71871aa6df drm/nouveau/mmu/gp100-: add privileged methods for fault replay/cancel
Host methods exist to do at least some of what we need, but we are not
currently pushing replay/cancels through a channel like UVM does as it's
not clear whether it's necessary in our case (UVM also updates PTEs with
the GPU).

UVM also pushes a software method for fault cancels on Pascal, seemingly
because the host methods don't appear to be sufficient.  If/when we want
to push the replay/cancel on the GPU, we can re-purpose the cancellation
code here to implement that swmthd.

Keep it simple for now, until we figure out exactly what we need here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs a5ff307fe1 drm/nouveau/mmu: add a privileged method to directly manage PTEs
This provides a somewhat more direct method of manipulating the GPU page
tables, which will be required to support SVM.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 8e68271d7c drm/nouveau/mmu: store mapped flag separately from memory pointer
This will be used to support a privileged client providing PTEs directly,
without a memory object to use as a reference.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 2606f29162 drm/nouveau/mmu: support initialisation of client-managed address-spaces
NVKM is currently responsible for managing the allocation of a client's
GPU address-space, but there's various use-cases (ie. HMM address-space
mirroring) where giving a client more direct control is desirable.

This commit allows for a VMM to be created where the area allocated for
NVKM is limited to a client-specified window, the remainder of address-
space is controlled directly by the client.

Leaving a window is necessary to support various internal requirements,
but also to support existing allocation interfaces as not all of the HW
is capable of working with a HMM allocation.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs ae5ea7f6a8 drm/nouveau/gr/gf100-: expose method to determine current context
MMU will need access to this info.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 169f30b35d drm/nouveau/gr/gf100-: expose fecs methods for pausing ctxsw
MMU will need access to these.

v2. Apply fix from Rhys Kidd to send correct FECS method for STOP_CTXSW.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 8d2c1e3376 drm/nouveau/sec2/tu102-: instantiate SEC2 falcon
Required for ACR.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:59 +10:00
Ben Skeggs fdad518362 drm/nouveau/sec2: utilise engine PRI address from TOP
Turing has its SEC2 instance in an alternate location, and this avoids
needing to duplicate the code here for it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:59 +10:00
Ben Skeggs 0457427350 drm/nouveau/nvdec/gp102-: utilise engine PRI address from TOP
Turing has its NVDEC instances in an alternate location.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs 2944b19b5c drm/nouveau/gsp/gv100-: instantiate GSP falcon
We need this for Turing ACR, but it's present from Volta onwards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs eec9ffe47f drm/nouveau/top: add function to lookup PRI address for devices
Will be using this in upcoming changes to avoid the need for entirely
new subdevs to deal with Turing register moves.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs 78cdadb840 drm/nouveau/core: define GSP subdev
Exact meaning of the acronym is unknown, but we need this for Turing ACR.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs b6c8285476 drm/nouveau/ce/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs f10271ffda drm/nouveau/fifo/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs 8603774233 drm/nouveau/disp/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs 954f97983c drm/nouveau/fault/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs ef7664d9df drm/nouveau/bar/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:57 +10:00
Ben Skeggs c011b25421 drm/nouveau/mmu/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:57 +10:00
Ben Skeggs fd95bfbdb9 drm/nouveau/mc/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:57 +10:00
Ben Skeggs b51f9dfac7 drm/nouveau/devinit/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:57 +10:00
Ilia Mirkin fc78224274 drm/nouveau/volt/gf117: fix speedo readout register
GF117 appears to use the same register as GK104 (but still with the
general Fermi readout mechanism).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108980
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:57 +10:00
Ben Skeggs 2d583ade74 drm/nouveau/core: increase maximum number of nvdec instances to 3
RTX2070 appears to have 3 copies of the engine.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:55 +10:00
Ben Skeggs c36322d23d drm/nouveau/ce/tu104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:55 +10:00
Ben Skeggs 641d0b3056 drm/nouveau/fifo/tu104: initial support
Various different bits and pieces vs GV100.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:55 +10:00
Ben Skeggs 114b6556db drm/nouveau/disp/tu104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:54 +10:00
Ben Skeggs 17fb2807c6 drm/nouveau/fault/tu104: initial support
New registers.

Currently uncertain how exactly to mask fault buffer interrupts.  This will
likely be corrected at around the same time as the new MC interrupt stuff
has been properly figured out and implemented.

For the moment, it shouldn't matter too much.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:54 +10:00
Ben Skeggs 838efaa574 drm/nouveau/bar/tu104: initial support
New registers.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:53 +10:00
Ben Skeggs 7986f813c6 drm/nouveau/mmu/tu104: initial support
New flush method.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:53 +10:00
Ben Skeggs f2e55b9ea9 drm/nouveau/mc/tu104: initial support
Things are a bit different here on Turing, and will require further changes
yet once I've investigated them more thoroughly.

For now though, the existing GP100 code is compatible enough with one small
hack to forward on fault buffer interrupts.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:52 +10:00
Ben Skeggs 43d61cda30 drm/nouveau/devinit/tu104: initial support
The GPU executes DEVINIT itself now, which makes our lives a bit easier.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:50 +10:00
Ben Skeggs 344d9c8f35 drm/nouveau/core: recognise TU104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:50 +10:00
Ben Skeggs 9d24907ccf drm/nouveau/fifo/gv100: return work submission token in channel ctor args
The token will also contain runlist ID on Turing, so instead expose it as
an opaque value from NVKM so the client doesn't need to care.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:49 +10:00
Ben Skeggs 85532bd984 drm/nouveau/fifo/gk104-: support enabling privileged ce functions
Will be used by SVM code to allow direct (without going through MMU) memcpy
using the GPU copy engines.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:47 +10:00
Ben Skeggs 86b442d74c drm/nouveau/fifo/gk104-: return channel instance in ctor args
Will be used to match fault buffer entries with a channel.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:47 +10:00
Ben Skeggs 302daab1a7 drm/nouveau/fifo/gf100-: call into BAR to reset BARs after MMU fault
This is needed for Turing, but we're supposed to wait for completion after
re-writing the value on older GPUs anyway.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:47 +10:00
Ben Skeggs 1786bf56e4 drm/nouveau/imem/nv50: support pinning objects in BAR2 and returning address
Various structures are accessed by the GPU through BAR2 for some reason
on newer GPUs.  This commit makes it more convenient to handle.

Will be used for GP100- fault buffers, and GV100- fault method buffers.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:46 +10:00
Ben Skeggs e4f90a35c9 drm/nouveau/tmr: detect stalled gpu timer and break out of waits
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:45 +10:00
Ben Skeggs 7919faab51 drm/nouveau/bios: translate USB-C connector type
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:45 +10:00
Ben Skeggs 2d5257b73e drm/nouveau/bios: translate additional memory types
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:45 +10:00
Ben Skeggs 936a1678f3 drm/nouveau/core: support multiple nvdec instances
Turing GPUs can have more than one.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:44 +10:00
Ilia Mirkin 4126b99e74 drm/nouveau/disp: add a way to configure scrambling/tmds for hdmi 2.0
High pixel clocks are required to use a 40 TMDS divider instead of 10,
and even low ones may optionally use scrambling depending on device
support.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-10-11 09:54:10 +10:00
Nick Desaulniers c9fb2cc84c drm/nouveau/nvif: remove const attribute from nvif_mclass
Similar to commit 0bf8bf50ed ("module: Remove
const attribute from alias for MODULE_DEVICE_TABLE")

Fixes many -Wduplicate-decl-specifier warnings due to the combination of
const typeof() of already const variables.

Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16 18:06:29 +10:00
Ben Skeggs d521097f58 drm/nouveau/gr/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:47 +10:00
Ben Skeggs 6e1f34e33c drm/nouveau/ce/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:46 +10:00
Ben Skeggs 37e1c45a58 drm/nouveau/fifo/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:46 +10:00
Ben Skeggs 290ffeafcc drm/nouveau/disp/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:43 +10:00
Ben Skeggs 6fb566b913 drm/nouveau/dma/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:39 +10:00