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OpenCloudOS-Kernel
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10 Commits

Author SHA1 Message Date
Yong Zhao e02c80d60c Revert "drm/amdgpu: Delete user queue doorbell variables" 
This reverts commit 9006c6bd9059cb9807fa863bafc1d776222cb61b.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-02-19 15:58:26 -05:00
Yong Zhao 828845b7c8 drm/amdgpu: Add first_non_cp and last_non_cp in amdgpu_doorbell_index 
They will be used to inform KFD the doorbell range not usable for CP.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-02-18 18:00:16 -05:00
Yong Zhao c0d9271ecb drm/amdgpu: Delete user queue doorbell variables 
They are no longer used, so delete them to avoid confusion.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-02-13 17:51:10 -05:00
Oak Zeng fd4855409f drm/amdgpu: Add per device sdma_doorbell_range field 
Different ASIC has different sdma doorbell range. Add
a per device sdma_doorbell_range field and initialize
it.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-01-25 16:15:34 -05:00
Oak Zeng 898e0d9d40 drm/amdgpu: Use sdma_engine array 
Use sdma_engine[8] array instead of sdma_engine0~7 so it is easier
to program.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-01-14 15:04:30 -05:00
Oak Zeng 062f380725 drm/amdgpu: Vega10 doorbell index initialization 
v2: Use enum definition instead of hardcoded value
v3: Remove unused enum definition

Signed-off-by: Oak Zeng <ozeng@amd.com>
Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-11-28 15:55:31 -05:00
Rex Zhu 73b1917454 drm/amdgpu: Add CLK IP base offset 
so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-10 14:16:39 -05:00
Evan Quan 1b59fb036a drm/amdgpu: add MP1 and THM hw ip base reg offset 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:14:01 -05:00
Hawking Zhang f797dd5184 drm/amdgpu: include new ip and ip offset headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:13 -05:00
Shaoyun Liu 4522824c48 drm/amdgpu: Dynamic initialize IP base offset 
The base offsets of the IP blocks may change across
asics even though the relative register offsets
are the same for an IP.  Handle this dynamically.

Acked-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-08 11:16:51 -05:00