Add support for identifying the RZ/V2M (R9A09G011) SoC.
Note that the SoC does not have a identification register.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[biju: removed config changes ]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221116102140.852889-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
GPIOLIB and PINCTRL config options are required by all ARM32/ARM64/RISC-V
Renesas SoCs, so instead of selecting them under ARCH_RENESAS for each
architecture just explicitly select them under SOC_RENESAS config option
which will be visible for all the three architectures (if ARCH_RENESAS is
enabled).
Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220919104606.96553-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Select RENESAS_RZG2L_IRQC config option if ARCH_RZG2L is enabled
so that IRQC driver is enabled on RZ/G2L (and alike) SoC's.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220718192824.7246-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reduce the sizes of the rcar_sysc_area and rcar_gen4_sysc_area
structures:
- parent is in the range [-1..32] or [-1..64], so s8 is sufficient,
- flags needs just 3 bits (for now), so u8 is plenty.
This reduces kernel size by:
- 288 bytes for an R-Car Gen1+Gen2 kernel (arm32),
- 1772 bytes for an R-Car Gen3+Gen4 kernel (arm64).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/cbbc8f464743d636895c048de61aa610d75392de.1654701156.git.geert+renesas@glider.be
The PDR values for the A2DP1 and A2CV[2357] power areas on R-Car V3U are
incorrect (copied-and-pasted from A2DP0 and A2CV[0146]).
Fix them.
Reported-by: Renesas Vietnam via Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Fixes: 1b4298f000 ("soc: renesas: r8a779a0-sysc: Add r8a779a0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87bc2e70ba4082970cf8c65871beae4be3503189.1654696188.git.geert+renesas@glider.be
PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs.
Without these configs, the clocks used by the PCI bridge are not
enabled and so accessing the devices leads to a kernel crash:
Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848
Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20220422120850.769480-5-herve.codina@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The Renesas RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SoCs have identical IP
blocks for which drivers are common. To avoid updating the Kconfig
files for drivers in common to each SoC, introduce the ARCH_RZG2L config
option.
The ARCH_RZG2L config option will be selected by the above mentioned
SoCs, and the ARCH_RZG2L config option will be used as a dependency for
the drivers in common.
While at it, move PM and PM_GENERIC_DOMAINS under the ARCH_RZG2L config
option instead of keeping it for individual SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220224092114.25737-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Explicitly select PM and PM_GENERIC_DOMAINS configs for ARCH_R9A07G044
and ARCH_R9A07G054 configs. PM and PM_GENERIC_DOMAINS configs are
required for RZ/{G2L,V2L} SoC without these configs the SMARC EVK's
won't boot.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220221222450.5393-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
As per RZ/G2L HW manual (Rev.1.00 Sep, 2021) DEV_ID [31:28] indicates
product revision. Use this information to populate the revision info
for RZ/G2L family.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220121014117.21248-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for R-Car S4-8 (R8A779F0) to the R-Car RST driver.
The register map of R-Car S4-8 is the same as R-Car V3U so that
renames "V3U" and "r8a779a0" to "Gen4".
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-11-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Currently renesas_soc_init() scans the whole device tree up to three
times, to find a device node describing a product register.
Furthermore, the product register handling for the different variants is
very similar, with the major difference being the location of the
product bitfield inside the product register.
Reduce scanning to a single pass using of_find_matching_node_and_match()
instead. Switch to a common handling of product registers, by storing
the intrinsics of each product register type in the data field of the
corresponding match entry.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/057721f46c7499de4133135488f0f3da7fb39265.1636570669.git.geert+renesas@glider.be
R-Car Gen3 SoC series has a realtime processor, the boot
address of this processor can be set thanks to CR7BAR register
of the reset module.
Export this function so that it's possible to set the boot
address from a remoteproc driver.
Also drop the __initdata qualifier on rcar_rst_base,
since we will use this address later than init time.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Link: https://lore.kernel.org/r/20211022122101.66998-1-julien.massot@iot.bzh
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for identifying the remaining R-Car Gen3e SoCs: R-Car H3e
(R8A779M0), M3e (R8A779M2), M3Ne (R8A779M4), M3Ne-2G (R8A779M5), E3e
(R8A779M6), D3e (R8A779M7), and H3Ne (R8A779M8).
As these are different gradings of the already supported R-Car Gen3
SoCs, support for them is enabled through the existing ARCH_R8A779*
configuration symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ccf2206b24147b3d977e4119bbdefaedceb28644.1628766192.git.geert+renesas@glider.be
strcpy() performs no bounds checking on the destination buffer. This
could result in linear overflows beyond the end of the buffer, leading
to all kinds of misbehaviors. So, use memcpy() as a safe replacement.
This is a previous step in the path to remove the strcpy() function
entirely from the kernel.
Signed-off-by: Len Baker <len.baker@gmx.com>
Link: https://lore.kernel.org/r/20210808125012.4715-3-len.baker@gmx.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for identifying the R-Car H3e-2G (R8A779M1) and R-Car M3e-2G
(R8A779M3) SoCs.
As these are different gradings of the already supported R-Car H3 ES3.0
(R8A77951) and M3-W+ (R8A77961) SoCs, support for them is enabled
through the existing ARCH_R8A77951 and ARCH_R8A77961 configuration
symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/42b4578ab4739cb48ec3aed0a447fc40c34de1e5.1626708063.git.geert+renesas@glider.be
Add support for reading the LSI DEVID register which is present in
SYSC block of RZ/G2{L,LC} SoC's.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609163717.3083-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add ARCH_R9A07G044 as a configuration symbol for the new Renesas
RZ/G2L SoC variants.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Currently, there are two drivers binding to the R-Mobile System
Controller (SYSC):
- The rmobile-sysc driver registers PM domains from a core_initcall(),
and does not use a platform driver,
- The optional rmobile-reset driver registers a reset handler, and
does use a platform driver.
As fw_devlink only considers devices, commit bab2d712ee ("PM:
domains: Mark fwnodes when their powerdomain is added/removed") works
only for PM Domain drivers where the DT node is a real device node, and
not for PM Domain drivers using a hierarchical representation inside a
subnode. Hence if fw_devlink is enabled, probing of on-chip devices
that are part of the SYSC PM domain is deferred until the optional
rmobile-reset driver has been bound. If the rmobile-reset driver is
not available, this will never happen, and thus lead to complete system
boot failures.
Fix this by explicitly marking the fwnode initialized.
Suggested-by: Saravana Kannan <saravanak@google.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Saravana Kannan <saravanak@google.com>
Link: https://lore.kernel.org/r/20210216123958.3180014-1-geert+renesas@glider.be
As of commit b587288001 ("ARM: shmobile: R-Mobile: Remove legacy
PM Domain code"), the R-Mobile System Controller driver no longer
handles the adding of platform devices to PM Domains, but delegates that
to the PM Domain core code.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210205132141.1920137-1-geert+renesas@glider.be
The R-Car System Controller (SYSC) driver registers PM domains from an
early_initcall(). It does not use a platform driver, as secondary CPU
startup on R-Car H1 needs to control the CPU power domains, before
initialization of the driver framework.
As fw_devlink only considers devices, it does not know that the System
Controller is ready. Hence probing of on-chip devices that are part of
the SYSC PM domain fails if fw_devlink is enabled:
probe deferral - supplier e6180000.system-controller not ready
Fix this by setting the OF_POPULATED flag for the SYSC device node after
successful initialization. This will make of_link_to_phandle() ignore
the SYSC device node as a dependency, and consumer devices will be
probed again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Saravana Kannan <saravanak@google.com>
Link: https://lore.kernel.org/r/20210128082847.2205950-1-geert+renesas@glider.be
There is no reason to keep on using the __raw_{read,write}l() I/O
accessors in Renesas ARM driver code. Switch to using the plain
{read,write}l() I/O accessors, to have a chance that this works on
big-endian.
Suggested-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201119125214.4065925-1-geert+renesas@glider.be
This code needs to call iounmap() on one error path.
Fixes: 2173fc7cb6 ("ARM: shmobile: R-Mobile: Add DT support for PM domains")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/20200923113142.GC1473821@mwanda
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for R-Car V3U (R8A779A0) SoC power areas and register
access, because register specification differs from R-Car Gen2/3.
Inspired by patches in the BSP by Tho Vu.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599810232-29035-5-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
For easy understanding of architecture and alphabetical merging, this
patch uses ARM32/ARM64 for description.
This prepares for sorting the menu.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87bliiv54u.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Now, Renesas SoC drivers are under menu, but current descriptions are
not aligned.
This patch aligns them.
- Emma Mobile EV2
- RZ/A1H (R7S72100)
...
- R-Car H2 (R8A77900)
...
- Renesas R-Car H3 ES1.x SoC Platform
...
- R-Car H2 System Controller support
- R-Car M2-W/N System Controller support
- R-Car V2H System Controller support
- R-Car E2 System Controller support
- R-Car H3 System Controller support
- R-Car M3-W System Controller support
- R-Car M3-W+ System Controller support
- R-Car M3-N System Controller support
+ SoC Platform support for Emma Mobile EV2
+ SoC Platform support for RZ/A1H+
...
+ SoC Platform support for R-Car H2
...
+ SoC Platform support for R-Car H3 ES1.x
...
+ System Controller support for R-Car H2
+ System Controller support for R-Car M2-W/N
+ System Controller support for R-Car V2H
+ System Controller support for R-Car E2
+ System Controller support for R-Car H3
+ System Controller support for R-Car M3-W
+ System Controller support for R-Car M3-W+
+ System Controller support for R-Car M3-N
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87zh6kyedc.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Renesas related SoC settings are located on TOP level menu,
thus it is very verbose.
This patch groups Renesas related settings into
"Renesas SoC driver support" menu.
And it aligns config menu names.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87k0xxho7t.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
These are the usual updates for SoC specific device drivers and related
subsystems that don't have their own top-level maintainers:
- ARM SCMI/SCPI updates to allow pluggable transport layers
- TEE subsystem cleanups
- A new driver for the Amlogic secure power domain controller
- Various driver updates for the NXP Layerscape DPAA2, NXP i.MX SCU and
TI OMAP2+ sysc drivers.
- Qualcomm SoC driver updates, including a new library module for
"protection domain" notifications
- Lots of smaller bugfixes and cleanups in other drivers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-drivers-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"These are the usual updates for SoC specific device drivers and
related subsystems that don't have their own top-level maintainers:
- ARM SCMI/SCPI updates to allow pluggable transport layers
- TEE subsystem cleanups
- A new driver for the Amlogic secure power domain controller
- Various driver updates for the NXP Layerscape DPAA2, NXP i.MX SCU
and TI OMAP2+ sysc drivers.
- Qualcomm SoC driver updates, including a new library module for
"protection domain" notifications
- Lots of smaller bugfixes and cleanups in other drivers"
* tag 'arm-drivers-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (70 commits)
soc: fsl: qe: fix sparse warnings for ucc_slow.c
soc: fsl: qe: ucc_slow: remove 0 assignment for kzalloc'ed structure
soc: fsl: qe: fix sparse warnings for ucc_fast.c
soc: fsl: qe: fix sparse warnings for qe_ic.c
soc: fsl: qe: fix sparse warnings for ucc.c
soc: fsl: qe: fix sparse warning for qe_common.c
soc: fsl: qe: fix sparse warnings for qe.c
soc: qcom: Fix QCOM_APR dependencies
soc: qcom: pdr: Avoid uninitialized use of found in pdr_indication_cb
soc: imx: drop COMPILE_TEST for IMX_SCU_SOC
firmware: imx: add COMPILE_TEST for IMX_SCU driver
soc: imx: gpc: fix power up sequencing
soc: imx: increase build coverage for imx8m soc driver
soc: qcom: apr: Add avs/audio tracking functionality
dt-bindings: soc: qcom: apr: Add protection domain bindings
soc: qcom: Introduce Protection Domain Restart helpers
devicetree: bindings: firmware: add ipq806x to qcom_scm
memory: tegra: Correct debugfs clk rate-range on Tegra124
memory: tegra: Correct debugfs clk rate-range on Tegra30
memory: tegra: Correct debugfs clk rate-range on Tegra20
...
Phil Edworthy