Commit Graph

61 Commits

Author SHA1 Message Date
Eddie Huang 47e90154fa soc: mediatek: add scpsys support active_wakeup
Register gpd_dev_ops.active_wakeup function to support keep power
during suspend state. And add flag to each power domain to
decide whether keep power during suspend or not.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-09-27 15:18:33 +02:00
Henry Chen bbe379fc7c soc: mediatek: Move the initial setting of pmic wrap interrupt before requesting irq.
The watchdog may not be initialized by the bootloader, even if the rest
of the pwrap is. Move the watchdog initialization out of pwrap_init() to
make sure the watchdog is always initialized and not only when the pwrap
is uninitialized.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-09-27 13:56:08 +02:00
Matthias Brugger 9dd068a4b8 soc: mediatek: Fix SCPSYS compilation
SCPSYS driver misses the module.h include which makes it fail
when compiling with allmodconf.

This patch fixes this.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-05 11:12:44 +02:00
Krzysztof Kozlowski 3fd4079fe2 soc: mediatek: Drop owner assignment from platform_driver
platform_driver does not need to set an owner because
platform_driver_register() will set it.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-07-10 16:38:44 +02:00
Sascha Hauer c84e358718 soc: Mediatek: Add SCPSYS power domain driver
This adds a power domain driver for the Mediatek SCPSYS unit.

The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.

For now this driver only adds power domain support, the more
advanced features are not yet supported. The driver implements
the generic PM domain device tree bindings, the first user will
most likely be the Mediatek AFE audio driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-07-06 18:36:32 +02:00
Sascha Hauer 16a624a9c8 soc: mediatek: Add infracfg misc driver support
This adds support for some miscellaneous bits of the infracfg controller.
The mtk_infracfg_set/clear_bus_protection functions are necessary for
the scpsys power domain driver to handle the bus protection bits which
are contained in the infacfg register space.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-07-06 18:36:31 +02:00
Matthias Brugger 2a910d139e soc: mediatek: Add compile dependency to pmic-wrapper
The pmic-wrapper calls the reset controller. If CONFIG_RESET_CONTROLLER
is not set, compilation fails with:
drivers/soc/mediatek/mtk-pmic-wrap.c: In function ‘pwrap_probe’:
drivers/soc/mediatek/mtk-pmic-wrap.c:836:2: error: implicit declaration of function ‘devm_reset_control_get’ [-Werror=implicit-function-declaration]

This patch sets the dependency in the Kconfig file.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-05-27 16:27:05 +02:00
Sascha Hauer d956b80ac7 soc: mediatek: PMIC wrap: Fix register state machine handling
When the PMIC wrapper state machine has read a register it goes into the
"wait for valid clear" (vldclr) state. The state machine stays in this
state until the VLDCLR bit is written to. We should write this bit after
reading a register because the SCPSYS won't let the system go into
suspend as long as the state machine waits for valid clear.

Since now we never leave the state machine in vldclr state we no longer
have to check for this state on pwrap_read/pwrap_write entry and can
remove the corresponding code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-05-27 14:11:41 +02:00
Sascha Hauer d71c11f3bd soc: mediatek: PMIC wrap: Fix clock rate handling
replace chipselect extension values based on SPI clock with hardcoded SoC
specific values.

The PMIC wrapper has the ability of extending the chipselects by configurable
amounts of time. We configured the values based on the rate of SPI clock, but
this is wrong. The delays should be configured based on the internal PMIC clock
that latches the values from the SPI bus to the internal PMIC registers. By
default this clock is 24MHz. Other clock frequencies are for debugging only
and can be removed from the driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-05-27 14:11:41 +02:00
Thierry Reding 7a4261d5d3 soc/mediatek: Remove unused variables
The PMIC wrapper driver adds a couple of variables that are never used.
Remove them to avoid build warnings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-04-13 10:35:53 +02:00
Flora Fu 1f022d84bd soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs
This adds support for the PMIC wrapper found on MediaTek MT8135 and
MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these
are currently not supported.

On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via
SPI. The SPI master interface is not directly visible to the CPU, but
only through the PMIC wrapper inside the SoC. The communication between
the SoC and the PMIC can optionally be encrypted. Also a non standard
Dual IO SPI mode can be used to increase speed. The MT8135 also supports
a special feature named "IP Pairing". With IP Pairing the pins of some
SoC internal peripherals can be on the PMIC. The signals of these pins
are routed over the SPI bus using the pwrap bridge. Because of these
optional non SPI conform features the PMIC driver is not implemented as
a SPI bus master driver.

Signed-off-by: Flora Fu, MediaTek
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-30 12:25:40 +02:00