This change modifies gen_pool_get() and devm_gen_pool_create() client
interfaces adding one more argument "name" of a gen_pool object.
Due to implementation gen_pool_get() is capable to retrieve only one
gen_pool associated with a device even if multiple gen_pools are created,
fortunately right at the moment it is sufficient for the clients, hence
provide NULL as a valid argument on both producer devm_gen_pool_create()
and consumer gen_pool_get() sides.
Because only one created gen_pool per device is addressable, explicitly
add a restriction to devm_gen_pool_create() to create only one gen_pool
per device, this implies two possible error codes returned by the
function, account it on client side (only misc/sram). This completes
client side changes related to genalloc updates.
[akpm@linux-foundation.org: gen_pool_get() cleanup]
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
New or improved SoC support:
- Addition of support for Atmel's SAMA5D2 SoC
- Addition of Freescale i.MX6UL
- Improved support of TI's DM814x platform
- Misc fixes and improvements for RockChip platforms
- Marvell MVEBU suspend/resume support
A few driver changes that ideally would belong in the drivers branch are
also here (acked by appropriate maintainers):
- Power key input driver for Freescale platforms (svns)
- RTC driver updates for Freescale platforms (svns/mxc)
- Clk fixes for TI DM814/816X
+ a bunch of other changes for various platforms
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"New or improved SoC support:
- add support for Atmel's SAMA5D2 SoC
- add support for Freescale i.MX6UL
- improved support for TI's DM814x platform
- misc fixes and improvements for RockChip platforms
- Marvell MVEBU suspend/resume support
A few driver changes that ideally would belong in the drivers branch
are also here (acked by appropriate maintainers):
- power key input driver for Freescale platforms (svns)
- RTC driver updates for Freescale platforms (svns/mxc)
- clk fixes for TI DM814/816X
+ a bunch of other changes for various platforms"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
ARM: rockchip: pm: Fix PTR_ERR() argument
ARM: imx: mach-imx6ul: Fix allmodconfig build
clk: ti: fix for definition movement
ARM: uniphier: drop v7_invalidate_l1 call at secondary entry
memory: kill off set_irq_flags usage
rtc: snvs: select option REGMAP_MMIO
ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAE
ARM: BCM: Enable ARM erratum 798181 for BRCMSTB
ARM: OMAP2+: Fix power domain operations regression caused by 81xx
ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend
ARM: rockchip: set correct stabilization thresholds in suspend
ARM: rockchip: rename osc_switch_to_32k variable
ARM: imx6ul: add fec MAC refrence clock and phy fixup init
ARM: imx6ul: add fec bits to GPR syscon definition
rtc: mxc: add support of device tree
dt-binding: document the binding for mxc rtc
rtc: mxc: use a second rtc clock
ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake callback
soc: mediatek: Fix SCPSYS compilation
ARM: at91/soc: add basic support for new sama5d2 SoC
...
We should call phy_register_fixup_for_uid() only when CONFIG_PHYLIB
is built-in, otherwise we get the following link error when building
allmodconfig:
arch/arm/mach-imx/built-in.o: In function `imx6ul_init_machine':
:(.init.text+0xa714): undefined reference to `phy_register_fixup_for_uid'
This is the same approach done in mach-imx6q.c and mach-imx6sx.c.
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
* fixes: (28 commits)
ARM: ux500: add an SMP enablement type and move cpu nodes
ARM: dts: keystone: fix dt bindings to use post div register for mainpll
ARM: nomadik: disable UART0 on Nomadik boards
ARM: dts: i.MX35: Fix can support.
ARM: OMAP2+: hwmod: Fix _wait_target_ready() for hwmods without sysc
ARM: dts: add CPU OPP and regulator supply property for exynos4210
ARM: dts: Update video-phy node with syscon phandle for exynos3250
ARM: keystone: dts: rename pcie nodes to help override status
ARM: keystone: dts: fix dt bindings for PCIe
ARM: pxa: fix dm9000 platform data regression
ARM: DRA7: hwmod: fix gpmc hwmod
ARM: dts: Correct audio input route & set mic bias for am335x-pepper
ARM: OMAP2+: Add HAVE_ARM_SCU for AM43XX
MAINTAINERS: digicolor: add dts files
ARM: ux500: fix MMC/SD card regression
ARM: ux500: define serial port aliases
ARM: dts: OMAP5: Add #iommu-cells property to IOMMUs
ARM: dts: OMAP4: Add #iommu-cells property to IOMMUs
ARM: dts: Fix frequency scaling on Gumstix Pepper
ARM: dts: configure regulators for Gumstix Pepper
...
Add FEC MAC refrence clock init.
Add phy fixup init for i.MX6ul 14x14 evk board that installs KSZ8081 phy.
For the phy, there needs extra phy fixup for MII and RMII mode.
Signed-off-by: Fugang Duan <b38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:
IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN
For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Imre Kaloz <kaloz@openwrt.org>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Roland Stigge <stigge@antcom.de>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Daniel Mack <daniel@zonque.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Simtec Linux Team <linux@simtec.co.uk>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Wan ZongShun <mcuos.com@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-omap@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Init data marked const should be annotated with __initconst for
correctness and not __initdata. In some cases the array gathering
references to that data has to be marked const as well. This fixes
LTO builds that otherwise fail with section mismatch errors.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Migrate imx driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.
This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.
Also drop 'clockevent_mode': It was caching the last state of the
clockevent device. The same behavior can be achieved by using
clockevents state helpers. These helpers are only required for oneshot
mode as shutdown/resume wouldn't be done twice by the core.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
If CONFIG_PM is not set the PU power domain needs to be enabled always,
otherwise there are two failure scenarios which will hang the system if
one of the devices in the PU domain is accessed.
1. New DTs (4.1+) drop the "always-on" property from the PU regulator, so
if it isn't properly enabled by the GPC code it will be disabled at the
end of boot.
2. If the bootloader already disabled the PU domain the GPC explicitly
needs to enable it again, even if the kernel doesn't do any power
management. This is a bit hypothetical, as it requires to boot a
mainline kernel on a downstream bootloader, as no mainline bootloader
disables the PM domains.
Cc: <stable@vger.kernel.org> # 4.1
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
To be consistent with other genalloc interface namings, rename
dev_get_gen_pool() to gen_pool_get(). The original omitted "dev_" prefix
is removed, since it points to argument type of the function, and so it
does not bring any useful information.
[akpm@linux-foundation.org: update arch/arm/mach-socfpga/pm.c]
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Mark Brown <broonie@kernel.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Alan Tull <atull@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Our SoC branch usually contains expanded support for new SoCs and
other core platform code. Some highlights from this round:
- sunxi: SMP support for A23 SoC
- socpga: big-endian support
- pxa: conversion to common clock framework
- bcm: SMP support for BCM63138
- imx: support new I.MX7D SoC
- zte: basic support for ZX296702 SoC
Conflicts:
arch/arm/mach-socfpga/core.h
Trivial remove/remove conflict with our cleanup branch.
Resolution: remove both sides
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform support updates from Kevin Hilman:
"Our SoC branch usually contains expanded support for new SoCs and
other core platform code. Some highlights from this round:
- sunxi: SMP support for A23 SoC
- socpga: big-endian support
- pxa: conversion to common clock framework
- bcm: SMP support for BCM63138
- imx: support new I.MX7D SoC
- zte: basic support for ZX296702 SoC"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
ARM: zx: Add basic defconfig support for ZX296702
ARM: dts: zx: add an initial zx296702 dts and doc
clk: zx: add clock support to zx296702
dt-bindings: Add #defines for ZTE ZX296702 clocks
ARM: socfpga: fix build error due to secondary_startup
MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
ARM: ep93xx: simone: support for SPI-based MMC/SD cards
MAINTAINERS: update Shawn's email to use kernel.org one
ARM: socfpga: support suspend to ram
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
ARM: EXYNOS: register power domain driver from core_initcall
ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
ARM: SAMSUNG: Constify platform_device_id
ARM: EXYNOS: Constify irq_domain_ops
ARM: EXYNOS: add coupled cpuidle support for Exynos3250
ARM: EXYNOS: add exynos_get_boot_addr() helper
ARM: EXYNOS: add exynos_set_boot_addr() helper
ARM: EXYNOS: make exynos_core_restart() less verbose
ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
...
A relatively small setup of cleanups this time around, and similar to last time
the bulk of it is removal of legacy board support:
- OMAP: removal of legacy (non-DT) booting for several platforms
- i.MX: remove some legacy board files
Conflicts: None
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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Kevin Hilman:
"A relatively small setup of cleanups this time around, and similar to
last time the bulk of it is removal of legacy board support:
- OMAP: removal of legacy (non-DT) booting for several platforms
- i.MX: remove some legacy board files"
* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits)
ARM: fix EFM32 build breakage caused by cpu_resume_arm
ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state
ARM: v7 setup function should invalidate L1 cache
mach-omap2: Remove use of deprecated marco, PTR_RET in devices.c
ARM: OMAP2+: Remove calls to deprecacted marco,PTR_RET in the files,fb.c and pmu.c
ARM: OMAP2+: Constify irq_domain_ops
ARM: OMAP2+: use symbolic defines for console loglevels instead of numbers
ARM: at91: remove useless Makefile.boot
ARM: at91: remove at91rm9200_sdramc.h
ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h
ARM: at91/pm: use the atmel-mc syscon defines
pcmcia: at91_cf: Use syscon to configure the MC/smc
ARM: at91: declare the at91rm9200 memory controller as a syscon
mfd: syscon: Add Atmel MC (Memory Controller) registers definition
ARM: at91: drop sam9_smc.c
ata: at91: use syscon to configure the smc
ARM: ux500: delete static resource defines
ARM: ux500: rename ux500_map_io
ARM: ux500: look up PRCMU resource from DT
ARM: ux500: kill off L2CC static map
...
- Add new SoC i.MX7D support, which integrates two Cortex-A7 and one
Cortex-M4 cores.
- Support suspend from IRAM on i.MX53, so that DDR pins can be set to
high impedance for more power saving during suspend.
- Move i.MX clock drivers from arch/arm/mach-imx to drivers/clk/imx.
- Move i.MX GPT timer driver from arch/arm/mach-imx into
drivers/clocksource.
- A couple of clock driver update for VF610 and i.MX6Q.
- A few random code correction and improvement.
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Merge tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
The i.MX SoC updates for 4.2:
- Add new SoC i.MX7D support, which integrates two Cortex-A7 and one
Cortex-M4 cores.
- Support suspend from IRAM on i.MX53, so that DDR pins can be set to
high impedance for more power saving during suspend.
- Move i.MX clock drivers from arch/arm/mach-imx to drivers/clk/imx.
- Move i.MX GPT timer driver from arch/arm/mach-imx into
drivers/clocksource.
- A couple of clock driver update for VF610 and i.MX6Q.
- A few random code correction and improvement.
* tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits)
ARM: imx: imx7d requires anatop
clocksource: timer-imx-gpt: remove include of <asm/mach/time.h>
ARM: imx: move timer driver into drivers/clocksource
ARM: imx: remove platform headers from timer driver
ARM: imx: provide gpt device specific irq functions
ARM: imx: get rid of variable timer_base
ARM: imx: define gpt register offset per device type
ARM: imx: move clock event variables into imx_timer
ARM: imx: set up .set_next_event hook via imx_gpt_data
ARM: imx: setup tctl register in device specific function
ARM: imx: initialize gpt device type for DT boot
ARM: imx: define an enum for gpt timer device type
ARM: imx: move timer resources into a structure
ARM: imx: use relaxed IO accessor in timer driver
ARM: imx: make imx51/3 suspend optional
ARM: clk-imx6q: refine sata's parent
ARM: imx: clk-v610: Add clock for I2C2 and I2C3
ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAP
ARM: imx: add imx7d clk tree support
ARM: clk: imx: update pllv3 to support imx7
...
Conflicts:
arch/arm/mach-imx/Kconfig
Like i.MX6, the i.MX7 code calls into the anatop driver, which fails
if that is disabled:
arch/arm/mach-imx/built-in.o: In function `imx7d_init_machine':
arch/arm/mach-imx/mach-imx7d.c:24: undefined reference to `imx_anatop_init'
arch/arm/mach-imx/built-in.o: In function `imx7d_init_irq':
arch/arm/mach-imx/mach-imx7d.c:29: undefined reference to `imx_init_revision_from_anatop'
This patch ensures that for an imx7-only build, we still get anatop
built-in, matching what we do for imx6. We also need to select
HAVE_IMX_MMDC, as that is needed by the anatop code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
After the cleanup on imx timer driver, now it's ready to be moved into
drivers/clocksource/. Let's do it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
It splits irq enable/disable/acknowledge operations into device specific
functions as the hooks in imx_gpt_data, so that we can save the use of
timer_is_xxx() and cpu_is_xxx() checking in these irq functions.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We now have pointer to imx_timer structure available where timer base
address is needed, so we can just kill global timer_base by using
imxtm->base instead.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It defines offset of gpt registers TSTAT, TCN and TCMP per device
type in imx_gpt_data, so that these registers can be accessed in an
way without timer_is_v2() checking.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since we now have imx_timer structure, it makes more sense to move those
clock event related variables into the structure, so that we can save
some global variables.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It creates a gpt device speicific data structure and adds function hook
gpt_setup_tctl in there to set up gpt TCTL register.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use different initialization function in CLOCKSOURCE_OF_DECLARE() to
initialize gpt device type for DT boot.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Define an enum for gpt timer device type in include/soc/imx/timer.h to
tell the gpt block differences among SoCs. Update non-DT users (clock
drivers) to pass the device type.
As we now have include/soc/imx/timer.h, the declaration of
mxc_timer_init() is moved into there as the best fit.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of passing around as individual argument, let's move timer
resources like irq and clocks together with base address into a data
structure, and pass pointer of the structure as argument to simplify
the function call interface.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed
which is endian-safe, as a step of moving the driver code into folder
drivers/clocksource.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
A recent change to the imx53 power management caused a build
regression when CONFIG_SOC_IMX53 is disabled:
mach-imx/built-in.o:(.init.rodata+0x60): undefined reference to `imx53_suspend'
mach-imx/built-in.o:(.init.rodata+0x64): undefined reference to `imx53_suspend_sz'
This avoids the problem by compiling the code in question
conditionally on the presence of CONFIG_SOC_IMX53. For
consistency, I'm also changing the same thing for
CONFIG_SOC_IMX51.
An additional benefit of this approach is reduced code size
for kernels that only include support for one of the two
SoCs.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 1579c7b9fe ("ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use the generic mechanism to declare a bitmap instead of unsigned long.
Signed-off-by: Joe Perches <joe@perches.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
In order to save power the DDR pins should be put into high
impedance when in suspend to RAM.
This requires manually requesting self refresh (rather than using the
automatic mode implemented by the CCM / ESDCTL), followed by
reconfiguring the IOMUXC.
Of course the code to do this cannot itself run from DDR so the
code is copied to and executed from internal memory.
In my tests using a custom i.MX53 board with LPDDR2 RAM
this reduced the suspend power consumption from 200mW to 60mW.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Include the "common.h" header file to fix the following sparse warning:
arch/arm/mach-imx/mmdc.c:66:5: warning: symbol 'imx_mmdc_get_ddr_type' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The comments were corrected as the following to reflect
the real situation of Freescale MXC timer IP block.
There are totally 4 version of the timer on Freescale i.MX SoCs.
Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Removed the duplicated function declaration of mxc_timer_init
which was already declared in drivers/clk/imx/clk.h.
Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function")
moves imx6_set_lpm() from clock init function into
imx6_pm_common_init(). This causes a hang when cpuidle support is
enabled. The reason for that is ARM core clock is shut down
unexpectedly by WAIT mode. It happens with the following call stack:
cpuidle_register_governor()
cpuidle_switch_governor()
cpuidle_uninstall_idle_handler()
synchronize_sched()
wait_rcu_gp()
wait_for_completion()
When wait_for_completion() is called as above, all cores are idle/WFI.
Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a
hardware shutdown of the ARM core clock.
To fix the regression, we need to ensure that CCM_CLPCR_LPM is
initialized into RUN mode earlier than cpuidle governor registration,
which is a postcore_initcall. This patch creates function
imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into
RUN mode, and have the function called from machine .init_irq hook,
which should be early enough.
Reported-by: Kevin Hilman <khilman@kernel.org>
Fixes: 8fb76a07e2 ("ARM: imx6: set initial power mode in pm function")
Tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
After the cleanup on clock drivers, they are now ready to be moved into
drivers/clk. Let's move them into drivers/clk/imx folder.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
With the cleanup done before, we now can simply define base address and
irq as needed in clock driver, to get those platform header inclusions
removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of calling cpu_is_xxx() in clk-pllv1 driver, let's add clk-pllv1
type support to handle the difference/quirk in particular SoC designs.
Doing so will help get clk-pllv1 driver ready for being moved out of
arch/arm/mach-imx folder.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As we're about to move clock drivers out of arch/arm/mach-imx,
cpu_is_xxx() shouldn't be used any more. Let's avoid the call by
looking at the device tree machine compatible string to determine
which SoC the clock driver is running on.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We are about to move imx6 clock driver into drivers/clk, so let's get
imx6 pm code map CCM block on its own rather than relying on clock
driver to do the mapping.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Rather than setting initial low-power mode in every single i.MX6 clock
initialization function, we should really do that in pm code. Let's
move imx6q_set_lpm(WAIT_CLOCKED) call into imx6_pm_common_init().
While at it, let's rename the function to imx6_set_lpm() since it's
actually common for all i.MX6 SoCs.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We are about to move imx5 clock driver into drivers/clk, so let's get
imx5 pm code map CCM block on its own rather than relying on clock
driver to do the mapping.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The revision definitions and declarations are widely used by clock
drivers. As a step of moving clock drivers out of arch/arm/mach-imx,
let's create header include/soc/imx/revision.h to accommodate them.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Pass physical address of timer block to mxc_timer_init() call, which in
turn does dynamic mapping within the function. Thus, we can avoid using
static mapping in clock drivers.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.
This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.
ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.
Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Merge cleanups from Russell King:
* 'for-arm-soc' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: Show proper respect for Heinrich Hertz by using the correct unit for frequency
If the devicetree is too old and does not provide the regulator and clocks
for the power domain, we need to avoid registering the power domain.
Otherwise runtime PM will try to control the domain, which will lead to
machine hangs without the proper DT configuration data.
This restores functionality to the kernel 4.0 level if an old DT is
detected, where the power domain is constantly powered on.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The GPC rewrite to IRQ domains has been on the premise that it may break
suspend/resume for new kernels on old DT, but otherwise keep things working
from a user perspective. This was an accepted compromise to be able to move
the GIC cleanup forward.
What actually happened was that booting a new kernel on an old DT crashes
before even the console is up, so the user does not even see the warning
that the DT is too old. The warning message suggests that this has been
known before, which is clearly unacceptable.
Fix the early crash by mapping the GPC memory space if the IRQ controller
doesn't claim it. This keeps at least CPUidle and the needed CPU wakeup
workarounds working. With this fixed the system is able to boot up
properly minus the expected suspend/resume breakage.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch allows to build the Kernel for Vybrid (VF6xx) SoC
when ARMv7-M CPU is selected. The resulting image runs on the
secondary Cortex-M4 core. This core has equally access to all
peripherals as the main Cortex-A5 core. However, there is no
resource control mechanism, hence when both cores are used
simultaneously, orthogonal device tree's are required.
The boot CPU is dependent on the SoC variant. The available
boards use mostly variants where the Cortex-A5 is the primary
and hence the boot CPU. Booting the secondary Cortex-M4 CPU
needs SoC specific registers written. There is no in kernel
support for this right now, a external userspace utility
called "m4boot" can be used to boot the kernel:
m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The SI unit of frequency is Hertz, named after Heinrich Hertz, and is
given the symbol "Hz" to denote this. "hz" is not the unit of frequency,
and is in fact meaningless.
Fix arch/arm to correctly use "Hz", thereby acknowledging Heinrich Hertz'
contribution to the modern world.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This platform_driver does not need to set an owner as it will be
populated by the driver core.
The semantic patch that makes this change is available
in scripts/coccinelle/api/platform_no_drv_owner.cocci.
More information about semantic patching is available at
http://coccinelle.lip6.fr/
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
eukrea_mbimxsd35 board has device tree support, so we can get rid of the
board related files.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
My Pengutronix address is not valid anymore, redirect people to the Pengutronix
kernel team.
Reported-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We were expecting to sit on this branch through most of the merge window since
the contents was merged into our tree late, but we ended up sitting on all of
our contents so it can go in with the rest.
The contents here is:
- A large branch of cleanups of the CM/PRM blocks on OMAP.
- A couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- A branch with DT updates for Freescale i.MX. including some shuffling from
.dts to .dtsi (include) files that causes a little churn.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Olof Johansson:
"We were expecting to sit on this branch through most of the merge
window since the contents was merged into our tree late, but we ended
up sitting on all of our contents so it can go in with the rest.
The contents here is:
- a large branch of cleanups of the CM/PRM blocks on OMAP.
- a couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- a branch with DT updates for Freescale i.MX. including some
shuffling from .dts to .dtsi (include) files that causes a little
churn"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits)
ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON
ARM: OMAP4+: control: add support for initializing control module via DT
ARM: dts: dra7: add minimal l4 bus layout with control module support
ARM: dts: omap5: add minimal l4 bus layout with control module support
ARM: OMAP4+: control: remove support for legacy pad read/write
ARM: OMAP4: display: convert display to use syscon for dsi muxing
ARM: dts: omap4: add minimal l4 bus layout with control module support
ARM: dts: am4372: add minimal l4 bus layout with control module support
ARM: dts: am43xx-epos-evm: fix pinmux node layout
ARM: dts: am33xx: add minimal l4 bus layout with control module support
ARM: dts: omap3: add minimal l4 bus layout with control module support
ARM: dts: omap24xx: add minimal l4 bus layout with control module support
ARM: OMAP2+: control: add syscon support for register accesses
ARM: OMAP2+: id: cache omap_type value
ARM: OMAP2+: control: remove API for getting control module base address
ARM: OMAP2+: clock: add low-level support for regmap
ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
ARM: OMAP2+: CM: move SoC specific init calls within a generic API
ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
...
Our SoC branch usually contains expanded support for new SoCs and other core
platform code. In this case, that includes:
- Support for the new Annapurna Labs "Alpine" platform
- A rework greatly simplifying adding new platform support to the MCPM
subsystem (Multi-cluster power management)
- Cpuidle and PM improvements for Exynos3250
- Misc updates for Renesas, OMAP, Meson, i.MX. Some of these could have
gone in other branches but ended up here for various reasons.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"Our SoC branch usually contains expanded support for new SoCs and
other core platform code. In this case, that includes:
- support for the new Annapurna Labs "Alpine" platform
- a rework greatly simplifying adding new platform support to the
MCPM subsystem (Multi-cluster power management)
- cpuidle and PM improvements for Exynos3250
- misc updates for Renesas, OMAP, Meson, i.MX. Some of these could
have gone in other branches but ended up here for various reasons"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
ARM: alpine: add support for generic pci
ARM: Exynos: migrate DCSCB to the new MCPM backend abstraction
ARM: vexpress: migrate DCSCB to the new MCPM backend abstraction
ARM: vexpress: DCSCB: tighten CPU validity assertion
ARM: vexpress: migrate TC2 to the new MCPM backend abstraction
ARM: MCPM: move the algorithmic complexity to the core code
ARM: EXYNOS: allow cpuidle driver usage on Exynos3250 SoC
ARM: EXYNOS: add AFTR mode support for Exynos3250
ARM: EXYNOS: add code for setting/clearing boot flag
ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
ARM: S3C64XX: Use fixed IRQ bases to avoid conflicts on Cragganmore
ARM: cygnus: fix const declaration bcm_cygnus_dt_compat
ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4
ARM: DRA7: hwmod: Add data for GPTimers 13 through 16
ARM: EXYNOS: Remove left over 'extra_save'
ARM: EXYNOS: Constify exynos_pm_data array
ARM: EXYNOS: use static in suspend.c
ARM: EXYNOS: Use platform device name as power domain name
ARM: EXYNOS: add support for async-bridge clocks for pm_domains
ARM: omap-device: add missed callback for suspend-to-disk
...
We've got a fairly large cleanup branch this time. The bulk of this is removal
of non-DT platforms of several flavors:
- Atmel at91 platforms go full-DT, with removal of remaining board-file based
support
- OMAP removes legacy board files for three more platforms
- Removal of non-DT mach-msm, newer Qualcomm platforms now live in mach-qcom
- Freescale i.MX25 also removes non-DT platform support
Most of the rest of the changes here are fallout from the above, i.e. for
example removal of drivers that now lack platforms, etc.
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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"We've got a fairly large cleanup branch this time. The bulk of this
is removal of non-DT platforms of several flavors:
- Atmel at91 platforms go full-DT, with removal of remaining
board-file based support
- OMAP removes legacy board files for three more platforms
- removal of non-DT mach-msm, newer Qualcomm platforms now live in
mach-qcom
- Freescale i.MX25 also removes non-DT platform support"
Most of the rest of the changes here are fallout from the above, i.e. for
example removal of drivers that now lack platforms, etc.
* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (58 commits)
mmc: Remove msm_sdcc driver
gpio: Remove gpio-msm-v1 driver
ARM: Remove mach-msm and associated ARM architecture code
ARM: shmobile: cpuidle: Remove the pointless default driver
ARM: davinci: dm646x: Add interrupt resource for McASPs
ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
ARM: davinci: dm646x: Clean up the McASP DMA resources
ARM: davinci: devices-da8xx: Add support for McASP2 on da830
ARM: davinci: devices-da8xx: Clean up and correct the McASP device creation
ARM: davinci: devices-da8xx: Add interrupt resource to McASP structs
ARM: davinci: devices-da8xx: Add resource name for the McASP DMA request
ARM: OMAP2+: Remove legacy support for omap3 TouchBook
ARM: OMAP3: Remove legacy support for devkit8000
ARM: OMAP3: Remove legacy support for EMA-Tech Stalker board
ARM: shmobile: Consolidate the pm code for R-Car Gen2
ARM: shmobile: r8a7791: Correct SYSCIER value
ARM: shmobile: r8a7790: Correct SYSCIER value
ARM: at91: remove old setup
ARM: at91: sama5d4: remove useless map_io
ARM: at91: sama5 use SoC detection infrastructure
...
- Generic PM domains support update including new PM domain
callbacks to handle device initialization better (Russell King,
Rafael J Wysocki, Kevin Hilman).
- Unified device properties API update including a new mechanism
for accessing data provided by platform initialization code
(Rafael J Wysocki, Adrian Hunter).
- ARM cpuidle update including ARM32/ARM64 handling consolidation
(Daniel Lezcano).
- intel_idle update including support for the Silvermont Core in
the Baytrail SOC and for the Airmont Core in the Cherrytrail and
Braswell SOCs (Len Brown, Mathias Krause).
- New cpufreq driver for Hisilicon ACPU (Leo Yan).
- intel_pstate update including support for the Knights Landing
chip (Dasaratharaman Chandramouli, Kristen Carlson Accardi).
- QorIQ cpufreq driver update (Tang Yuantian, Arnd Bergmann).
- powernv cpufreq driver update (Shilpasri G Bhat).
- devfreq update including Tegra support changes (Tomeu Vizoso,
MyungJoo Ham, Chanwoo Choi).
- powercap RAPL (Running-Average Power Limit) driver update
including support for Intel Broadwell server chips (Jacob Pan,
Mathias Krause).
- ACPI device enumeration update related to the handling of the
special PRP0001 device ID allowing DT-style 'compatible' property
to be used for ACPI device identification (Rafael J Wysocki).
- ACPI EC driver update including limited _DEP support (Lan Tianyu,
Lv Zheng).
- ACPI backlight driver update including a new mechanism to allow
native backlight handling to be forced on non-Windows 8 systems
and a new quirk for Lenovo Ideapad Z570 (Aaron Lu, Hans de Goede).
- New Windows Vista compatibility quirk for Sony VGN-SR19XN (Chen Yu).
- Assorted ACPI fixes and cleanups (Aaron Lu, Martin Kepplinger,
Masanari Iida, Mika Westerberg, Nan Li, Rafael J Wysocki).
- Fixes related to suspend-to-idle for the iTCO watchdog driver and
the ACPI core system suspend/resume code (Rafael J Wysocki, Chen Yu).
- PM tracing support for the suspend phase of system suspend/resume
transitions (Zhonghui Fu).
- Configurable delay for the system suspend/resume testing facility
(Brian Norris).
- PNP subsystem cleanups (Peter Huewe, Rafael J Wysocki).
/
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Merge tag 'pm+acpi-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull power management and ACPI updates from Rafael Wysocki:
"These are mostly fixes and cleanups all over, although there are a few
items that sort of fall into the new feature category.
First off, we have new callbacks for PM domains that should help us to
handle some issues related to device initialization in a better way.
There also is some consolidation in the unified device properties API
area allowing us to use that inferface for accessing data coming from
platform initialization code in addition to firmware-provided data.
We have some new device/CPU IDs in a few drivers, support for new
chips and a new cpufreq driver too.
Specifics:
- Generic PM domains support update including new PM domain callbacks
to handle device initialization better (Russell King, Rafael J
Wysocki, Kevin Hilman)
- Unified device properties API update including a new mechanism for
accessing data provided by platform initialization code (Rafael J
Wysocki, Adrian Hunter)
- ARM cpuidle update including ARM32/ARM64 handling consolidation
(Daniel Lezcano)
- intel_idle update including support for the Silvermont Core in the
Baytrail SOC and for the Airmont Core in the Cherrytrail and
Braswell SOCs (Len Brown, Mathias Krause)
- New cpufreq driver for Hisilicon ACPU (Leo Yan)
- intel_pstate update including support for the Knights Landing chip
(Dasaratharaman Chandramouli, Kristen Carlson Accardi)
- QorIQ cpufreq driver update (Tang Yuantian, Arnd Bergmann)
- powernv cpufreq driver update (Shilpasri G Bhat)
- devfreq update including Tegra support changes (Tomeu Vizoso,
MyungJoo Ham, Chanwoo Choi)
- powercap RAPL (Running-Average Power Limit) driver update including
support for Intel Broadwell server chips (Jacob Pan, Mathias Krause)
- ACPI device enumeration update related to the handling of the
special PRP0001 device ID allowing DT-style 'compatible' property
to be used for ACPI device identification (Rafael J Wysocki)
- ACPI EC driver update including limited _DEP support (Lan Tianyu,
Lv Zheng)
- ACPI backlight driver update including a new mechanism to allow
native backlight handling to be forced on non-Windows 8 systems and
a new quirk for Lenovo Ideapad Z570 (Aaron Lu, Hans de Goede)
- New Windows Vista compatibility quirk for Sony VGN-SR19XN (Chen Yu)
- Assorted ACPI fixes and cleanups (Aaron Lu, Martin Kepplinger,
Masanari Iida, Mika Westerberg, Nan Li, Rafael J Wysocki)
- Fixes related to suspend-to-idle for the iTCO watchdog driver and
the ACPI core system suspend/resume code (Rafael J Wysocki, Chen Yu)
- PM tracing support for the suspend phase of system suspend/resume
transitions (Zhonghui Fu)
- Configurable delay for the system suspend/resume testing facility
(Brian Norris)
- PNP subsystem cleanups (Peter Huewe, Rafael J Wysocki)"
* tag 'pm+acpi-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (74 commits)
ACPI / scan: Fix NULL pointer dereference in acpi_companion_match()
ACPI / scan: Rework modalias creation when "compatible" is present
intel_idle: mark cpu id array as __initconst
powercap / RAPL: mark rapl_ids array as __initconst
powercap / RAPL: add ID for Broadwell server
intel_pstate: Knights Landing support
intel_pstate: remove MSR test
cpufreq: fix qoriq uniprocessor build
ACPI / scan: Take the PRP0001 position in the list of IDs into account
ACPI / scan: Simplify acpi_match_device()
ACPI / scan: Generalize of_compatible matching
device property: Introduce firmware node type for platform data
device property: Make it possible to use secondary firmware nodes
PM / watchdog: iTCO: stop watchdog during system suspend
cpufreq: hisilicon: add acpu driver
ACPI / EC: Call acpi_walk_dep_device_list() after installing EC opregion handler
cpufreq: powernv: Report cpu frequency throttling
intel_idle: Add support for the Airmont Core in the Cherrytrail and Braswell SOCs
intel_idle: Update support for Silvermont Core in Baytrail SOC
PM / devfreq: tegra: Register governor on module init
...
Now that the GPC has been converted to be a full blown irqchip
(and not a mole on the side of the GIC), booting a new kernel
with an old DT is likely to result in a rough ride for the user.
This patch makes sure such a situation is promptly detected and
the user made aware that a DT update is in order.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
While converting the GPC code to a stacked irqchip, we lost the
possibility to change the CPU affinity of an interrupt routed
through the GPC.
This patch restore the expected behaviour by forwarding the
affinity setup to the underlying irqchip (GIC).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The cpu_do_idle() function is always used by the cpuidle drivers.
That led to have each driver including cpuidle.h and proc-fns.h, they are
always paired. That makes a lot of duplicate headers inclusion. Instead of
including both in each .c file, move the proc-fns.h header inclusion in the
cpuidle.h header file directly, so we can save some line of code.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
platform-imxdi_rtc.c is only used by mx25, so it can safely go away now that
mx25 has been converted to dt.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As mx25 has been converted to a dt-only platform, we do not need the "mx25.h"
header file anymore.
Remove it and also clean up all the mx25 occurences from the platform helper
code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We use dynamic memory mapping when using dt, so remove all the static mappings.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We should use dt to retrieve the IIM base address.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
mx25_clocks_init() is only used to register the clocks for non-dt platforms.
As mx25 has been converted to a dt-only platform, we can safely remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Depend the MXC debug board on machines which actually support it.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since commit 035a61c314 ("clk: Make clk API return per-user struct clk
instances"), clk API users can no longer check if two struct clk
pointers are pointing to the same hardware clock, i.e. struct clk_hw, by
simply comparing two pointers. That's because with the per-user clk
change, a brand new struct clk is created whenever clients try to look
up the clock by calling clk_get() or sister functions like clk_get_sys()
and of_clk_get(). This changes the original behavior where the struct
clk is only created for once when clock driver registers the clock to
CCF in the first place. The net change here is before commit
035a61c314 the struct clk pointer is unique for given hardware
clock, while after the commit the pointers returned by clk lookup calls
become different for the same hardware clock.
That said, the struct clk pointer comparing in the code doesn't work any
more. Call helper function clk_is_match() instead to fix the problem.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
As mx25 is a dt-only platform, we can get rid of platform code support files,
which are unused now.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As there is no more mx25 board files, we can turn mx25 into a dt-only platform.
Rename imx25-dt.c to mach-imx25.c to be consistent with the other i.MX SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
eukrea mx25 is well supported in device tree, so let's get rid of its board
files.
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
When generic pm domain support is enabled, the PGC can be used
to completely gate power to the PU power domain containing GPU3D,
GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU
isolation cells and gate power and then disables the PU regulator.
To reenable, the reverse powerup sequence is triggered after the PU
regulator is enabled again.
The GPU and VPU devices in the PU power domain temporarily need
to be clocked during powerup, so that the reset machinery can work.
[Avoid explicit regulator enabling in probe, unless !PM]
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds support for Vybrid's interrupt router. On VF6xx models,
almost all peripherals can be used by either of the two CPU's,
the Cortex-A5 or the Cortex-M4. The interrupt router routes the
peripheral interrupts to the configured CPU.
This IRQ chip driver configures the interrupt router to route
the requested interrupt to the CPU the kernel is running on.
The driver makes use of the irqdomain hierarchy support. The
parent is given by the device tree. This should be one of the
two possible parents either ARM GIC or the ARM NVIC interrupt
controller. The latter is currently not yet supported.
Note that there is no resource control mechnism implemented to
avoid concurrent access of the same peripheral. The user needs
to make sure to use device trees which assign the peripherals
orthogonally. However, this driver warns the user in case the
interrupt is already configured for the other CPU. This provides
a poor man's resource controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Link: https://lkml.kernel.org/r/1425249689-32354-2-git-send-email-stefan@agner.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
imx25-pdk.dts provides a more complete support than the board file version, so
let's get rid of the board file.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use "This enables" in the Kconfig help text to fix grammar.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Also fix all machine files to make use of it and while at it also make
the pad lists __initconst.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the ipg clock's output. The MIPI DSI host
controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk -
the APB clock signal . In order to gate/ungate the ipg clock, this patch adds
a new shared clock gate named as "mipi_ipg".
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output. The MIPI DSI host controller embedded in the
i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and
MIPI core configuration clock. In order to gate/ungate the two MIPI DSI
host controller relevant clocks, this patch adds the mipi_core_cfg clock as
a shared clock gate.
Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
clock, according to the i.MX6q/sdl reference manuals. This clock is
actually the gate for several clocks, including the hsi_tx_sel clock's
output and the video_27m clock's output. So, this patch changes the
hsi_tx clock to be a shared clock gate.
Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr
clock's parent should be the video_27m clock. The i.MX6DL reference manual
has the same statement. This patch changes the hdmi_isfr clock's parent
from the pll3_pfd1_540m clock to the video_27m clock.
Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The Vybrid SoC has only one Cortex-A5 core and hence should select
the SMP_ON_UP configuration on a SMP kernel.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
of_device_ids (i.e. compatible strings and the respective data) are not
supposed to change at runtime. All functions working with of_device_ids
provided by <linux/of.h> work with const of_device_ids. So mark the
non-const structs in arch/arm as const, too.
While at it also add some __initconst annotations.
Acked-by: Jason Cooper <jason@lakedameon.net>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
New and updated SoC support. Also included are some cleanups where the
platform maintainers hadn't separated cleanups from new developent in
separate branches.
Some of the larger things worth pointing out:
- A large set of changes from Alexandre Belloni and Nicolas Ferre
preparing at91 platforms for multiplatform and cleaning up quite a
bit in the process.
- Removal of CSR's "Marco" SoC platform that never made it out to the
market. We love seeing these since it means the vendor published
support before product was out, which is exactly what we want!
New platforms this release are:
- Conexant Digicolor (CX92755 SoC)
- Hisilicon HiP01 SoC
- CSR/sirf Atlas7 SoC
- ST STiH418 SoC
- Common code changes for Nvidia Tegra132 (64-bit SoC)
We're seeing more and more platforms having a harder time labelling
changes as cleanups vs new development -- which is a good sign that
we've come quite far on the cleanup effort. So over time we might start
combining the cleanup and new-development branches more.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"New and updated SoC support. Also included are some cleanups where
the platform maintainers hadn't separated cleanups from new developent
in separate branches.
Some of the larger things worth pointing out:
- A large set of changes from Alexandre Belloni and Nicolas Ferre
preparing at91 platforms for multiplatform and cleaning up quite a
bit in the process.
- Removal of CSR's "Marco" SoC platform that never made it out to the
market. We love seeing these since it means the vendor published
support before product was out, which is exactly what we want!
New platforms this release are:
- Conexant Digicolor (CX92755 SoC)
- Hisilicon HiP01 SoC
- CSR/sirf Atlas7 SoC
- ST STiH418 SoC
- Common code changes for Nvidia Tegra132 (64-bit SoC)
We're seeing more and more platforms having a harder time labelling
changes as cleanups vs new development -- which is a good sign that
we've come quite far on the cleanup effort. So over time we might
start combining the cleanup and new-development branches more"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
ARM: at91/trivial: unify functions and machine names
ARM: at91: remove at91_dt_initialize and machine init_early()
ARM: at91: change board files into SoC files
ARM: at91: remove at91_boot_soc
ARM: at91: move alternative initial mapping to board-dt-sama5.c
ARM: at91: merge all SOC_AT91SAM9xxx
ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
ARM: digicolor: select syscon and timer
ARM: zynq: Simplify SLCR initialization
ARM: zynq: PM: Fixed simple typo.
ARM: zynq: Setup default gpio number for Xilinx Zynq
ARM: digicolor: add low level debug support
ARM: initial support for Conexant Digicolor CX92755 SoC
ARM: OMAP2+: Add dm816x hwmod support
ARM: OMAP2+: Add clock domain support for dm816x
ARM: OMAP2+: Add board-generic.c entry for ti81xx
ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
ARM: at91: remove unused mach/system_rev.h
ARM: at91: stop using HAVE_AT91_DBGUx
ARM: at91: fix ordering of SRAM and PM initialization
...
imx6q_opp_check_speed_grading() remaps memory to the base variable and
never unmaps it. I can't see how this can be of any use later so here I
unmap it.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add support for clock gating of the SNVS peripheral.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add support for clock gating of UART4 and UART5.
We use these UART's in a (not yet mainlined)
device tree.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As the result of commit b82b6cca48 ("cpuidle: Invert
CPUIDLE_FLAG_TIME_VALID logic"), the flag gets removed and hence we see
the compile error below.
CC arch/arm/mach-imx/cpuidle-imx6sx.o
arch/arm/mach-imx/cpuidle-imx6sx.c:69:13: error: ‘CPUIDLE_FLAG_TIME_VALID’ undeclared here (not in a function)
Since the behavior of the original flag has been the default, we can
simply drop the flag now.
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch introduces an independent cpuidle driver for
i.MX6SX, and supports arm power off in idle, totally
3 levels of cpuidle are supported as below:
1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.
ARM power off can save at least 5mW power.
This patch also replaces imx6q_enable_rbc with imx6_enable_rbc.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Now we support DSM in OCRAM for all i.MX6 SoCs,
the resume entry point is set in asm code of
suspend-imx6.S, so no need to set the resume
entry point for SRC in pre-suspend flow.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Vladimir Zapolskiy