Update global clock controller SDCC2/4 clocks to use the floor rcg ops,
so as to use the rounded down clock rates for these clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
See similar issue solved by commit 5f2420ed21
("clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998")
Without this patch, PCIe PHY init fails:
qcom-qmp-phy 1c06000.phy: pipe_clk enable failed err=-16
phy phy-1c06000.phy.0: phy init failed --> -16
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Fixes: b5f5f525c5 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Several clock controller drivers define a list of clk_hw devices, and then
register those devices in probe() before using common code to process the
rest of initialization. Extend the common code to accept a list of clk_hw
devices to process, thus eliminating many duplicate implementations.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by
the phy during init. The clock needs to be enabled during the init
sequence, but may not be fully active until after the init sequence is
complete. This causes a catch-22 if the clock status is checked during
enable. As a result, skip the checks to avoid the troubling situation.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The usb30_master_clk supports a 60Mhz frequency, but that is missing from
the table of supported frequencies. Add it.
Fixes: b5f5f525c5 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
A branch clock is basically a clock that can be gated for power savings,
but is also what devices/drivers consume. Configuring a branch clock's
rate needs to be done at the source, so for all branch clocks which have
a defined parent, set CLK_SET_RATE_PARENT so that clk_set_rate() calls on
branch clocks can do what is expected. This is important as most drivers
do not check the resulting clock rate after a successful clk_set_rate()
call, thus the driver may get out of sync with the actual hardware state
and weird issues might crop up. This has been observed with issues
getting SDHCI to reliably support "fast" cards such as SDR104.
Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
gcc_lpass_trig_clk is not used downstream, therefore there is no reason to
expect it to be needed for clients. Let's remove it because messing with
the clock has been observed to cause Linux hangs when the qdss_clk is
initialized by rpmcc.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Similar to other qcom targets, gcc_mmss_noc_cfg_ahb_clk should not be
disabled. Any mmss access depends on this clock, and its been observed
that enabling mmssnoc_axi_rpm_clk with rpmcc results in an implicit
access to mmss and will crash the system if gcc_mmss_noc_cfg_ahb_clk is
disabled.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all
sourced off CXO_IN, so parent them off "xo" until a proper link to the
rpmcc can be described in DT.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Drop the halt check of the UFS symbol clocks, in accordance with other
platforms. This makes clk_disable_unused() happy and makes it possible
to turn the clocks on again without an error.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Disabling gcc_hmss_dvm_bus_clk and gcc_lpass_at_clk causes the board to
lock up, and by that preventing the kernel to boot without
clk_ignore_unused.
gcc_hmss_dvm_bus_clk is marked always-on downstream, but not referenced,
and gcc_lpass_at_clk isn't mentioned. So let's remove them until they
are needed by some client.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The current list of defined resets is incomplete compared to what the
hardware implements. Enumerate the remaining resets according to the
hardware documentation.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
We have this dummy factor clk in place to workaround a missing rpm clk
driver that can manage the XO clk state. Add it in to match what we do
on msm8996.
Cc: Jeffrey Hugo <jhugo@codeaurora.org>
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Tested-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The offsets for the defined BCR reset registers does not match the hardware
documentation. Update the values to match the hardware documentation.
Fixes: b5f5f525c5 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the global clock controller found on MSM8998
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Signed-off-by: Imran Khan <kimran@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[bjorn: Specify regs for alpha_plls, fix white spaces and add binding]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das