Commit Graph

23625 Commits

Author SHA1 Message Date
Thomas Hellstrom 4e0858a682 drm/vmwgfx: Properly flush cursor updates and page-flips
With the introduction of the new command buffer mechanism,
proper care wasn't taken to flush cursor image updates and
event-less screen-target page-flips.

Fix this by introducing explicit flush points.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-11-06 16:12:41 +01:00
Imre Deak 1b0e3a049e drm/i915/skl: disable display side power well support for now
The display power well support on this platform is in a somewhat broken
state atm, so disable it by default.

This in effect will get rid of incorrect assert WARNs about the CSR/DMC
firmware not being loaded during power well toggling. It also removes a
problem during driver loading where a register is accessed while its
backing power well is down, resulting in another WARN. Until we come up
with the root cause of the second problem and the proper fix for both
issues, keep all display side power wells on.

Also clarify a bit the option description.

Reported-by: Dave Airlie <airlied@redhat.com>
Reference: http://mid.gmane.org/CAPM=9tyjBQjSBTKa49cRr6SYkpNW7Pq-fUFznZZ8Y1snvvk7mA@mail.gmail.com
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446757451-2777-1-git-send-email-imre.deak@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-11-06 14:46:05 +02:00
Maarten Lankhorst b291681926 drm/i915: Extend DSL readout fix to BDW and SKL.
Those platforms have the same bug as haswell, and the same fix applies
to them.

The original HSW fix that this extends is

commit 41b578fb0e
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Tue Sep 22 12:15:54 2015 -0700

    drm/i915: workaround bad DSL readout v3

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org # v4.3
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91579
Link: http://patchwork.freedesktop.org/patch/msgid/1446535913-31970-3-git-send-email-maarten.lankhorst@linux.intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-11-06 10:40:16 +02:00
Mika Kuoppala 99106bc17e drm/i915: Do graphics device reset under forcewake
We have a timed release of a forcewake when using
I915_READ/WRITE macros. wait_for() macro will go to quite
long sleep if the first read doesn't satisfy the condition for
successful exit. With these two interacting, it is possible that
we lose the forcewake during the wait_for() and the subsequent read
will reaquire forcewake.

Further experiments with skl shows that when we lose forcewake,
we lose the reset request we submitted. So reset request register
is not power context saved.

Grab forcewakes for all engines before starting the reset/request
dance so that all requests stay valid for the duration of reset
requisition across all the engines.

v2: Add comment on power well sleeps. Wrap the reset handling
    under forcewake instead of just reset requests (Chris)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92774
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Tomi Sarvela <tomix.p.sarvela@intel.com> (v1, v2)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446721898-1450-1-git-send-email-mika.kuoppala@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-11-05 15:31:07 +02:00
Vivek Kasireddy 9807216f58 drm/i915: Skip fence installation for objects with rotated views (v4)
While pinning a fb object to the display plane, only install a fence
if the object is using a normal view. This corresponds with the
behavior found in i915_gem_object_do_pin() where the fencability
criteria is determined only for objects with normal views.

v2:
Look at the object's map_and_fenceable flag to determine whether to
install a fence or not (Chris).

v3:
Pin and unpin a fence only if the current view type is normal.

v4:
Extend the "view type is normal" check for pin_fence as well.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446170078-20792-1-git-send-email-vivek.kasireddy@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-11-05 14:00:29 +02:00
Lukas Wunner e02328f47b vga_switcheroo: Drop client power state VGA_SWITCHEROO_INIT
hda_intel.c:azx_probe() defers initialization of an audio controller
on the discrete GPU if the GPU is powered off. The power state of the
GPU is determined by calling vga_switcheroo_get_client_state().

vga_switcheroo_get_client_state() returns VGA_SWITCHEROO_INIT if
vga_switcheroo is not enabled, i.e. if no second GPU or no handler
has registered.

This can go wrong in the following scenario:
- Driver for the integrated GPU is not loaded.
- Driver for the discrete GPU registers with vga_switcheroo, uses driver
  power control to power down the GPU, handler cuts power to the GPU.
- Driver for the audio controller gets loaded after the GPU was powered
  down, calls vga_switcheroo_get_client_state() which returns
  VGA_SWITCHEROO_INIT instead of VGA_SWITCHEROO_OFF.
- Consequence: azx_probe() tries to initialize the audio controller even
  though the GPU is powered down.

The power state VGA_SWITCHEROO_INIT was introduced by c8e9cf7bb2
("vga_switcheroo: Add a helper function to get the client state").
It is not apparent what its benefit might be. The idea seems to
be to initialize the audio controller even if the power state is
VGA_SWITCHEROO_OFF (were vga_switcheroo enabled), but as shown
above this can fail.

Drop VGA_SWITCHEROO_INIT to solve this.

Acked-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-05 11:07:36 +10:00
Dave Airlie b26eae934e drm/panel: Changes for v4.4-rc1
Just two small cleanup patches to fix coccinelle warnings.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJWM6yPAAoJEN0jrNd/PrOhyBUQALPErCqaBBlS6nv+inM/dIqH
 UrhdBQcLF0BFPQmTEix82inkuqYEqB3u2TSDU6MH1IcJfJsOvSjj3/IOpx6uw1+P
 AygHPGluMQzunjC48zPWwfYzbrz5zqLK+Apq6afyEowxpnLUcO4yT14u/s2SVdkg
 qcNRU2pja/SsXJpz+JYBtCqyGPyuNU+AUBCqc3xFd2RuRQ99P5lZL0rdFTFihCoK
 If8MT3VehSE9QKYTkWuWe2c3y3CeucOmreGT+HITj+BE7rbULu73vyd4zdfhb5n6
 ObOER1L8YyyM9YfmWUm1swrcEUlG+mSq+ISm76mCwOVvftK0UKQV090WEgpNCRbH
 I9D1+pn1vjEK2FXyErOH0AifNAILdoDj3boXLLtyITnjc4K4gKuMeDUpHwUarg/a
 Ys51eHrO2mS4EWRxe8QwuP7hj2XFP6sFg3uwWNWMb2WYNoOGfPtxBfobhqU6jBMt
 NkNWqSBv/dOvj/5Bddz+3dH6Ea7LDw1oZ3GbBX8K1x1EQTvEPwTjseL3PSAbRbMO
 wmRQq/cknkQ9mSP0FEupUw73wc81C6C0iyxJXVtXfJUDkUfMPFJLo3L1Sjqsl4Ey
 DVqRpGFUt6hspw8f+DzeittVrXsq65XRKDTg3VlnEQVq/tBPErzXPwVNLhi9fLkY
 WQzb+vHIEic4zYY8yIjB
 =Q9bM
 -----END PGP SIGNATURE-----

Merge tag 'drm/panel/for-4.4-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/panel: Changes for v4.4-rc1

Just two small cleanup patches to fix coccinelle warnings.

* tag 'drm/panel/for-4.4-rc1' of git://anongit.freedesktop.org/tegra/linux:
  drm/bridge: ptn3460: Fix coccinelle warnings
  drm/bridge: ps8622: Fix coccinelle warnings
2015-11-05 11:07:13 +10:00
Dave Airlie 596a1d32bb drm/tegra: Changes for v4.4-rc1
Just a couple of minor fixes and cleanups for this cycle.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJWM6wLAAoJEN0jrNd/PrOh/HwP/23WEi/j4lBC8NMIOuxg9Eg5
 xfEN7hD3VLS3a/wzqCsM5UK9d8hSftCSKrYggKFL1NWsb3XIIyDHTc40dHl3MFMA
 r8WVk01XJhdpmSxhc0To1/a0HaKWfKlti2tZNTTYRa2w3pWMLSL/TVKmtAnebv9Z
 s15ISWzyjsV6hIMwl3AdvawLDy+u/j3kvwXw/XnSJYRvjDvsFQb0msIu7lGEIWfO
 /kabMKJAWUt/cdllWUbPbQdDZv2cY4m3MnSv3NLjOeyHqoZbnHvnx1zNMCYs/3+f
 tAzIgpPaMRVNA2vvXINqs7GA3oqks9JmqPysBfUoXD3uiewCzSHXV5fC39kwdhSh
 BntCBtL8PTbmVbX7dsgFEFHRx99Lvs37Jrk+4TTzO50L8nTtkXg8UsA/dpL/Ww5B
 jlNe/ZAXCOvlEpnmLjmH7Y2N+kbaV7yQmYv/7YKDb1hkQ3mEnv2kwbM9WdN9emyG
 pHdXWNGeb72Q8+fBAF1h47M40Zeebkfa6issx8uesTJj1smBwIqxIr3r8f3yShKt
 YbMre/K5C+X3xbX9uV79A2k9QqCgWhGkdxSmpGfivOZSzfVNZ3e81fgIeF7f3bbs
 uMLs2dpo46XSAOa+fl7GEKIt72824TiQSve+HpqqUv+qt2F5QcBldlwbqv0eJdF+
 VmfERYXWM8sgLSLru7L7
 =c0/4
 -----END PGP SIGNATURE-----

Merge tag 'drm/tegra/for-4.4-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v4.4-rc1

Just a couple of minor fixes and cleanups for this cycle.

* tag 'drm/tegra/for-4.4-rc1' of git://anongit.freedesktop.org/tegra/linux:
  drm/tegra: dc: Request/free syncpoint at init/exit
  drm/tegra: fb: Remove gratuituous blank line
  gpu: host1x: Fix MLOCK's debug info
2015-11-05 11:07:03 +10:00
Dave Airlie cb0fb27121 imx-drm fixes and color format updates
- Some correctness fixes found by coccinelle
 - Add drivers/gpu/ipu-v3 directory to MAINTAINERS
 - Add support for more color formats
 - Fix a regression, making displays larger than FullHD work again
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWM5loAAoJEFDCiBxwnmDrLwkQAOd2iOsgGemyffmh8shGwGq4
 pVgw/2Z9FzdlLXe21R9B8rYOsvq/QR74m49blNGSwlNO6c2L3+65BBkyc2VQoI6t
 c3GX0w2mnjqfHOZYiBT1Ca84FT1DBXjOprhljVbCBBZOr0xK4jRY3YBtlk30r8Yv
 RlithxYNWjoCBidf4w7FyCKM7tIN7bNXXGtyysAMzNuXU7Mq3dfhF8/qYucYFmYP
 XHOxFFX/q4EYchcQBCQi56kxEgEHtaFc+pwzM7mCwN5OVETcVeHw0EoTm56AjQrL
 zHwBXvP4ryKpuNFCUqsMdy9KZw+4inHycAjfEKwD2s72llycx+W+Kbg/00Ve8rWn
 6/Iv4Q0SuSSuRn4fWfioWSdQqHBZig3Y0AWCQ8BVCdTL2K2KIyxcT45vamo/zQhw
 uxRVxQzEUle4ZJJ4DOt5h4ZHF70eQNM9TDGYYSKUqtfQcbZ6pr6mz36J9PgyQuh7
 lTOfC5OZstTmS1iK+dqb5zbxhC76ff+v1lS8oTyJPK207f0hwt5OXTki9i7TueUH
 DXbPmrotajFWoNOkgFPcBBQaI6P5+29lzFqXE2z43Qk6UoYmR4T+UbpD2nNKaj+I
 qsIvgn4Zkg2RkxXehVQxRqynxx7XzfXVBXmtpbDfm50PoWsQMQa7fUiqWTyAp493
 zQybk9I0eNexJNFIzyie
 =EqNE
 -----END PGP SIGNATURE-----

Merge tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux into drm-next

imx-drm fixes and color format updates

- Some correctness fixes found by coccinelle
- Add drivers/gpu/ipu-v3 directory to MAINTAINERS
- Add support for more color formats
- Fix a regression, making displays larger than FullHD work again

* tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux:
  drm/imx: hdmi: fix HDMI setup to allow modes larger than FullHD
  gpu: ipu-v3: fix div_ratio type
  gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors.
  drm/imx: enable ARGB4444 16-bit color format
  gpu: ipu-v3: add support for ARGB4444 16-bit color format
  drm/imx: ipuv3-plane: enable support for RGBX8888 and RGBA8888 pixel formats
  gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formats
  drm/imx: enable 15-bit RGB with 1-bit alpha formats
  gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formats
  MAINTAINERS: Add IPUv3 core driver to the i.MX DRM driver section
  gpu: ipu-v3: ipu-csi: bool test doesn't need a comparison to false
2015-11-05 11:06:56 +10:00
Dave Airlie 793423ffcb Merge branch 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-next
- Updated register headers for GFX 8.1 for Stoney
- Add some new CZ revisions
- minor pageflip optimizations
- Fencing clean up
- Warning fix
- More fence cleanup
- oops fix
- Fiji fixes

* 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux: (29 commits)
  drm/amdgpu: group together common fence implementation
  drm/amdgpu: remove AMDGPU_FENCE_OWNER_MOVE
  drm/amdgpu: remove now unused fence functions
  drm/amdgpu: fix fence fallback check
  drm/amdgpu: fix stoping the scheduler timeout
  drm/amdgpu: cleanup on error in amdgpu_cs_ioctl()
  drm/amdgpu: update Fiji's Golden setting
  drm/amdgpu: update Fiji's rev id
  drm/amdgpu: extract common code in vi_common_early_init
  drm/amd/scheduler: don't oops on failure to load
  drm/amdgpu: don't oops on failure to load (v2)
  drm/amdgpu: don't VT switch on suspend
  drm/amdgpu: Make amdgpu_mn functions inline
  drm/amdgpu: remove amdgpu_fence_ref/unref
  drm/amdgpu: use common fence for sync
  drm/amdgpu: use the new fence_is_later
  drm/amdgpu: use common fences for VMID management v2
  drm/amdgpu: move ring_from_fence to common code
  drm/amdgpu: switch to common fence_wait_any_timeout v2
  drm/amdgpu: remove unneeded fence functions
  ...
2015-11-05 10:57:25 +10:00
Christian König a95e264254 drm/amdgpu: group together common fence implementation
And also add some missing function documentation. No functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-04 12:29:23 -05:00
Christian König 7a91d6cb3c drm/amdgpu: remove AMDGPU_FENCE_OWNER_MOVE
Moves are exclusive operations anyway, just use the undefined owner for those.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-04 12:29:23 -05:00
Christian König a67bcd34f6 drm/amdgpu: remove now unused fence functions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-04 12:29:22 -05:00
Christian König 24372447e5 drm/amdgpu: fix fence fallback check
Interrupts are notorious unreliable, enable the fallback at
a couple of more places.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-04 12:29:22 -05:00
Christian König 424839a6a9 drm/amdgpu: fix stoping the scheduler timeout
cancel_delayed_work_sync is forbidden in interrupt context.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-04 12:29:21 -05:00
Dan Carpenter 4cfdcd9cec drm/amdgpu: cleanup on error in amdgpu_cs_ioctl()
We recently changed the locking in this function and now there is a
missing unlock on error.  Also there are some other resources that we
should probably release as well...

Fixes: f48b2659f5 ('drm/amdgpu: fix the broken vm->mutex V2')
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
2015-11-04 12:29:21 -05:00
Mark Brown 4c84518523 Merge remote-tracking branches 'spi/topic/omap-100k', 'spi/topic/omap-uwire', 'spi/topic/owner', 'spi/topic/pxa' and 'spi/topic/pxa2xx' into spi-next 2015-11-04 11:02:12 +00:00
Daniel Stone bf248ca1f5 drm/i915: Fix locking around GuC firmware load
The GuC firmware load requires struct_mutex to create a GEM object,
but this collides badly with request_firmware. Move struct_mutex
locking down into the loader itself, so we don't hold it across the
entire load process, including request_firmware.

[   20.451400] ======================================================
[   20.451420] [ INFO: possible circular locking dependency detected ]
[   20.451441] 4.3.0-rc5+ #1 Tainted: G        W
[   20.451457] -------------------------------------------------------
[   20.451477] plymouthd/371 is trying to acquire lock:
[   20.451494]  (&dev->struct_mutex){+.+.+.}, at: [<ffffffffa0093c62>]
drm_gem_mmap+0x112/0x290 [drm]
[   20.451538]
               but task is already holding lock:
[   20.451557]  (&mm->mmap_sem){++++++}, at: [<ffffffff811fd9ac>]
vm_mmap_pgoff+0x8c/0xf0
[   20.451591]
               which lock already depends on the new lock.

[   20.451617]
               the existing dependency chain (in reverse order) is:
[   20.451640]
               -> #3 (&mm->mmap_sem){++++++}:
[   20.451661]        [<ffffffff8110644e>] lock_acquire+0xce/0x1c0
[   20.451683]        [<ffffffff8120ec9a>] __might_fault+0x7a/0xa0
[   20.451705]        [<ffffffff8127e34e>] filldir+0x9e/0x130
[   20.451726]        [<ffffffff81295b86>] dcache_readdir+0x186/0x230
[   20.451748]        [<ffffffff8127e117>] iterate_dir+0x97/0x130
[   20.451769]        [<ffffffff8127e66a>] SyS_getdents+0x9a/0x130
[   20.451790]        [<ffffffff8184f2f2>] entry_SYSCALL_64_fastpath+0x12/0x76
[   20.451829]
               -> #2 (&sb->s_type->i_mutex_key#2){+.+.+.}:
[   20.451852]        [<ffffffff8110644e>] lock_acquire+0xce/0x1c0
[   20.451872]        [<ffffffff8184b516>] mutex_lock_nested+0x86/0x400
[   20.451893]        [<ffffffff81277790>] walk_component+0x1d0/0x2a0
[   20.451914]        [<ffffffff812779f0>] link_path_walk+0x190/0x5a0
[   20.451935]        [<ffffffff8127803b>] path_openat+0xab/0x1260
[   20.451955]        [<ffffffff8127a651>] do_filp_open+0x91/0x100
[   20.451975]        [<ffffffff81267e67>] file_open_name+0xf7/0x150
[   20.451995]        [<ffffffff81267ef3>] filp_open+0x33/0x60
[   20.452014]        [<ffffffff8157e1e7>] _request_firmware+0x277/0x880
[   20.452038]        [<ffffffff8157e9e4>] request_firmware_work_func+0x34/0x80
[   20.452060]        [<ffffffff810c7020>] process_one_work+0x230/0x680
[   20.452082]        [<ffffffff810c74be>] worker_thread+0x4e/0x450
[   20.452102]        [<ffffffff810ce511>] kthread+0x101/0x120
[   20.452121]        [<ffffffff8184f66f>] ret_from_fork+0x3f/0x70
[   20.452140]
               -> #1 (umhelper_sem){++++.+}:
[   20.452159]        [<ffffffff8110644e>] lock_acquire+0xce/0x1c0
[   20.452178]        [<ffffffff8184c5c1>] down_read+0x51/0xa0
[   20.452197]        [<ffffffff810c203b>]
usermodehelper_read_trylock+0x5b/0x130
[   20.452221]        [<ffffffff8157e147>] _request_firmware+0x1d7/0x880
[   20.452242]        [<ffffffff8157e821>] request_firmware+0x31/0x50
[   20.452262]        [<ffffffffa01b54a4>]
intel_guc_ucode_init+0xf4/0x400 [i915]
[   20.452305]        [<ffffffffa0213913>] i915_driver_load+0xd63/0x16e0 [i915]
[   20.452343]        [<ffffffffa00987d9>] drm_dev_register+0xa9/0xc0 [drm]
[   20.452369]        [<ffffffffa009ae3d>] drm_get_pci_dev+0x8d/0x1e0 [drm]
[   20.452396]        [<ffffffffa01521e4>] i915_pci_probe+0x34/0x50 [i915]
[   20.452421]        [<ffffffff81464675>] local_pci_probe+0x45/0xa0
[   20.452443]        [<ffffffff81465a6d>] pci_device_probe+0xfd/0x140
[   20.452464]        [<ffffffff8156a2e4>] driver_probe_device+0x224/0x480
[   20.452486]        [<ffffffff8156a5c8>] __driver_attach+0x88/0x90
[   20.452505]        [<ffffffff81567cf3>] bus_for_each_dev+0x73/0xc0
[   20.452526]        [<ffffffff81569a7e>] driver_attach+0x1e/0x20
[   20.452546]        [<ffffffff815695ae>] bus_add_driver+0x1ee/0x280
[   20.452566]        [<ffffffff8156b100>] driver_register+0x60/0xe0
[   20.453197]        [<ffffffff81464050>] __pci_register_driver+0x60/0x70
[   20.453845]        [<ffffffffa009b070>] drm_pci_init+0xe0/0x110 [drm]
[   20.454497]        [<ffffffffa027f092>] 0xffffffffa027f092
[   20.455156]        [<ffffffff81002123>] do_one_initcall+0xb3/0x200
[   20.455796]        [<ffffffff811d8c01>] do_init_module+0x5f/0x1e7
[   20.456434]        [<ffffffff8114c4e6>] load_module+0x2126/0x27d0
[   20.457071]        [<ffffffff8114cdf9>] SyS_finit_module+0xb9/0xf0
[   20.457738]        [<ffffffff8184f2f2>] entry_SYSCALL_64_fastpath+0x12/0x76
[   20.458370]
               -> #0 (&dev->struct_mutex){+.+.+.}:
[   20.459773]        [<ffffffff8110584f>] __lock_acquire+0x191f/0x1ba0
[   20.460451]        [<ffffffff8110644e>] lock_acquire+0xce/0x1c0
[   20.461074]        [<ffffffffa0093c88>] drm_gem_mmap+0x138/0x290 [drm]
[   20.461693]        [<ffffffff8121a5ec>] mmap_region+0x3ec/0x670
[   20.462298]        [<ffffffff8121abb2>] do_mmap+0x342/0x420
[   20.462901]        [<ffffffff811fd9d2>] vm_mmap_pgoff+0xb2/0xf0
[   20.463532]        [<ffffffff81218f62>] SyS_mmap_pgoff+0x1f2/0x290
[   20.464118]        [<ffffffff8102187b>] SyS_mmap+0x1b/0x30
[   20.464702]        [<ffffffff8184f2f2>] entry_SYSCALL_64_fastpath+0x12/0x76
[   20.465289]
               other info that might help us debug this:

[   20.467179] Chain exists of:
                 &dev->struct_mutex --> &sb->s_type->i_mutex_key#2 -->
&mm->mmap_sem

[   20.468928]  Possible unsafe locking scenario:

[   20.470161]        CPU0                    CPU1
[   20.470745]        ----                    ----
[   20.471325]   lock(&mm->mmap_sem);
[   20.471902]                                lock(&sb->s_type->i_mutex_key#2);
[   20.472538]                                lock(&mm->mmap_sem);
[   20.473118]   lock(&dev->struct_mutex);
[   20.473704]
                *** DEADLOCK ***

Signed-off-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-04 13:23:15 +10:00
Flora Cui a7ca8ef930 drm/amdgpu: update Fiji's Golden setting
Change-Id: Ic3f3bfce4767cc05d04f6eb24e22a0f3e7ceacaa
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-11-03 11:48:18 -05:00
Flora Cui b6bc28ff29 drm/amdgpu: update Fiji's rev id
Change-Id: I0018e2b72feb771683c57960ba3ce942bec5d3ab
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-11-03 11:47:39 -05:00
Flora Cui a3d08fa56b drm/amdgpu: extract common code in vi_common_early_init
Change-Id: I9ed25353c559e27bc1b1d5b50f977b0ff03de87f
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-11-03 11:46:44 -05:00
Dave Airlie 32544d0215 drm/amd/scheduler: don't oops on failure to load
In two places amdgpu tries to tear down something it hasn't
initalised when failing. This is what happens when you
enable experimental support on topaz which then fails in
ring init.

This patch allows it to fail cleanly.

agd: Split out from from the original patch since the
scheduler is a driver independent.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2015-11-03 11:15:29 -05:00
Dave Airlie fe295b2715 drm/amdgpu: don't oops on failure to load (v2)
In two places amdgpu tries to tear down something it hasn't
initalised when failing. This is what happens when you
enable experimental support on topaz which then fails in
ring init.

This patch allows it to fail cleanly.

v2 (agd): split out scheduler change into a separate patch

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2015-11-03 11:15:19 -05:00
Alex Deucher df7989fe1e drm/amdgpu: don't VT switch on suspend
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-03 11:15:08 -05:00
Dave Airlie 1c431cb461 Merge branch 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- Vast improvements to gk20a instmem handling.
- Improved PGOB detection + GK107 support.
- Compatibility between old/new interfaces added, final missing piece to
finally enabling userspace to start using them.
- Kepler GDDR5 PLL stability improvements
- Support for non-GPIO (PWM) voltage controllers
- G8x/GT2xx memory clock improvements
- Misc other fixes

* 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (45 commits)
  drm/nouveau: bump patchlevel to indicate availability of abi16/nvif interop
  drm/nouveau/abi16: implement limited interoperability with usif/nvif
  drm/nouveau/abi16: introduce locked variant of nouveau_abi16_get()
  drm/nouveau/abi16: remove unused argument from nouveau_abi16_get()
  drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
  drm/nouveau/pci: enable c800 magic for Lenovo Y510P
  drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5
  drm/nouveau/clk/g84: Enable reclocking for GDDR3 G94-G200
  drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristic
  drm/nouveau/fb/ramnv50: Script changes for G94 and up
  drm/nouveau/fb/ramnv50: Deal with cards without timing entries
  drm/nouveau/fb/ramnv50: Voltage GPIOs
  drm/nouveau/fb/ramgt215: Restructure r111100 calculation for DDR2
  drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for it
  drm/nouveau/fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to generic
  drm/nouveau/bios/rammap: Identify DLLoff for >= GF100
  drm/nouveau/pci: Handle 5-bit and 8-bit tag field
  drm/nouveau/disp,pm: constify nvkm_object_func structures
  drm/nouveau/gr: add FERMI_COMPUTE_B class to GF110+
  drm/nouveau/gr: document mp error 0x10
  ...
2015-11-03 15:42:59 +10:00
Dave Airlie b459004796 Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
This pull request includes comprehensive cleanups to HDMI part and
   several fixups. In addition, this pull request includes also a defconfig
   patch which enables mixer driver as default. For this, I got already
   Acked-by from Krzysztof Kozlowski who is a Exynos SoC maintainer.

* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (34 commits)
  drm/exynos/gem: remove DMA-mapping hacks used for constructing page array
  ARM: exynos_defconfig: enable Exynos DRM Mixer driver
  drm/exynos: simplify Kconfig component names
  drm/exynos: re-arrange Kconfig entries
  drm/exynos: abstract out common dependency
  drm/exynos: separate Mixer and HDMI drivers
  drm/exynos/mixer: replace direct cross-driver call with drm mode validation
  drm/exynos: add atomic_check callback to exynos_crtc
  drm/exynos/decon5433: add support for DECON-TV
  drm/exynos/decon5433: remove duplicated initialization
  drm/exynos/decon5433: merge different flag fields
  drm/exynos/decon5433: add function to set particular register bits
  drm/exynos/decon5433: fix timing registers writes
  drm/exynos/decon5433: add PCLK clock
  drm/exynos: cleanup name of gem object for exynos_drm
  drm/exynos: fix to detach device of iommu
  drm/exynos: add cursor plane support
  drm/exynos: add global macro for the default primary plane
  drm/exynos: fix spelling errors
  drm: exynos: mixer: fix using usleep() in atomic context
  ...
2015-11-03 15:42:10 +10:00
Ben Skeggs 79ef5dca5e drm/nouveau: bump patchlevel to indicate availability of abi16/nvif interop
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs 2621a41647 drm/nouveau/abi16: implement limited interoperability with usif/nvif
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs 786a57ef2c drm/nouveau/abi16: introduce locked variant of nouveau_abi16_get()
USIF already takes the client mutex, but will need access to ABI16 data
in order to provide some limited interoperability.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs 09433f24e6 drm/nouveau/abi16: remove unused argument from nouveau_abi16_get()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin b41c48571d drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin a2736b07df drm/nouveau/pci: enable c800 magic for Lenovo Y510P
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Karol Herbst 78eaf335e4 drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5
This patch uses an approach closer to the nvidia driver to configure
both PLLs for high gddr5 memory clocks (usually above 2400MHz)

Previously nouveau used the one PLL as it was used for the lower clocks
and just adjusted the second PLL to get as close as possible to the
requested clock.  This means for my card, that I got a 4050 MHz clock
although 4008 MHz was requested.

Now the driver iterates over a list of PLL configuration also used by
the nvidia driver and then adjust the second PLL to get near the
requested clock.  Also it hold to some restriction I found while
analyzing the PLL configurations

This won't fix all gddr5 high clock issues itself, but it should be
fine on hybrid gpu systems as found on many laptops these days.  Also
switching while normal desktop usage should be a lot more stable than
before.

v2: move the pll code into ramgk104

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet 0d42743dfa drm/nouveau/clk/g84: Enable reclocking for GDDR3 G94-G200
Your milage may vary, as it's only been tested on a single G94 and one G96.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet 271c27665c drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristic
Avoids waiting for VBLANKS that never arrive on headless or otherwise
unconventional set-ups. Strategy taken from MEMX.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet 4d9faafa0f drm/nouveau/fb/ramnv50: Script changes for G94 and up
10053c is not even read on some cards, and I have no idea exactly what the
criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables
all features that are never used. The practical effect should be the same
as this implementation though.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet 797eb6ed8f drm/nouveau/fb/ramnv50: Deal with cards without timing entries
Like Pierre's G94. We might want to structure Kepler similarly in a follow-up.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet 1cf688dd1b drm/nouveau/fb/ramnv50: Voltage GPIOs
Does not seem to be necessary for NVA0, hence untested by me.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet 0b0b78cd7d drm/nouveau/fb/ramgt215: Restructure r111100 calculation for DDR2
Seems to be mostly equal to DDR3 on < GT218, should improve stability for
DDR2 reclocks.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet ef6e8f4c7f drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for it
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet e0a37f85fc drm/nouveau/fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to generic
In preparation of changing FBVDDQ, as observed on at least one GDDR3 card.
While at it, adhere to func.log[1] properly for consistency.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet b4f2bf33bb drm/nouveau/bios/rammap: Identify DLLoff for >= GF100
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Pierre Moreau 5d5b43f59b drm/nouveau/pci: Handle 5-bit and 8-bit tag field
If the hardware supports extended tag field (8-bit ones), then enable it.

This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).

In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.

Fixes: fdo#86537

v2: Restrict changes to chipsets >= 0x84
v3:
  * Add nvkm_pci_mask to pci.h
  * Mask bit 8 before setting it
v4:
  * Rename `add` argument of nvkm_pci_mask to `value`
  * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
    checks
v5:
  * Rebase code on latest PCI structure
  * Restore PCIe check
  * Fix namings in nvkm_pci_mask
  * Rephrase part of the commit message

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Julia Lawall 354a224966 drm/nouveau/disp,pm: constify nvkm_object_func structures
These nvkm_object_func structures are never modified.  All other
nvkm_object_func structures are declared as const.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin 2e69a5cd25 drm/nouveau/gr: add FERMI_COMPUTE_B class to GF110+
GF110+ supports both the A and B compute classes, make sure to accept
both.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin 3988f645f0 drm/nouveau/gr: document mp error 0x10
NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE,
which apparently happens when trying to use an atomic operation on
local or shared memory (instead of global memory).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Sudip Mukherjee bad4274a69 drm/nouveau: fix memory leak
If pm_runtime_get_sync() we were going to "out" but we missed freeing
vma.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Sudip Mukherjee 4458c5639b drm/nouveau: remove unused function
coverity.com reported that memset was using a buffer of size 0, on
checking the code it turned out that the function was not being used. So
remove it.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs 3c9aca3181 drm/nouveau/pmu/gk107: enable PGOB codepaths
Reported to be needed as per fdo#70354 comment #61.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs 560f989fe4 drm/nouveau/pmu/gk104: check fuse to determine presence of PGOB
Not 100% confirmed, but seems to match from the few boards I've looked
at so far.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs 779d16aacc drm/nouveau/pci: prepare for chipset-specific initialisation tasks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs c4266a9c7b drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default
Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs b31505c472 drm/nouveau/pci/g94: split implementation from nv40
An upcoming patch will implement functionality that we don't use on any
NV40 chipset.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs 3e55b53bc7 drm/nouveau/pci/g84: split implementation from nv50
An upcoming patch will implement functionality that we don't use on the
original NV50.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Samuel Pitoiset b6afa2650c drm/nouveau/ibus/gf100: increase wait timeout to avoid read faults
Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.

This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres 24580d1c31 drm/nouveau/gm204/6: add voltage control using the new gk104 volt class
I got confirmation that we can read and change the voltage with the same code.
The divider is also computed correctly on the gm204 we got our hands on.

Thanks to Yoshimo on IRC for executing the tests on his gm204!

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres dc47700f7d drm/nouveau/gm107: add voltage control using the new gk104 volt class
Let's ignore the other desktop Maxwells until I get my hands on one and confirm
that we still can change the voltage.

Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03 15:02:18 +10:00
Martin Peres 1531dbbb56 drm/nouveau/volt/gk104: add support for pwm and gpio modes
Most Keplers actually use the GPIO-based voltage management instead of the new
PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles
the case where no GPIOs exist.

All the Maxwells seem to use the PWM method though.

v2:
 - Do not forget to commit the PWM configuration change!

Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03 15:02:18 +10:00
Martin Peres 4c58a05b4a drm/nouveau/volt: add support for non-vid-based voltage controllers
This patch is not ideal but it definitely beats a rewrite of the current
interface and is very self-contained.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres 7bddeba966 drm/nouveau/bios/volt: add support for pwm-based volt management
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot b31cf78b93 drm/nouveau/ttm: set the DMA mask for platform devices
So far the DMA mask was not set for platform devices, which limited them
to a 32-bit physical space. Allow dma_set_mask() to be called for
non-PCI devices, and also take the IOMMU bit into account since it could
restrict the physically addressable space.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot 524883bb48 drm/nouveau/ttm: convert to DMA API
The pci_dma_* functions are now superseeded in the kernel by the DMA
API. Make the conversion to this more generic API.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot 68b566534c drm/nouveau/instmem/gk20a: make use of the IOMMU bit
Use the IOMMU bit specified in platform data instead of hardcoding it to
the bit used by current Tegra GPUs.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot e396ecd178 drm/nouveau/platform: allow to specify the IOMMU bit
Current Tegra code taking advantage of the IOMMU assumes a hardcoded
value for the IOMMU bit. Make it a platform property instead for
flexibility.

v2 (Ben Skeggs): remove nvkm dependence on drm structures

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot 69c4938249 drm/nouveau/instmem/gk20a: use direct CPU access
The Great Nouveau Refactoring Take II brought us a lot of goodness,
including acquire/release methods that are called before and after an
instobj is modified. These functions can be used as synchronization
points to manage CPU/GPU coherency if we modify an instobj using the
CPU.

This patch replaces the legacy and slow PRAMIN access for gk20a instmem
with CPU mappings and writes. A LRU list is used to unmap unused
mappings after a certain threshold (currently 1MB) of mapped instobjs is
reached. This allows mappings to be reused most of the time.

Accessing instobjs using the CPU requires to maintain the GPU L2 cache,
which we do in the acquire/release functions. This triggers a lot of L2
flushes/invalidates, but most of them are performed on an empty cache
(and thus return immediately), and overall context setup performance
greatly benefits from this (from 250ms to 160ms on Jetson TK1 for a
simple libdrm program).

Making L2 management more explicit should allow us to grab some more
performance in the future.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs fcf3f91c34 drm/nouveau: remove unnecessary usage of object handles
No longer required in a lot of cases, as objects are identified over NVIF
via an alternate mechanism since the rework.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot a0a49bac2f drm/nouveau/ltc/gf100: add flush/invalidate functions
Allow clients to manually flush and invalidate L2. This will be useful
for Tegra systems for which we want to write instmem using the CPU.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot 38a8fc78d0 drm/nouveau/ltc: add hooks for invalidate and flush
These are useful for systems without a coherent CPU/GPU bus. For such
systems we may need to maintain the L2 ourselves.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot 542f60dc84 drm/nouveau/timer: re-introduce nvkm_wait_xsec macros
Reintroduce macros allowing us to test a register against a certain
mask, since this is the most common usage pattern for the more generic
nvkm_xsec macros and makes the code more concise and readable.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot 579b7c5821 drm/nouveau/pmu: do not assume a PMU is present
Some devices may not have a PMU. Avoid a NULL pointer dereference in
such cases by checking whether the pointer given to nvkm_pmu_pgob() is
valid.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin 04b8a4bd8e drm/nouveau/gem: return only valid domain when there's only one
On nv50+, we restrict the valid domains to just the one where the buffer
was originally created. However after the buffer is evicted to system
memory, we might move it back to a different domain that was not
originally valid. When sharing the buffer and retrieving its GEM_INFO
data, we still want the domain that will be valid for this buffer in a
pushbuf, not the one where it currently happens to be.

This resolves fdo#92504 and several others. These are due to suspend
evicting all buffers, making it more likely that they temporarily end up
in the wrong place.

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92504
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 14:56:06 +10:00
Marek Szyprowski df547bf773 drm/exynos/gem: remove DMA-mapping hacks used for constructing page array
Exynos GEM objects contains an array of pointers to the pages, which the
allocated buffer consists of. Till now the code used some hacks (like
relying on DMA-mapping internal structures or using ARM-specific
dma_to_pfn helper) to build this array. This patch fixes this by adding
proper call to dma_get_sgtable_attrs() and using the acquired scatter-list
to construct needed array. This approach is more portable (work also for
ARM64) and finally fixes the layering violation that was present in this
code.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:39 +09:00
Andrzej Hajda 5a3c35b377 drm/exynos: simplify Kconfig component names
Many Exynos DRM sub-options mentions Exynos DRM in their titles.
It is redundant and can be safely shortened. The patch additionally
makes some entries more descriptive.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:38 +09:00
Andrzej Hajda ea9776465d drm/exynos: re-arrange Kconfig entries
Exynos DRM driver have quite big number of components and options.
The patch re-arranges them into three logical groups:
- CRTCs,
- Encoders and Bridges,
- Sub-drivers.
It should make driver options more clear.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:38 +09:00
Andrzej Hajda dba6c5280d drm/exynos: abstract out common dependency
All options depends on DRM_EXYNOS so it can be moved to enclosing if clause.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:38 +09:00
Andrzej Hajda 3cb02b4a9e drm/exynos: separate Mixer and HDMI drivers
Latest Exynos SoCs does not have Mixer IP, but they still have HDMI IP.
Their drivers should be configurable separately.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:38 +09:00
Andrzej Hajda 3ae24362e0 drm/exynos/mixer: replace direct cross-driver call with drm mode validation
HDMI driver called directly function from MIXER driver to invalidate modes
not supported by MIXER. The patch replaces the hack with proper .atomic_check
callback.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:38 +09:00
Andrzej Hajda 5625b3418a drm/exynos: add atomic_check callback to exynos_crtc
Some CRTCs needs mode validation, this patch adds neccessary
callback to Exynos DRM framework. It is called from DRM core
via atomic_check helper for drm_crtc.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:37 +09:00
Andrzej Hajda b8182832c5 drm/exynos/decon5433: add support for DECON-TV
DECON-TV IP is responsible for generating video stream which is transferred
to HDMI IP. It is almost fully compatible with DECON IP.

The patch is based on initial work of Hyungwon Hwang.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:37 +09:00
Andrzej Hajda 5d929ba50a drm/exynos/decon5433: remove duplicated initialization
Field .commit is already initialized few lines above.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:37 +09:00
Andrzej Hajda 7b6bb6ed01 drm/exynos/decon5433: merge different flag fields
Driver uses four different fields for internal flags. They can be merged
into one.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:37 +09:00
Andrzej Hajda b219207385 drm/exynos/decon5433: add function to set particular register bits
The driver often sets only particular bits of configuration registers.
Using separate function to such action simplifies the code.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:37 +09:00
Andrzej Hajda 85de275ad9 drm/exynos/decon5433: fix timing registers writes
All timing registers should contain values decreased by one.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:36 +09:00
Andrzej Hajda 4f54f21cd6 drm/exynos/decon5433: add PCLK clock
PCLK clock is used by DECON IP. The patch also replaces magic number with
number of clocks in array definition.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03 11:46:36 +09:00
Harry Wentland 1d1106b0f6 drm/amdgpu: Make amdgpu_mn functions inline
Unused amdgpu_mn functions threw warnings for every file that includes
amdgpu.h. It makes sense to inline this amdgpu_mn stubs to avoid the warning.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
2015-11-02 10:24:56 -05:00
Jani Nikula 9be64eee3a drm/i915: add quirk to enable backlight on Dell Chromebook 11 (2015)
Reported-by: Keith Webb <khwebb@gmail.com>
Suggested-by: Keith Webb <khwebb@gmail.com>
Cc: stable@vger.kernel.org
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=106671
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446209424-28801-1-git-send-email-jani.nikula@intel.com
2015-11-02 10:24:04 +02:00
Thomas Hellstrom b76ff5ea1c drm/vmwgfx: Replace iowrite/ioread with volatile memory accesses
Now that we use memremap instead of ioremap, Use WRITE_ONCE / READ_ONCE
instead of iowrite / ioread.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2015-11-02 00:16:05 -08:00
Thomas Hellstrom 53c1e53571 drm/vmwgfx: Turn off support for multisample count != 0 v2
Do this until we know how much MOB memory to allocate for these surfaces.
v2: Mask also non-DX multisample.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-11-02 00:16:05 -08:00
Dan Williams 5ad9dceee9 drm/vmwgfx: switch from ioremap_cache to memremap
Per commit 2e586a7e01 "drm/vmwgfx: Map the fifo as cached" the driver
expects the fifo registers to be cacheable.  In preparation for
deprecating ioremap_cache() convert its usage in vmwgfx to memremap().

Cc: David Airlie <airlied@linux.ie>
Cc: Thomas Hellstrom <thellstrom@vmware.com>
Cc: Sinclair Yeh <syeh@vmware.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
2015-11-02 00:16:05 -08:00
Maarten Lankhorst b10f1b2017 drm/i915/skl: Prevent unclaimed register writes on skylake.
I'm getting unclaimed register writes when checking the WM registers
after the crtc is disabled. So I would imagine those are guarded by
the crtc power well. Fix this by not reading out wm state when the
power well is off.

Cc: stable@vger.kernel.org # v4.3
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-11-02 09:55:34 +02:00
Maneet Singh 8731b269f0 drm: Correct arguments to list_tail_add in create blob ioctl
Arguments passed to list_add_tail were reversed resulting in deletion
of old blob property everytime the new one is added.

Fixes

commit e2f5d2ea47
Author: Daniel Stone <daniels@collabora.com>
Date:   Fri May 22 13:34:51 2015 +0100

    drm/mode: Add user blob-creation ioctl

Signed-off-by: Maneet Singh <mmaneetsingh@nvidia.com>
[seanpaul tweaked commit subject a little]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Cc: stable@kernel.org # v4.2
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
2015-10-31 10:22:26 +10:00
Dan Carpenter 9ac0934bbe drm: crtc: integer overflow in drm_property_create_blob()
The size here comes from the user via the ioctl, it is a number between
1-u32max so the addition here could overflow on 32 bit systems.

Fixes: f453ba0460 ('DRM: add mode setting support')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: stable@kernel.org # v4.2
Signed-off-by: Dave Airlie <airlied@gmail.com>
2015-10-31 10:00:05 +10:00
Thierry Reding 2bcdcbfae2 drm/tegra: dc: Request/free syncpoint at init/exit
syncpoints are resources provided by host1x and their lifetime is tied
to the host1x device. They are not properly reference counted either, so
removing the host1x device before any of its clients causes a use-after-
free error. Adding proper reference counting would be a major enterprise
so work around it for now by requesting and freeing the syncpoint at
init and exit time, respectively. The host1x device is guaranteed to be
around at this point.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-30 18:40:52 +01:00
kbuild test robot f1811a8a64 drm/bridge: ptn3460: Fix coccinelle warnings
The platform_no_drv_owner.cocci coccinelle script generates the
following warning:

	drivers/gpu/drm/bridge/nxp-ptn3460.c:403:3-8: No need to set .owner here. The core will do it.

Remove .owner field if calls are used which set it automatically. Patch
generated by scripts/coccinelle/api/platform_no_drv_owner.cocci.

Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-30 18:40:36 +01:00
kbuild test robot ab0162b8fd drm/bridge: ps8622: Fix coccinelle warnings
The platform_no_drv_owner.cocci coccinelle script generates the
following warning:

	drivers/gpu/drm/bridge/parade-ps8622.c:671:3-8: No need to set .owner here. The core will do it.

Remove .owner field if calls are used which set it automatically. Patch
generated by scripts/coccinelle/api/platform_no_drv_owner.cocci.

Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-30 18:38:32 +01:00
Lucas Stach a5f4185c4b drm/imx: hdmi: fix HDMI setup to allow modes larger than FullHD
This worked before the dw-hdmi bridge code was changed to validate
the setup data more strictly. Add back support for modes with a
pixel clock up to 216MHz. Even higher clocks should work, but we
are missing the required setup data for now.

Also change the mode validate callbacks to disallow modes with
higher pixelclocks, so we don't end up failing the modeset later
on.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:54 +01:00
Andrzej Hajda 9b6d0d33c8 gpu: ipu-v3: fix div_ratio type
The variable can be negative.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Philippe De Muyter 3e8b2246c3 gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors.
Enable the MEDIA_BUS_FMT_Y8_1X8 format.

Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Lucas Stach cb166a3025 drm/imx: enable ARGB4444 16-bit color format
This patch allows to use the ARGB4444 color format on planes.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Lucas Stach 7d2e8a204a gpu: ipu-v3: add support for ARGB4444 16-bit color format
This patch adds support for the ARGB4444 color format.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00