Add DT OPP table for OMAP443x family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp4xxx_data.c
Since the omap4460 OPP tables would be different from OMAP443x,
introduce an new omap443x.dtsi for 443x specific entries and use
existing omap4.dtsi as the common dtsi file for all OMAP4 platforms.
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp4xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Define VDD1 regulator in twl4030 DT and mark it as the supply for the
various OMAP34xx/35xx/36xx/37xx platforms (all use TWL4030 variants with
VDD1 supplying the CPU).
NOTE: This currently will use I2C1 bus communication path to set the
voltage in device tree boot. In the legacy non device tree boot, we
continue to use twl-common.c which bypasses I2C1 bus communication path
and uses I2C4 bus path using OMAP voltage libraries. We should
eventually be able to use I2C4 path once we have voltage regulator for
OMAP which is capable of using the voltage controller/voltage processor
IP blocks.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP36xx/37xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp3xxx_data.c
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp3xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP34xx/35xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp3xxx_data.c
Since the omap36xx OPP tables would be different from OMAP34xx/35xx,
introduce an new omap34xx.dtsi for 34xx/35xx specific entries and use
existing omap3.dtsi as the common dtsi file for all OMAP3 platforms.
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp3xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The binding documentation for the OMAP GPIO controller has the
"#interrupt-cells" property listed before "#interrupt-controller"
property but its description after.
This is confusing so we move "#interrupt-cells" after the
"interrupt-controller" property so is followed by its description.
While being there, change the properties order to be consistent with
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
and Documentation/devicetree/bindings/gpio/gpio.txt.
According with these docs, the order of the properties for a gpio-omap
device node should be:
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
OMAP hwmod layer does the reset of the IPs in early code so that
we have SOC in sane state. To do the soft-reset, it needs to ioremap()
the IP address space to be able to write to sysconfig registers.
But there are few hwmod which doesn't have sysconfig registers and hence
no need to ioremap() them in early init code.
Prevent calling the _init_mpu_rt_base() conditional based on sysc
availability.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Patch adds the code for extracting the module ocp address space
from device tree blob in case the hwmod address space look up fails.
The idea is to remove the address space data from hwmod and extract
it from DT blob.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add l3-noc node for OMAP4 and OMAP5 devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[jon-hunter@ti.com: Fix the problem caused by adding 32 to the interrupt
number for the L3 interrupts to account for per processor interrupts (PPI)
and software generated interrupts (SGI) which typically are mapped to the
first 32 interrupts in the ARM GIC. This is not necessary because the first
parameter of the ARM GIC interrupt property specifies the GIC interrupt
type (ie. SGI, PPI, etc). Hence, fix the interrupt number for the L3
interrupts by substracting 32]
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
OMAP L3 driver needs reg address space for its operation
and hence its a required property.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
To be able to run kernel in HYP mode, virtual timer
and GIC node information needs to be populated.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
GIC is not part of OCP space so move the gic DT node
out of ocp DT address space.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Specify both secure as well as nonsecure PPI IRQ for arch
timer. This fixes the following errors seen on DT OMAP5 boot..
[ 0.000000] arch_timer: No interrupt available, giving up
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
It has been decided to not duplicate banked modules dt nodes and that is
how the current arch timer dt extraction code is.
Update the OMAP5 DT file accordingly.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap.
Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB
memory.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the needed sections to enable audio support on
Devkit8000 when booted with DT blob.
Signed-off-by: Anil Kumar <anilk4.v@gmail.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
DevKit8000 is a beagle board clone from Timll, sold by
armkits.com. The DevKit8000 has RS232 serial port, LCD, DVI-D,
S-Video, Ethernet, SD/MMC, keyboard, camera, SPI, I2C, USB and
JTAG interface.
Add the basic DT support for devkit8000. It includes:
- twl4030 (PMIC)
- MMC1
- I2C1
- leds
Signed-off-by: Anil Kumar <anilk4.v@gmail.com>
Tested-by: Thomas Weber <thomas@tomweber.eu>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Adds basic device-tree support for OMAP3430 SDP board which has 256MB
of RAM, 128MB ONENAND flash, 256MB NAND flash and uses the TWL4030
power management IC.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The OMAP3 gpio bindings are currently missing the reg and interrupt
properties and so add these properties.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The OMAP gpio binding documention [1] states that the #interrupts-cells
property for gpio controllers should be 2. Currently, for OMAP3+ devices
the #interrupt-cells is set to 1. By setting this property to 2, it
allows clients to pass a 2nd parameter indicating the sensitivity (level
or edge) and polarity (high or low) of the interrupt. The OMAP gpio
controllers support these options and so update the #interrupt-cells
property for OMAP3+ devices to 2.
[1] Documentation/devicetree/bindings/gpio/gpio-omap.txt
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the device-tree node for GPMC on OMAP2, OMAP4 and OMAP5 devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add SDMA controller binding for OMAP2+ devices and populate DMA client
information for SPI and MMC peripheral on OMAP3+ devices. Please note
that OMAP24xx devices do not have SPI and MMC bindings available yet and
so DMA client information is not populated.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add PMU nodes for OMAP2, OMAP3 and OMAP4460 devices.
Please note that the node for OMAP4460 has been placed in a separate
header file for OMAP4460, because the node is not compatible with
OMAP4430. The node for OMAP4430 is not included because PMU is not
currently supported on OMAP4430 due to the absence of a cross-trigger
interface driver.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
If device-tree is present, then do not create the PMU device from within
the OMAP specific PMU code. This is required to allow device-tree to
create the PMU device from the PMU device-tree node.
PMU is not currently supported for OMAP4430 (due to a dependency on
having a cross-trigger interface driver) and so ensure that this
indicated on boot with or without device-tree.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add dwc3 omap glue data to the omap5 dt data file.
The information about the dt node added here is available @
Documentation/devicetree/bindings/usb/omap-usb.txt.
Also added dwc3 core dt data as a subnode to dwc3 omap glue
data in omap5 dt data file.
The information for the entered data node is available @
Documentation/devicetree/bindings/usb/dwc3.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap-usb3 and omap-usb2 data node in OMAP5 device tree file.
The information for the node added here is available @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add ocp2scp data node in omap5 device tree file.
The information for the node added here can be found @
Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in OMAP5 device tree file.
This will have the register address of registers to
power on the USB2 PHY and USB3 PHY.
The information for the node added here is available in
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add usb otg data node in omap4/omap3 device tree file. Also update
the node with board specific setting in omapx-<board>.dts file.
The dt data specifies among others the interface type (ULPI or UTMI),
mode which is mostly OTG, power that specifies the amount of power
this can supply when in host mode.
The information about usb otg node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap-usb2 data node in omap4 device tree file. Since omap-usb2
is connected to ocp2scp, omap-usb2 dt data is added as a child node
of ocp2scp. The information about this data node is availabe @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in omap4 device tree file. This will have the
register address of registers to power on the PHY and to write to
mailbox. The information about this data node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Currently the OMAP General-Purpose Memory Controller (GPMC) device
node maps 16 MB of address space for its hardware registers.
This is because the OMAP Technical Reference Manual says that the
GPMC module register address space size is 16 MB. But in practice
the maximum address offset used by a GPMC register is 0x02d0.
So, there is no need to map such a big address space for GPMC regs.
This change was suggested by Jon Hunter [1].
[1]: https://patchwork.kernel.org/patch/2057111/
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add device-tree support for the GPMC controller on the OMAP3.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap4 panda results in the following error
[ 0.444427] omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 0.445770] omap_i2c 48070000.i2c: bus 0 rev0.11 at 400 kHz
[ 0.473937] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 0.474670] omap_i2c 48072000.i2c: bus 1 rev0.11 at 400 kHz
[ 0.474822] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 0.476379] omap_i2c 48060000.i2c: bus 2 rev0.11 at 100 kHz
[ 0.477294] omap_i2c 48350000.i2c: did not get pins for i2c error: -19
[ 0.477996] omap_i2c 48350000.i2c: bus 3 rev0.11 at 400 kHz
[ 0.483398] Switching to clocksource 32k_counter
This happens because omap4 panda dts file is not adapted to use i2c through
pinctrl framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4460 panda with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Luciano Coelho <coelho@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 5430evm results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap5 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap5430 evm with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the needed sections to enable audio support on Overo.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 4430sdp results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap4 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4430 sdp with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Convert the on-board LED connected to the TWL4030 (LEDB) to use
pwm-leds.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Section to describe the backlight for the LCD panels.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Sections to describe the pwm-leds in the system.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
We have proper driver stack to handle the pmu_stat LED which is connected
PWMB of twl4030.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Enable support for the PWMs and LED as PWM drivers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Enable support for the PWMs and LEDs as PWM drivers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add a new address space/memory resource to d_can device tree node. D_CAN
RAM initialization is achieved through RAMINIT register which is part of
AM33XX control module address space. D_CAN RAM init or de-init should be
done by writing instance corresponding value to control module register.
Till we have a separate control module driver to write to control module,
d_can driver will handle the register writes to control module by itself.
So a new address space to represent this control module register is added
to d_can driver.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Nishanth Menon