Create /sys/firmware/opal directory. We wil use this
interface to fetch opal error logs, firmware update, etc.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Add a VMX optimised xor, used primarily for RAID5. On a POWER7 blade
this is a decent win:
32regs : 17932.800 MB/sec
altivec : 19724.800 MB/sec
The bigger gain is when the same test is run in SMT4 mode, as it
would if there was a lot of work going on:
8regs : 8377.600 MB/sec
altivec : 15801.600 MB/sec
I tested this against an array created without the patch, and also
verified it worked as expected on a little endian kernel.
[ Fix !CONFIG_ALTIVEC build -- BenH ]
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Correct reference to the location of the kexec_sequence() assembly helper.
There never was a kexec_stub.S in mainline.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The condition register (CR) is a 32 bit quantity so we should use
32 bit loads and stores.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Enable a few modules required to boot on a POWER multipath
box.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Run savedefconfig over the ppc64, ppc64e and pseries config
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Using -mcpu=power7 allows gcc to use a number of new instructions
including 64 bit byte reversed loads.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
commit f13c13a005 (powerpc: Stop using non-architected shared_proc
field in lppaca) fixed a potential issue with shared/dedicated
partition detection. The old method of detection relied on an
unarchitected field (shared_proc), and this patch switched
to using something architected (a non zero yield_count).
Unfortunately the assertion in the Linux header that yield_count
is only non zero on shared processor partitions is not true. It
turns out dedicated processor partitions can increment yield_count
and as such we falsely detect dedicated partitions as shared.
Fix the comment, and switch back to using the old method.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This patch addresses unaligned single precision floating point loads
and stores in the single-step code. The old implementation
improperly treated an 8 byte structure as an array of two 4 byte
words, which is a classic little endian bug.
Signed-off-by: Tom Musta <tmusta@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This patch modifies the unaligned access routines of the sstep.c
module so that it properly reverses the bytes of storage operands
in the little endian kernel kernel. This is implemented by
breaking an unaligned little endian access into a combination of
single byte accesses plus an overal byte reversal operation.
Signed-off-by: Tom Musta <tmusta@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This patch enables alignment handling for the load/store floating point
pair instructions (lfdp, lfdpx, stfdp, stfdpx). The handler routine
is properly coded and only needs to be enabled.
Signed-off-by: Tom Musta <tmusta@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The alignment handler is incorrect for unaligned string instructions
in little endian mode. These instructions access data as arrays of
bytes and thus are endian neutral. However, the routine also handles
the load/store multiple instructions, which are NOT endian neutral.
This patch toggles the byte swapping flag for the string instructions
in little endian builds. This effectively disables the byte swapping
logic.
Signed-off-by: Tom Musta <tmusta@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This issue was causing the QEMU emulated USB device to fail dring
PCI probe.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
PPC44x supports page sizes other than 4K however when 64K page sizes
are selected compilation fails. This is due to a change in the
definition of pgtable_t introduced by the following patch:
commit 5c1f6ee9a3
Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
powerpc: Reduce PTE table memory wastage
The above patch only implements the new layout for PPC64 so it doesn't
compile for PPC32 with a 64K page size. Ideally we should implement
the same layout for PPC32 however for the meantime this patch reverts
the definition of pgtable_t for PPC32.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
If you try and build the FA_DUMP code with CONFIG_KEXEC=n, you see
errors such as the following:
arch/powerpc/kernel/fadump.c
408:2: error: 'crashing_cpu' undeclared (first use in this function)
410:2: error: implicit declaration of function 'crash_save_vmcoreinfo'
513:22: error: storage size of 'prstatus' isn't known
520:2: error: implicit declaration of function 'elf_core_copy_kernel_regs'
521:36: error: 'KEXEC_CORE_NOTE_NAME' undeclared (first use in this function)
624:49: error: 'note_buf_t' undeclared (first use in this function)
872:2: error: implicit declaration of function 'paddr_vmcoreinfo_note'
874:18: error: 'vmcoreinfo_max_size' undeclared (first use in this function)
This is because although FA_DUMP doesn't use kexec as the actual reboot
mechanism, it does use parts of the kexec code to assemble/disassemble
the crash image.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This patch fixes typo in comments virtual to physical
address conversion.
Signed-off-by: Vaishnavi Bhat <vaishnavi@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Move the few declarations from arch/powerpc/kernel/setup.h
into arch/powerpc/include/asm/setup.h. This resolves a
sparse warning for arch/powerpc/mm/numa.c which defines
do_init_bootmem() but can't include the setup.h header
in the prior path.
Resolves:
arch/powerpc/mm/numa.c:998:13:
warning: symbol 'do_init_bootmem' was not declared.
Should it be static?
Signed-off-by: Robert C Jennings <rcj@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Simple fixes for sparse warnings in this file.
Resolves:
arch/powerpc/mm/numa.c:198:24:
warning: Using plain integer as NULL pointer
arch/powerpc/mm/numa.c:1157:5:
warning: symbol 'hot_add_node_scn_to_nid' was not declared.
Should it be static?
arch/powerpc/mm/numa.c:1238:28:
warning: Using plain integer as NULL pointer
arch/powerpc/mm/numa.c:1538:6:
warning: symbol 'topology_schedule_update' was not declared.
Should it be static?
Signed-off-by: Robert C Jennings <rcj@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Commit c55aef0e5b ("powerpc/boot: Change the load address for the
wrapper to fit the kernel") adjusts the wrapper address unnecessarily
for platforms that use arch/powerpc/boot/of.c, since the code there
allocates space for the kernel wherever it can find it and doesn't
necessarily load the kernel at address 0. Changing the link address
is actually harmful since it can cause the zImage to overlap with
Open Firmware and thus fail to boot.
To fix this, we set make_space to n for all of the platforms that
use of.o.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Caused by commit a4da0d50b2 ("powerpc: Implement
arch_get_random_long/int() for powernv") from the powerpc tree
interacting with commit b5b4bb3f6a ("of: only include prom.h on sparc")
from the dt-rh tree.
I added this merge fix patch (which will need to be sent to Linus when
these two trees get merged, or could be applied now to the powerpc tree):
[ Also add linux/smp.h to get cpu_to_chip_id -- BenH ]
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This removes the COMMON_CLKDEV kernel configuration
parameter defined in arch/c6x/Kconfig, but used nowhere
in the makefiles and source code.
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
On TC2, the cpu clocks are controlled by the external M3 microcontroller
and SPC provides the interface between the CPU and the power controller.
The generic cpufreq drivers use the clock APIs to get the cpu clocks.
This patch add virtual spc clocks for all the cpus to control the cpu
operating frequency via the clock framework.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Pawel Moll <Pawel.Moll@arm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
SPC(Serial Power Controller) on TC2 also controls the CPU performance
operating points which is essential to provide CPU DVFS. The M3
microcontroller provides two sets of eight performance values, one set
for each cluster (CA15 or CA7). Each of this value contains the
frequency(kHz) and voltage(mV) at that performance level. It expects
these performance level to be passed through the SPC PERF_LVL registers.
This patch adds support to populate these performance levels from M3,
build the mapping to CPU OPPs at the boot and then use it to get and
set the CPU performance level runtime.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Pawel Moll <Pawel.Moll@arm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Convert ep93xx to use the OHCI platform driver and remove the
ohci-ep93xx bus glue driver.
Enable CONFIG_OHCI_HCD_PLATFORM in the ep93xx_defconfig so that USB
is still enabled by default on the EP93xx platform.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Cc: Ryan Mallon <rmallon@gmail.com>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Olof Johansson <olof@lixom.net>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Highlights include corenet board file consolidation, the ability to run
userspaces with lwsync on e500v1/v2, some cleanup patches that other KVM
patches will build on, support for stripped-down e6500 emulation targets,
and some fixes of minor longstanding issues.
make panda display work with recent u-boot.
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Merge tag 'omap-for-v3.13/dt-fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Few device tree changes that fix boot time warnings and
make panda display work with recent u-boot.
* tag 'omap-for-v3.13/dt-fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4-panda: add DPI pinmuxing
ARM: dts: AM33xx: Add RNG node
ARM: dts: AM33XX: Add hwspinlock node
ARM: dts: OMAP5: Add hwspinlock node
ARM: dts: OMAP4: Add hwspinlock node
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson reported:
In file included from arch/arm/include/asm/page.h:163:0,
from include/linux/mm_types.h:16,
from include/linux/sched.h:24,
from arch/arm/kernel/asm-offsets.c:13:
arch/arm/include/asm/memory.h: In function '__virt_to_idmap':
arch/arm/include/asm/memory.h:300:6: error: 'arch_virt_to_idmap' undeclared (first use in this function)
caused by arch_virt_to_idmap being placed inside a different
preprocessor conditional to its user. Move it along side its user.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
pcibios_last_bus was apparently copied from x86. On mn10300, it is
statically initialized to -1 and may be set with the "pci=lastbus=<X>"
boot option, but it is never tested. This patch removes everything
related to pcibios_last_bus.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
pcibios_last_bus was apparently copied from x86. On FR-V, it is
statically initialized to -1 and never changed unless the user boots
with "pci=lastbus=<X>". I doubt that option is used on FR-V, so this
patch removes all the code related to pcibios_last_bus.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
New u-boot versions no longer set the pinmuxing for Panda's DPI output,
and the muxing has to be done in the .dts file.
Add pinmuxing for DPI and TFP410. Without these, the DVI output on Panda
does not work with recent u-boot.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the AM33xx RNG module's device tree data.
Also add Documentation file describing the data
for the RNG module.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the hwspinlock device tree node for AM33xx family
of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the hwspinlock device tree node for OMAP4 family
of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
An NMI exception delivered from YAMON delivers the PC in ErrorPC
instead of EPC. It's also necessary to clear the Status.BEV
bit for the page fault exception handler to work properly.
[ralf@linux-mips: Let the assembler do the loading of the mask value rather
than the convoluted explicit %hi/%lo manual relocation sequence from the
original patch.]
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6035/
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/6084/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The PIIX4_ICTLR* and PIIX4_OCW* defines are not used by any other files.
Remove them.
The only file (other than fixup-malta.c which includes piix4.h in patch #1)
containing "#include <asm/mips-boards/piix4.h>" is
arch/mips/mti-malta/malta-int.c whose first version is actually
"1da177e4c3:arch/mips/mips-boards/malta/malta_int.c". In that version, in
the function get_int(), things in piix4.h are used. But now malta-int.c no
longer needs those stuff.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6032/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Make the code more readable by using defines.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6031/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Always register the R4K clocksource when CONFIG_CSRC_R4K is selected,
regardless of selected support for other clocksources. The kernel will
select the best clocksource based on their ratings, making it safe to
register R4K unconditionally and use it as a fallback should the
kernel be run on a system where other selected clocksources are
inoperable.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6024/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Checking for n<0 && n>9 makes no sense because it can never
be true. Moreover, we can have up to 64 vectored interrupts
so BUG_ON(n>9) was wrong anyway.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5909/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Nobody seems to care about this platform anymore and my attempts to find
somebody willing to provide some tlc for PowerTV have failed so far.
So let's nuke the bloody thing.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5910/
There are no users yet of task_user_regset_view. yet; users will be
implemented rsp activated in subsequent commits.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This gets us rid of the hard to maintain table of the number of syscall
arguments and paves the way for further restructuring of the syscall
code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
These are a leftover of the IRIX compat code which was removed in
2957c9e61e (kernel.org) rsp.
b934da913f236bca00c41d9e386e980586000461 (lmo) [[MIPS] IRIX: Goodbye
and thanks for all the fish].
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Allow usage of scratch register for current pgd even when
MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set
for 64r2 platforms to indicate availability of Xcontext for saving
cpuid, thus freeing Context to be used for saving PGD. This option
was also tied to using a scratch register for storing PGD.
This commit will allow usage of scratch register to store the current
pgd if one can be allocated for the platform, even when
MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0
Context register in this case.
The code to store the current pgd for the TLB miss handler is now
generated in all cases. When scratch register is available, the PGD
is also stored in the scratch register.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/5906/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
There is no reliable way to tell R4000/R4400 SC and MC variations apart,
however simple heuristic should give good results. Only the MC version
supports coherent caching so we can rely on such a mode having been set
for KSEG0 by the power-on firmware to reliably indicate an MC processor.
SC processors reportedly hang on coherent cached memory accesses and Linux
is linked to a cached load address so the firmware has to use the correct
caching mode to download the kernel image in a cached mode successfully.
OTOH if the firmware chooses to use either the non-coherent cached or the
uncached mode for KSEG0 on an MC processor, then the SC variant will be
reported, just as we currently do, so no regression here.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: MIPS Mailing List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5882/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4
[MIPS: DEC: Convert to new irq_chip functions] and
5359b938c0 [MIPS: DECstation I/O ASIC DMA
interrupt handling fix] and implements automatic handling of the two
classes of DMA interrupts the I/O ASIC implements, informational and
errors.
Informational DMA interrupts do not stop the transfer and use the
`handle_edge_irq' handler that clears the request right away so that
another request may be recorded while the previous is being handled.
DMA error interrupts stop the transfer and require a corrective action
before DMA can be reenabled. Therefore they use the `handle_fasteoi_irq'
handler that only clears the request on the way out. Because MIPS
processor interrupt inputs, one of which the I/O ASIC's interrupt
controller is cascaded to, are level-triggered it is recommended that
error DMA interrupt action handlers are registered with the IRQF_ONESHOT
flag set so that they are run with the interrupt line masked.
This change removes the export of clear_ioasic_dma_irq that now does not
have to be called by device drivers to clear interrupts explicitly
anymore. Originally these interrupts were cleared in the .end handler of
the `irq_chip' structure, before it was removed.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5874/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The semantics stay the same - on Cavium Octeon the functions were dead
code (it overrides the MIPS DMA ops) - on other platforms they contained
no code at all.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5720/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add support for the LZ4 compression scheme in the ZBOOT decompression
stub, in order to support it we need to:
- select the "lz4" compression tool to compress the vmlinux.bin
payload
- memcpy() is also required for decompress_unlz4.c so we share the
implementation between GZIP, XZ and now LZ4
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: james.hogan@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/5829/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
There is currently no corresponding ELF program header for the "text"
loadable segment which is confusing for some bootloader out there such
as CFE because it expects to find a program header matching the segment
it is trying to load. The Linux kernel ELF binary "vmlinux" has a
similar program header for the text segment so we just mimic this here
too.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: james.hogan@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/5827/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add support for the XZ compression scheme in the ZBOOT decompression
stub, in order to support it we need to:
- select the "xzkern" compression tool to compress the vmlinux.bin
payload
- link with ashldi3.o for xz_dec_run() to work
- memcpy() is also required for decompress_unxz.c so we share the
implementation between GZIP and XZ
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: james.hogan@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/5818/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
When CONFIG_SYS_SUPPORTS_ZBOOT is not enabled, we will still try to
build the decompressor code in arch/mips/boot/compressed as a
dependency for producing the vmlinuz target and this will result in
the following build failure:
OBJCOPY arch/mips/boot/compressed/vmlinux.bin
arch/mips/boot/compressed/decompress.c: In function 'decompress_kernel':
arch/mips/boot/compressed/decompress.c:105:2: error: implicit
declaration of function 'decompress'
make[1]: *** [arch/mips/boot/compressed/decompress.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [vmlinuz] Error 2
This is a genuine build failure because we have no implementation for
the decompress() function body since no kernel compression method
defined in CONFIG_KERNEL_(GZIP,BZIP2...) has been enabled.
arch/mips/Makefile already guards the install target for the "vmlinuz"
binary with a proper ifdef CONFIG_SYS_SUPPORTS_ZBOOT, we now also do the
same if we attempt to do a "make vmlinuz" and show that
CONFIG_SYS_SUPPORTS_ZBOOT is not enabled.
[ralf@linux-mips.org: Cleanup the makefile rule as suggested by James
Hogan.]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: richard@nod.at
Patchwork: https://patchwork.linux-mips.org/patch/5817/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Currently when using an initrd on a MIPS system the start of the bootmem
region of memory is set to the larger of the end of the kernel bss region
(_end) or the end of the initrd. In a typical memory layout where the
initrd is at some address above the kernel image this means that the start
of the bootmem region will be the end of the initrd. But when we are done
processing/loading the initrd we have no way to reclaim the memory region
it occupied, and we lose a large chunk of now otherwise empty RAM from our
final running system.
The bootmem code is designed to allow this initrd to be reserved (and the
code in finalize_initrd() currently does this). When the initrd is finally
processed/loaded its reserved memory is freed.
Fix the setting of the start of the bootmem map to be the end of the kernel.
[ralf@linux-mips.org: fold in the fix of Ashok Kumar <ashoks@broadcom.com>.]
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1574/
Cc: Ashok Kumar <ashoks@broadcom.com>
Patchwork: https://patchwork.linux-mips.org/patch/5883/
Patchwork: https://patchwork.linux-mips.org/patch/6028/
Patchwork: https://patchwork.linux-mips.org/patch/6064/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Based on quiet_cmd_X and cmd_X, this patch quiets the building output of
vmlinux.32 and vmlinux.64.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Sam Ravnborg <sam@ravnborg.org>
Patchwork: https://patchwork.linux-mips.org/patch/1766/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch converts the pci_load_of_ranges function to use the new common
of_pci_range_parser.
Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk>
Signed-off-by: Andrew Murray <Andrew.Murray@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-mips@linux-mips.org
Cc: jason@lakedaemon.net
Patchwork: https://patchwork.linux-mips.org/patch/5625/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The Asus WL520GC and WL520GU are based on the BCM5354 and clocked at
200MHz, but they do not have a clkfreq nvram variable set to the
correct value. This adds a workaround for these devices.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5843/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Some BCM5354 SoCs are running at 200MHz, but it is not possible to read
the clock from a register like it is done on some other SoC in ssb and
bcma. These devices should have a clkfreq nvram configuration value set
to 200, read it and set the clock to the correct value.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5842/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The nvram contains some gpio configuration for boards. It is stored in
a gpio<number>=name format e.g.
gpio8=wps_button
gpio4=robo_reset
This patches adds a function to parse these entries, so other driver
can use it.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5841/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Do not print the constant system type "Broadcom BCM47XX" but print the
name of the actual SoC in use and the detected board.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5839/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Detect on which board this code is running based on some nvram
settings. This is needed to start board specific workarounds and
configure the leds and buttons which are on different gpios on every board.
This patches add some boards we have seen, but there are many more.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5840
Patchwork: https://patchwork.linux-mips.org/patch/5855/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The CMP code is only designed to work with SMP configurations.
Fixes multiple build problems on certain randconfigs:
In file included from arch/mips/kernel/smp-cmp.c:34:0:
arch/mips/include/asm/smp.h:28:0:
error: "raw_smp_processor_id" redefined [-Werror]
In file included from include/linux/sched.h:30:0,
from arch/mips/kernel/smp-cmp.c:22:
include/linux/smp.h:135:0: note: this is the location of the
previous definition
In file included from arch/mips/kernel/smp-cmp.c:34:0:
arch/mips/include/asm/smp.h:57:20:
error: redefinition of 'smp_send_reschedule'
In file included from include/linux/sched.h:30:0,
from arch/mips/kernel/smp-cmp.c:22:
include/linux/smp.h:179:20: note: previous
definition of 'smp_send_reschedule' was here
In file included from arch/mips/kernel/smp-cmp.c:34:0:
arch/mips/include/asm/smp.h: In function 'smp_send_reschedule':
arch/mips/include/asm/smp.h:61:8:
error: dereferencing pointer to incomplete type
[...]
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/5812/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The definition of the CP0 register used to save the smp processor
id is repicated in many files, move them all to thread_info.h.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
In commit 15ef17f622
(tty: ar933x_uart: use the clk API to get the uart
clock), the AR933x UART driver for has been converted
to get the uart clock rate via the clock API and it
does not use the platform data anymore.
Remove the ar933x_uart_platform.h header file and get
rid of the superfluous variable and initialization code
in platform setup.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5832/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Remove unneeded error handling on the result of a call to
platform_get_resource_byname when the value is passed to devm_ioremap_resource.
A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
expression pdev,res,e,e1;
expression ret != 0;
identifier l;
@@
res = platform_get_resource_byname(...);
- if (res == NULL) { ... \(goto l;\|return ret;\) }
e = devm_ioremap_resource(e1, res);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Gabor Juhos <juhosg@openwrt.org>
Cc: kernel-janitors@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5725/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Since commit 9a46ad6d6d "smp: make smp_call_function_many() use
logic similar to smp_call_function_single()",
generic_smp_call_function_single_interrupt() is an alias of
generic_smp_call_function_interrupt(), so kill the redundant call.
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Cc: Jiang Liu <liuj97@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Shaohua Li <shli@kernel.org>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Jiri Kosina <trivial@kernel.org>
Cc: Wang YanQing <udknight@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arch@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5820/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
According to Software User's Manual, the event of last-level-cache
read/write misses is mapped to even counters. Odd counters of that
event number count miss cycles.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6036/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Set the default status for PCIe to disabled in the exynos5440.dtsi
file and let the board dts files such as exynos5440-ssdk5440.dts
enable the PCIe. However, keep the PCIe for SD5v1 board disabled,
because there is no PCIe slot on SD5v1 board.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
here prima2 i2c node is lacking of address-cells and size-cells.
Signed-off-by: Renwei Wu <Renwei.Wu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
here we need to add missed cell, cs and dma channels prop in SPI nodes
to match with drivers.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
there is a bus bridge for graphics 2D module lost in current dts, this patch takes it
back.
Signed-off-by: Jiansong Chen <jiansong.chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
CPHIF(Cell phone interface) is behind sys bridge, this patch adds the
missed node.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
memcontrol-monitor provides the ability of monitoring the memory bandwidth.
Signed-off-by: Ye He <ye.he@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
On an (even slightly) oversubscribed system, spinlocks are quickly
becoming a bottleneck, as some vcpus are spinning, waiting for a
lock to be released, while the vcpu holding the lock may not be
running at all.
The solution is to trap blocking WFEs and tell KVM that we're
now spinning. This ensures that other vpus will get a scheduling
boost, allowing the lock to be released more quickly. Also, using
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT slightly improves the performance
when the VM is severely overcommited.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
CPU hotplug and kexec rely on smp_ops.cpu_kill(), which is supposed
to wait for the CPU to park or power down, and perform the last
rites (such as disabling clocks etc., where the platform doesn't do
this automatically).
kexec in particular is unsafe without performing this
synchronisation to park secondaries. Without it, the secondaries
might not be parked when kexec trashes the kernel.
There is no generic way to do this synchronisation, so a new mcpm
platform_ops method power_down_finish() is added by this patch.
The new method is mandatory. A platform which provides no way to
detect when CPUs are parked is likely broken.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch factors the logical-to-physical CPU translation out of
mcpm_boot_secondary(), so that it can be reused elsewhere.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This removes the XSCALE_PMU Kconfig param, which is defined
but no longer used in makefiles and source files.
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Use CONFIG_ARCH_PHYS_ADDR_T_64BIT to determine
if ignoring or truncating of memory banks is
neccessary. This may be needed in the case of
64-bit memory bank addresses but when phys_addr_t
is kept 32-bit.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The DTB and/or the kernel command line may pass
64-bit addresses regardless of kernel configuration,
so update arm_add_memory() to take 64-bit arguments
independently of the phys_addr_t size.
This allows non-wrapping handling of high memory
banks such as the second memory bank of APE6EVM
(at 0x2_0000_0000) in case of 32-bit phys_addr_t.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is the ARM part of Christoph's patchset cleaning up the various
uses of __get_cpu_var across the tree.
The idea is to convert __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations
that use the offset. Thereby address calculations are avoided and fewer
registers are used when code is generated.
[will: fixed debug ref counting checks and pcpu array accesses]
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This code is becoming duplicated in many places. So let's consolidate
it into a handy macro that is known to be right and available for reuse.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add debug uart support for MSM8974. This patch adds a Kconfig
entry and the base address for the debug uart.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Create the hidden config DEBUG_MSM_UART and clean-up
the default selection for CONFIG_DEBUG_LL_INCLUDE.
Acked-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch proposes to remove the use of the IRQF_DISABLED flag
It's a NOOP since 2.6.35 and it will be removed one day.
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The memory pinning code in uaccess_with_memcpy.c does not check
for HugeTLB or THP pmds, and will enter an infinite loop should
a __copy_to_user or __clear_user occur against a huge page.
This patch adds detection code for huge pages to pin_page_for_write.
As this code can be executed in a fast path it refers to the actual
pmds rather than the vma. If a HugeTLB or THP is found (they have
the same pmd representation on ARM), the page table spinlock is
taken to prevent modification whilst the page is pinned.
On ARM, huge pages are only represented as pmds, thus no huge pud
checks are performed. (For huge puds one would lock the page table
in a similar manner as in the pmd case).
Two helper functions are introduced; pmd_thp_or_huge will check
whether or not a page is huge or transparent huge (which have the
same pmd layout on ARM), and pmd_hugewillfault will detect whether
or not a page fault will occur on write to the page.
Running the following test (with the chunking from read_zero
removed):
$ dd if=/dev/zero of=/dev/null bs=10M count=1024
Gave: 2.3 GB/s backed by normal pages,
2.9 GB/s backed by huge pages,
5.1 GB/s backed by huge pages, with page mask=HPAGE_MASK.
After some discussion, it was decided not to adopt the HPAGE_MASK,
as this would have a significant detrimental effect on the overall
system latency due to page_table_lock being held for too long.
This could be revisited if split huge page locks are adopted.
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The work-around for A15 errata 798181 is not needed if appropriate ECO
fixes have been applied to r3p2 and earlier core revisions. This can be
checked by reading REVIDR register bits 4 and 9. If only bit 4 is set,
then the IPI broadcast can be skipped.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Our spinlocks are only 32-bit (2x16-bit tickets) and, on processors
with 64-bit atomic instructions, cmpxchg64 makes use of the double-word
exclusive accessors.
This patch wires up the cmpxchg-based lockless lockref implementation
for ARM.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch introduces cmpxchg64_relaxed for arm, which performs a 64-bit
cmpxchg operation without barrier semantics. cmpxchg64_local is updated
to use the new operation.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Our cmpxchg64 macros are wrappers around atomic64_cmpxchg. Whilst this is
great for code re-use, there is a case for barrier-less cmpxchg where it
is known to be safe (for example cmpxchg64_local and cmpxchg-based
lockrefs).
This patch introduces a 64-bit cmpxchg implementation specifically
for the cmpxchg64_* macros, so that it can be later used by the lockref
code.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This implements output of debug messages on efm32 SoCs.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With LPAE enabled, physical address space is larger than 4GB. Allow mapping any
part of it via /dev/mem by using PHYS_MASK to determine valid range.
PHYS_MASK covers 40 bits with LPAE enabled and 32 bits otherwise.
Reported-by: Vassili Karpov <av1474@comtv.ru>
Signed-off-by: Sergey Dyasly <dserrg@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that we can deal with nested NMI due to IRET re-enabling NMIs and
can deal with faults from NMI by making sure we preserve CR2 over NMIs
we can in fact simply access user-space memory from NMI context.
So rewrite copy_from_user_nmi() to use __copy_from_user_inatomic() and
rework the fault path to do the minimal required work before taking
the in_atomic() fault handler.
In particular avoid perf_sw_event() which would make perf recurse on
itself (it should be harmless as our recursion protections should be
able to deal with this -- but why tempt fate).
Also rename notify_page_fault() to kprobes_fault() as that is a much
better name; there is no notifier in it and its specific to kprobes.
Don measured that his worst case NMI path shrunk from ~300K cycles to
~150K cycles.
Cc: Stephane Eranian <eranian@google.com>
Cc: jmario@redhat.com
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: dave.hansen@linux.intel.com
Tested-by: Don Zickus <dzickus@redhat.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20131024105206.GM2490@laptop.programming.kicks-ass.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
OK, so what I'm actually seeing on my WSM is that sched/clock.c is
'broken' for the purpose we're using it for.
What triggered it is that my WSM-EP is broken :-(
[ 0.001000] tsc: Fast TSC calibration using PIT
[ 0.002000] tsc: Detected 2533.715 MHz processor
[ 0.500180] TSC synchronization [CPU#0 -> CPU#6]:
[ 0.505197] Measured 3 cycles TSC warp between CPUs, turning off TSC clock.
[ 0.004000] tsc: Marking TSC unstable due to check_tsc_sync_source failed
For some reason it consistently detects TSC skew, even though NHM+
should have a single clock domain for 'reasonable' systems.
This marks sched_clock_stable=0, which means that we do fancy stuff to
try and get a 'sane' clock. Part of this fancy stuff relies on the tick,
clearly that's gone when NOHZ=y. So for idle cpus time gets stuck, until
it either wakes up or gets kicked by another cpu.
While this is perfectly fine for the scheduler -- it only cares about
actually running stuff, and when we're running stuff we're obviously not
idle. This does somewhat break down for perf which can trigger events
just fine on an otherwise idle cpu.
So I've got NMIs get get 'measured' as taking ~1ms, which actually
don't last nearly that long:
<idle>-0 [013] d.h. 886.311970: rcu_nmi_enter <-do_nmi
...
<idle>-0 [013] d.h. 886.311997: perf_sample_event_took: HERE!!! : 1040990
So ftrace (which uses sched_clock(), not the fancy bits) only sees
~27us, but we measure ~1ms !!
Now since all this measurement stuff lives in x86 code, we can actually
fix it.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: mingo@kernel.org
Cc: dave.hansen@linux.intel.com
Cc: eranian@google.com
Cc: Don Zickus <dzickus@redhat.com>
Cc: jmario@redhat.com
Cc: acme@infradead.org
Link: http://lkml.kernel.org/r/20131017133350.GG3364@laptop.programming.kicks-ass.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
The CS2 region contains the Assabet board configuration and status
registers, which are 32-bit. Unfortunately, some boot loaders do not
configure this region correctly, leaving it setup as a 16-bit region.
Fix this.
Cc: <stable@vger.kernel.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This updates the h3600 defconfig against the latest kernel with
some small options coming and going due to Kconfig structure,
then modernize it to:
- Configure for low latency preemptive kernel
- Configure for tickless idle
- Enable HRtimers
Tested on the iPAQ h3630.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The SA1100 was implementing its own variants of gpio_get_value()
and gpio_set_value() and only selectively falling back to
gpiolib for extended (EGPIO) handling. However the driver in
gpio/gpio-sa1100.c already handles the same functionality for
these lines, yet remain unused.
The only upside would be things like a timing-critical hotpath
on bit-banged GPIO, but that kind of things does not seem to
happen on these GPIOs, so it is not worth having the extra
complexity.
Tested with some buttons on the Compaq iPAQ H3630.
Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When removing the complex GPIO interface from the SA1100 machines,
we also removed the implicit #includes for a few header files
that was included by <linux/gpio.h> thru <mach/gpio.h>, causing
a compile warning on the simpad boardfile, as <asm/irq.h> was no
longer #included, as follows:
./../arch/arm/include/asm/irq.h:9:0: warning: "NR_IRQS" redefined
[enabled by default]
#define NR_IRQS NR_IRQS_LEGACY
^
In file included from ../../arch/arm/mach-sa1100/simpad.c:29:0:
../../arch/arm/mach-sa1100/include/mach/irqs.h:87:0: note: this is the
location of the previous definition
#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
This resolves the problem by explicitly including <asm/irq.h>
into the simpad boardfile.
Reported-by: Olof Johansson <olof@lixom.net>
Cc: Alexandre Courbot <acourbot@nvidia.com>
Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com>
Cc: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit 'f52bb722547f43caeaecbcc62db9f3c3b80ead9b'
Author: Sricharan R <r.sricharan@ti.com>
ARM: mm: Correct virt_to_phys patching for 64 bit physical addresses
introduced a __ARMEB__ macro usage in a new place, but missed the second
underscore. So correcting it here.
Also a explicit .align keyword is needed for the label with .long
data-type to be aligned on the 4 byte boundary. Otherwise this can
cause problem for thumb2 build. So adding it here.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit 9863c28a2a ("powerpc: Emulate sync
instruction variants") introduced a build breakage with
CONFIG_PPC_EMULATED_STATS enabled.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Kumar Gala <galak@kernel.org>
Cc: James Yang <James.Yang@freescale.com>
---
During "make ppc6xx_defconfig" the following happens:
HOSTCC scripts/basic/fixdep
GEN /usr/local/src/tmp/lnx/Makefile
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/zconf.tab.o
HOSTLD scripts/kconfig/conf
arch/powerpc/configs/ppc6xx_defconfig:74:warning: symbol value 'm' invalid for MCU_MPC8349EMITX
Setting CONFIG_MCU_MPC8349EMITX=y in ppc6xx_defconfig makes the warning
go away. This too has been reported by Geert Uytterhoeven a long time ago:
https://lkml.org/lkml/2011/11/13/11 - I only came across this because I
needed a "clean" defconfig for this Powerbook G5.
Signed-off-by: Christian Kujau <lists@nerdbynature.de>
[scottwood@freescale.com: cleaned up commit message slightly]
Signed-off-by: Scott Wood <scottwood@freescale.com>
In case of error, the function platform_device_register_simple() returns
RR_PTR() and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The P1010RDB-PB is similar to P1010RDB(P1010RDB-PA).
So, P1010RDB-PB use the same platform file as P1010RDB.
Then Add support for P1010RDB-PB platform.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
A few new i2c-drivers came into the kernel which clear the clientdata-pointer
on exit or error. This is obsolete meanwhile, the core will do it.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Add the missing iounmap() before return from hlwd_pic_init()
in the error handling case.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of
memory at bootup instead of 8. It is needed for "big" kernels for
instance when activating CONFIG_LOCKDEP_SUPPORT. This needs to be
taken into account in init_32 too, otherwise memory allocation soon
fails after startup.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first
three 8Mbytes pages. But the setting of MD_CTR to a pinnable entry was
missing before the pinning of the third 8Mb page. As the index is
decremented module 28 (MD_RSV4D is set) after every DTLB update, the
third 8Mbytes page was not pinned.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Currently all these boards use the same machine struct and also select
the same kernel options, so it seems a bit of redundant to keep one
separate kernel option for each board. Also update the defconfigs
according to this change.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This file is also used by some RDB and QDS boards. So the name seems
not so accurate. Rename it to corenet_generic.c. Also update the
function names in this file according to the change.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
In the current kernel, the board files for p2041rdb, p3041ds, p4080ds,
p5020ds, p5040ds, t4240qds and b4qds are almost the same except the
machine name. So this introduces a cornet_generic machine to support
all these boards to avoid the code duplication.
With these changes the file corenet_ds.h becomes useless. Just delete
it.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
C290PCIe has NAND flash present on IFC Chip Select(CS) 1.
So Add "ranges" field for NAND flash on CS1.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
B4860EMU is a emualtor target with minimum peripherals. It is based on
B4860QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
[scottwood@freescale.com: whitespace fix]
Signed-off-by: Scott Wood <scottwood@freescale.com>
T4240EMU is an emulator target with minimum peripherals. It is based on
T4240QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
[scottwood@freescale.com: whitespace fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Commit 9837b43c5f ("powerpc/85xx: enable
coreint for all the 64bit boards") removed the ifdef that avoided
coreint on 64-bit, but it missed b4_qds.c.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Kevin Hao <haokexin@gmail.com>
Cc: Shaveta Leekha <shaveta@freescale.com>
The commit e0908085fc ("powerpc/8xx: Fix
regression introduced by cache coherency rewrite") is not needed
anymore. The issue was because dcbst wrongly sets the store bit when
causing a DTLB error, but this is now fixed by commit
0a2ab51ffb ("powerpc/8xx: Fixup DAR from
buggy dcbX instructions.") which handles the buggy dcbx instructions on
data page faults on the 8xx.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[scottwood@freescale.com: fix commit message]
Signed-off-by: Scott Wood <scottwood@freescale.com>
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
The sub-nodes are also reorganized according to right I2C topology.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Enable CONFIG_AT803X_PHY to support AR8030/8033/8035 PHY.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Freescale T4240QDS reference board has extra voltage shifters added
to allow 3.3V operation, so add 3.3v voltage support for T4240QDS.
1.8v and 3.3v is recommand for eMMC and SDHC card.
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch modifies the Oops message in case of Software Emulation Exception.
The existing message is quite confusing because it refers to FPU Emulation
while most often the issue is due to either a non supported instruction
(not necessarily FPU related) or a stale instruction due to HW issues.
The new message tries to be more generic in order to make the user understand
that the Oops is due to something wrong with an instruction, not necessarily
due to an FPU instruction.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The regset defintion for SPE doesn't have the core_note_type
set, which prevents it from being dumped. Add the note type
NT_PPC_SPE for SPE regset.
Signed-off-by: Suzuki K Poulose <suzuki@in.ibm.com>
Cc: Roland McGrath <roland@hack.frob.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
bsc9131 device tree does not have these properties.
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
b4420 and b4860 device trees do not have these properties.
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Freescale platform has class code = 0x0b2000, when it boots. This makes
kernel PCI bus code to setup these devices resulting into the following
notice information when trying to enable them:
pci 0000:00:00.0: ignoring class 0x0b2000 (doesn't match header type 01)
The above information is outputted by judging value of dev->class before
pci_setup_device() function, and the DECLARE_PCI_FIXUP_HEADER quirk runs
after pci_setup_device() function. But the DECLARE_PCI_FIXUP_EARLY quirk
runs before judging value of dev->class and pci_setup_device() function.
So we use the DECLARE_PCI_FIXUP_EARLY macro to fix this issue.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Merge tag 'xtensa-next-20131015' of git://github.com/czankel/xtensa-linux
Pull Xtensa patchset from Chris Zankel:
"The main patch fixes a bug that can cause a kernel panic, and was
introduced in rc1. The other two have been discovered by a uclibc
test and 'coccinelle'"
* tag 'xtensa-next-20131015' of git://github.com/czankel/xtensa-linux:
xtensa: Cocci spatch "noderef"
xtensa: don't use alternate signal stack on threads
xtensa: fix fast_syscall_spill_registers_fixup
Two of the versatile irq definitions are incorrect, mostly because two
devices have connections to more than one interrupt controller. Fix them
by using the new interrupts-extended property to fan out without using
an awful interrupt-map nexus node.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
The standard interrupts property in device tree can only handle
interrupts coming from a single interrupt parent. If a device is wired
to multiple interrupt controllers, then it needs to be attached to a
node with an interrupt-map property to demux the interrupt specifiers
which is confusing. It would be a lot easier if there was a form of the
interrupts property that allows for a separate interrupt phandle for
each interrupt specifier.
This patch does exactly that by creating a new interrupts-extended
property which reuses the phandle+arguments pattern used by GPIOs and
other core bindings.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
[grant.likely: removed versatile platform hunks into separate patch]
Cc: Rob Herring <rob.herring@calxeda.com>
This converts the gemini machine to use generic clockevents
by rewriting the timer driver.
Cc: arm@kernel.org
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add a lot of N900 nodes
Add OPP table to OMAP5/DRA7
Add support for Newflow NanoBone board
Add i2c aliases
Add McASP and audio support
Add reset/idle on init bindings for OMAP
Add more nodes for AM4272
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Merge tag 'omap-for-v3.13/dt-late' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Some more dts changes from Benoit Cousson <bcousson@baylibre.com> via
Tony Lindgren:
- Add a lot of N900 nodes
- Add OPP table to OMAP5/DRA7
- Add support for Newflow NanoBone board
- Add i2c aliases
- Add McASP and audio support
- Add reset/idle on init bindings for OMAP
- Add more nodes for AM4272
* tag 'omap-for-v3.13/dt-late' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (42 commits)
ARM: dts: omap5-uevm: Remove pinmux for dmic pins
ARM: dts: omap5-uevm: Correct twl6040 reset GPIO pinmux
ARM: dts: TWL4030: Add power button support
ARM: dts: omap3-n900: Add LP5523 support
ARM: dts: omap3-n900: Add TLV320AIC3X support
ARM: dts: omap3-n900:: Mux RX51_LCD_RESET_GPIO in DTS
ARM: dts: omap3-n900: Add NAND support
ARM: dts: omap3-n900: Specify regulator info
ARM: dts: TWL4030: Add missing regulators
ARM: dts: omap3-n900: Add LP5523 support
ARM: dts: omap3-n900: Add vibrator device
ARM: dts: omap3-n900: GPIO key definitions
ARM: dts: omap3-n900: Add support for SD cards
ARM: dts: omap3-n900: Add UART support
ARM: dts: omap3-n900: Fix i2c bus speed
ARM: dts: omap3-n900: Add pinctrl for i2c devices
ARM: dts: DRA7: Add CPU OPP table
ARM: dts: OMAP5: Add CPU OPP table
ARM: dts: dra7-evm: add smps123 supply for CPU
ARM: dts: omap5-uevm: add smps123 supply for CPU
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Note that this branch has a dependency to the patches merged
with omap-for-v3.13/board-removal-signed-take2.
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Merge tag 'omap-for-v3.13/cpufreq-late' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Few patches to make cpufreq work for omap3 with device tree.
Note that this branch has a dependency to the patches merged
with omap-for-v3.13/board-removal-signed-take2.
* tag 'omap-for-v3.13/cpufreq-late' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP3+: use cpu0-cpufreq driver in device tree supported boot
ARM: OMAP2+: add missing lateinit hook for calling pm late init
ARM: OMAP3+: do not register non-dt OPP tables for device tree boot
Signed-off-by: Olof Johansson <olof@lixom.net>
Move some of the OMAP2+ CM and System Control Module direct
register accesses into CM- and System Control
Module-specific "drivers" underneath arch/arm/mach-omap2/. This
is a prerequisite for moving this code out of arch/arm/mach-omap2/ into
drivers/.
Basic test logs are available here:
http://www.pwsan.com/omap/testlogs/cm_scm_cleanup_a_v3.13/20131019101809/
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Merge tag 'omap-for-v3.13/cm-scm-cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Paul Walmsley <paul@pwsan.com> via Tony Lindgren:
Move some of the OMAP2+ CM and System Control Module direct
register accesses into CM- and System Control
Module-specific "drivers" underneath arch/arm/mach-omap2/. This
is a prerequisite for moving this code out of arch/arm/mach-omap2/ into
drivers/.
Basic test logs are available here:
http://www.pwsan.com/omap/testlogs/cm_scm_cleanup_a_v3.13/20131019101809/
* tag 'omap-for-v3.13/cm-scm-cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP3: control: add API for setting IVA bootmode
ARM: OMAP3: CM/control: move CM scratchpad save to CM driver
ARM: OMAP3: McBSP: do not access CM register directly
ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock
ARM: OMAP2: CM/PM: remove direct register accesses outside CM code
+ Linux 3.12-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
wait for the merge window.
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Merge tag 'omap-for-v3.13/fixes-not-urgent-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes-non-critical
From Tony Lindgren:
Few more omap fixes that are not regressions or oopses and can
wait for the merge window.
* tag 'omap-for-v3.13/fixes-not-urgent-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: irq, AM33XX add missing register check
ARM: OMAP2+: wakeupgen: AM43x adaptation
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch enables all drivers and alike to make defconfig-ed
kernels use Versatile Express specific features, like power
management services (PSCI, MCPM with drivers for DCCSB on
Fast Models and SPC on TC2), CMA for frame buffer allocation,
all virtio device drivers (for QEMU, KVM tools and Fast Models),
MTD physmap drivers with squashfs and UBIFS for flash,
I2C master, regulator and hwmon drivers and LEDs support with
most useful triggers. The maximum amount of CPUs has been
increased to 8 to facilitate big.Little systems.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch updates the Versatile Express defconfig to a level
which makes it possible to run a defconfig-ed kernel work
on the board and in QEMU with modern userspace. It does:
- update cmdline to contain "console=ttyAMA0" only
- enable devtmpfs filesystem
- enable voltage regulator support
- enable ext4 filesystem
- disable low level debug and early printk
Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
[PM: removed DEBUG_LL - it doesn't work on qemu]
[PM: reworded the commit message]
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Use macros for mxs pinctrl settings
* New board support: VF610 Cosmic/Cosmic+, imx6q-udoo, MSR M28CU3
* Support DSPI device for vf610
* Add PCIe device for imx6qdl
* Add UHS pinctrl states for imx6sl and imx6qdl
* Display support for APF and imx51-babbage boards
* Enable SPI NOR and USB for imx6sl-evk board
* Enable LVDS for imx6q-sabrelite and SPDIF for imx6qdl-wandboard
* Misc updates on boards: TX28, imx6qdl-wandboard, imx53-qsb etc.
* Some random updates on imx51 device tree
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Merge tag 'imx-dt-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo:
The imx/mxs device tree changes for 3.13:
- Use macros for mxs pinctrl settings
- New board support: VF610 Cosmic/Cosmic+, imx6q-udoo, MSR M28CU3
- Support DSPI device for vf610
- Add PCIe device for imx6qdl
- Add UHS pinctrl states for imx6sl and imx6qdl
- Display support for APF and imx51-babbage boards
- Enable SPI NOR and USB for imx6sl-evk board
- Enable LVDS for imx6q-sabrelite and SPDIF for imx6qdl-wandboard
- Misc updates on boards: TX28, imx6qdl-wandboard, imx53-qsb etc.
- Some random updates on imx51 device tree
* tag 'imx-dt-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6: (44 commits)
ARM: imx: imx6sl iomuxc syscon is compatible to imx6q
ARM: dts: imx6sl-evk: enable the SPI NOR
ARM: dts: imx6sl: add a pinctrl for ECSPI1
ARM: imx27: add missing #pwm-cells property
ARM: dts: imx6sl: add pinctrl uhs states for usdhc
ARM: dts: imx6qdl-sabresd: Add backlight support for lvds
ARM: dts: imx51-babbage: Make DVI and WVGA panel functional
ARM: imx27-apf27dev: Add framebuffer support
ARM: imx51-apf51dev: Add parallel display support
ARM: dts: imx53-qsb: Do not use GPIO1_8 as wakeup source
ARM: dts: imx53-qsb: SDHC1 does not have cd-gpios
ARM: dts: imx53-qsb: SDHC3 is connected in 8-bit mode
ARM: dts: mxs: Add MSR M28CU3 board
ARM: dts: imx6qdl-wandboard: Provide phy-reset-gpios
ARM: dts: imx6qdl-sabresd: Provide phy-reset-gpios
ARM: dts: imx6q-sabrelite: Add ethernet phy reset pin into hog
ARM: dts: imx6qdl: add pcie device node
ARM: dts: imx6q-udoo: Add initial board support
ARM: dts: mxs: Add muxing options for the SSP2 MMC
ARM: dts: add initial VF610 Cosmic/Cosmic+ board support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
It's incredibly difficult to diagnose early EFI boot issues without
special hardware because earlyprintk=vga doesn't work on EFI systems.
Add support for writing to the EFI framebuffer, via earlyprintk=efi,
which will actually give users a chance of providing debug output.
Cc: H. Peter Anvin <hpa@zytor.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Jones <pjones@redhat.com>
Signed-off-by: Matt Fleming <matt.fleming@intel.com>
* Low-level debug support for Vybrid
* Support soc bus/device for imx6
* Suspend support for imx6dl and imx6sl
* The imx6q clock updates for PCIe and audio PLL support
* IOMUXC GPR update for fec support
* Some random cleanup
* A few defconfig updates
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Merge tag 'imx-soc-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
The imx/mxs soc changes for 3.13:
* Low-level debug support for Vybrid
* Support soc bus/device for imx6
* Suspend support for imx6dl and imx6sl
* The imx6q clock updates for PCIe and audio PLL support
* IOMUXC GPR update for fec support
* Some random cleanup
* A few defconfig updates
* tag 'imx-soc-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6: (31 commits)
ARM: imx: enable suspend for imx6sl
ARM: imx: ensure dsm_request signal is not asserted when setting LPM
ARM: imx6q: call WB and RBC configuration from imx6q_pm_enter()
ARM: imx6q: move low-power code out of clock driver
ARM: imx: drop extern with function prototypes in common.h
ARM: imx: reset core along with enable/disable operation
ARM: imx: do not return from imx_cpu_die() call
ARM: imx_v6_v7_defconfig: Select CONFIG_PROVE_LOCKING
ARM: imx_v6_v7_defconfig: Enable LEDS_GPIO related options
ARM: mxs_defconfig: Turn off CONFIG_DEBUG_GPIO
ARM: imx: replace imx6q_restart() with mxc_restart()
ARM: mach-imx: mm-imx5: Retrieve iomuxc base address from dt
ARM: mach-imx: mm-imx5: Retrieve tzic base address from dt
ARM: mach-imx: clk-imx51-imx53: Retrieve base address and irq from dt
ARM: mxs_defconfig: Add CHIPIDEA_UDC support
ARM: imx: Include linux/err.h
ARM: imx_v6_v7_defconfig: Add CHIPIDEA_UDC support
ARM: imx_v6_v7_defconfig: Add SPDIF support
ARM: imx6q: clock and Kconfig update for PCIe support
ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
...
Signed-off-by: Olof Johansson <olof@lixom.net>
From Maxime Ripard:
Allwinner sunXi defconfig changes for 3.13
This pull request only see the introduction of a sunxi_defconfig.
* tag 'sunxi-defconfig-for-3.13' of https://github.com/mripard/linux:
ARM: sunxi: Add a defconfig for the Allwinner SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
The machine entries were split up, but the cleanup to remove .init_time
removed the function that the new/split entries refer to. Remove them
since they are no longer needed.
Cc: Maxime Ripard <mripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Nothing outstanding here, mostly some documentation cleanup, and the split of
the previous generic machine declaration into three different machines to
handle the sun4i/sun5i, sun6i and sun7i separately.
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Merge tag 'sunxi-core-for-3.13' of https://github.com/mripard/linux into next/soc
From Maxime Ripard:
Allwinner sunXi SoCs machine additions for 3.13
Nothing outstanding here, mostly some documentation cleanup, and the split of
the previous generic machine declaration into three different machines to
handle the sun4i/sun5i, sun6i and sun7i separately.
* tag 'sunxi-core-for-3.13' of https://github.com/mripard/linux:
Documentation: dt: Remove clock gates IDs list for Allwinner SoCs
Documentation: dt: Remove interrupt sources list for Allwinner SoCs
Documentation: sunxi: Update Allwinner SoC documentation
Documentation: sunxi: Update A13 user manual dead link
ARM: sunxi: Order Kconfig options alphabetically
ARM: sunxi: Simplify restart setup code
ARM: sunxi: Split out the DT machines for sun6i and sun7i
Signed-off-by: Olof Johansson <olof@lixom.net>
Merging in dt clock cleanup as a pre-req with some of the later SoC branches.
There are a handful of conflicts here -- some of the already merged SoC
branches should have been based on the cleanup but weren't.
In particular, a remove/add of include on highbank and two remove/remove
conflicts on kirkwood were fixed up.
* cleanup/dt-clock: (28 commits)
ARM: vt8500: remove custom .init_time hook
ARM: vexpress: remove custom .init_time hook
ARM: tegra: remove custom .init_time hook
ARM: sunxi: remove custom .init_time hook
ARM: sti: remove custom .init_time hook
ARM: socfpga: remove custom .init_time hook
ARM: rockchip: remove custom .init_time hook
ARM: prima2: remove custom .init_time hook
ARM: nspire: remove custom .init_time hook
ARM: nomadik: remove custom .init_time hook
ARM: mxs: remove custom .init_time hook
ARM: kirkwood: remove custom .init_time hook
ARM: imx: remove custom .init_time hook
ARM: highbank: remove custom .init_time hook
ARM: exynos: remove custom .init_time hook
ARM: dove: remove custom .init_time hook
ARM: bcm2835: remove custom .init_time hook
ARM: bcm: provide common arch init for DT clocks
ARM: call of_clk_init from default time_init handler
ARM: vt8500: prepare for arch-wide .init_time callback
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- Transparent Huge Pages and hugetlbfs support for KVM/ARM
- Yield CPU when guest executes WFE to speed up CPU overcommit
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Merge tag 'kvm-arm-for-3.13-2' of git://git.linaro.org/people/cdall/linux-kvm-arm into kvm-queue
Updates for KVM/ARM, take 2 including:
- Transparent Huge Pages and hugetlbfs support for KVM/ARM
- Yield CPU when guest executes WFE to speed up CPU overcommit
If the host supports it, we can and should expose it to the guest as
well, just like we already do with PIN_BASED_VIRTUAL_NMIS.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
__vmx_complete_interrupts stored uninjected NMIs in arch.nmi_injected,
not arch.nmi_pending. So we actually need to check the former field in
vmcs12_save_pending_event. This fixes the eventinj unit test when run
in nested KVM.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
As long as the hardware provides us 2MB EPT pages, we can also expose
them to the guest because our shadow EPT code already supports this
feature.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This patch updates the barrier semantics in the kuser helper functions
to take advantage of the ARMv8 additions to AArch32, which are
guaranteed to be available in situations where these functions will be
called.
Note that this slightly changes the cmpxchg functions in that they are
no longer necessarily full barriers if they return 1. However, the
documentation only states they include their own barriers "as needed",
not that they are obligated to act as a full barrier for the caller.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
CC: Matthew Leach <matthew.leach@arm.com>
CC: Dave Martin <dave.martin@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This typedef is unnecessary and should just be removed.
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
From Kukjin Kim, these are device-tree updates for Exynos. Among the changes:
- add MIPI PHY node for exynos4
- update regulator for origen and exynos5250-arndale
- add support HDMI for exynos5250, exynos5420
* commit '93457b9cb980ffeeef020c3bcd99065c3807619b':
ARM: dts: Add HDMI related I2C nodes for Arndale board
ARM: dts: enable hdmi subsystem for exynos5420 smdk board
ARM: dts: add dt nodes for hdmi subsystem for exynos5420
ARM: dts: add i2c device nodes for Exynos5420
ARM: dts: add clocks to hdmi dt node for exynos5250
ARM: dts: add mixer clocks to mixer node for Exynos5250
of/documentation: update with clock information for exynos hdmi subsystem
ARM: dts: Disable Exynos5250 I2S controllers by default
ARM: dts: Add reg property to regulator nodes in exynos5250-arndale
ARM: dts: Add fixed voltage regulator to simple bus for origen
ARM: dts: Add MIPI PHY node to exynos4.dtsi
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Merge tag 's3c24xx-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim, this branch adds device-tree support to the DMA controller
on the older Samsung SoCs. It also adds support for one of the missing SoCs
in the family (2410).
The driver has been Ack:ed by Vinod Koul, but is merged through here due
to dependencies with platform code.
* tag 's3c24xx-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C24XX: add dma pdata for s3c2410, s3c2440 and s3c2442
dmaengine: s3c24xx-dma: add support for the s3c2410 type of controller
ARM: S3C24XX: Fix possible dma selection warning
ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device
ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443
dmaengine: add driver for Samsung s3c24xx SoCs
ARM: S3C24XX: number the dma clocks
+ Linux 3.12-rc3
Signed-off-by: Olof Johansson <olof@lixom.net>
- remove unnecessary config options and header inclusions
- use CONFIG_ARCH_S3C64XX instead of PLAT_S3C64XX
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Merge tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
From Kukjin Kim:
Samsung Cleanup for v3.13
- remove unnecessary config options and header inclusions
- use CONFIG_ARCH_S3C64XX instead of PLAT_S3C64XX
* tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: remove CONFIG_MACH_EXYNOS[4, 5]_DT config options
ARM: EXYNOS: remove unnecessary header inclusions from exynos4/5 dt machine file
ARM: S3C64XX: Kill CONFIG_PLAT_S3C64XX
ASoC: samsung: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
s3c-camif: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
gpio: samsung: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
ARM: S3C64XX: Move if ARCH_S3C64XX statement into mach-s3c64xx
Signed-off-by: Olof Johansson <olof@lixom.net>
and adding SSP/SPI devices to the device tree.
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Merge tag 'ux500-dt-for-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
From Linus Walleij:
Five incremental device tree patches around the clock handling,
and adding SSP/SPI devices to the device tree.
* tag 'ux500-dt-for-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: register all SSP and SPI blocks
ARM: ux500: fix I2C4 clock bit
ARM: ux500: fix clock for GPIO blocks 6 and 7
clk: ux500: fix erroneous bit assignment
ARM: ux500: fix clock for GPIO block 8
Signed-off-by: Olof Johansson <olof@lixom.net>
This DT series sees the introduction of the cubietruck DT, plus the addition of
the i2c controller for the A20 based boards, and of the Security ID found in
all the Allwinner SoCs but the A31.
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Merge tag 'sunxi-dt-for-3.13' of https://github.com/mripard/linux into next/dt
From Maxime Ripard:
Allwinner sunXi SoCs device tree changes for 3.13
This DT series sees the introduction of the cubietruck DT, plus the addition of
the i2c controller for the A20 based boards, and of the Security ID found in
all the Allwinner SoCs but the A31.
* tag 'sunxi-dt-for-3.13' of https://github.com/mripard/linux:
ARM: sunxi: dts: Add support for the cubieboard3, the CubieTruck
ARM: sun7i: olinuxino-micro: Enable the I2C controllers
ARM: sun7i: cubieboard2: Enable the I2C controllers
ARM: sun7i: Add the pin muxing options for the I2C controllers
ARM: sun7i: Enable the I2C controllers
ARM: sunxi: dt: Add sunxi-sid to dts for sun4i, sun5i and sun7i
Signed-off-by: Olof Johansson <olof@lixom.net>
* pm-cpufreq: (167 commits)
cpufreq: create per policy rwsem instead of per CPU cpu_policy_rwsem
intel_pstate: Add Baytrail support
intel_pstate: Refactor driver to support CPUs with different MSR layouts
cpufreq: Implement light weight ->target_index() routine
PM / OPP: rename header to linux/pm_opp.h
PM / OPP: rename data structures to dev_pm equivalents
PM / OPP: rename functions to dev_pm_opp*
cpufreq / governor: Remove fossil comment
cpufreq: exynos4210: Use the common clock framework to set APLL clock rate
cpufreq: exynos4x12: Use the common clock framework to set APLL clock rate
cpufreq: Detect spurious invocations of update_policy_cpu()
cpufreq: pmac64: enable cpufreq on iMac G5 (iSight) model
cpufreq: pmac64: provide cpufreq transition latency for older G5 models
cpufreq: pmac64: speed up frequency switch
cpufreq: highbank-cpufreq: Enable Midway/ECX-2000
exynos-cpufreq: fix false return check from "regulator_set_voltage"
speedstep-centrino: Remove unnecessary braces
acpi-cpufreq: Add comment under ACPI_ADR_SPACE_SYSTEM_IO case
cpufreq: arm-big-little: use clk_get instead of clk_get_sys
cpufreq: exynos: Show a list of available frequencies
...
Conflicts:
drivers/devfreq/exynos/exynos5_bus.c
* pm-cpuidle:
ARM: AT91: DT: pm: Select ram controller standby based on DT
ARM: AT91: pm: Factorize standby function
ARM: at91: cpuidle: Move driver to drivers/cpuidle
ARM: at91: cpuidle: Convert to platform driver
ARM: ux500: cpuidle: fix section mismatch
ARM: zynq: cpuidle: convert to platform driver
ARM: zynq: cpuidle: Remove useless compatibility string
drivers: cpuidle: rename ARM big.LITTLE driver config and makefile entries
ARM: EXYNOS: convert cpuidle driver to be a platform driver
intel_idle: mark some functions with __init tag
intel_idle: mark states tables with __initdata tag
intel_idle: shrink states tables
* powercap:
PowerCap: Convert class code to use dev_groups
PowerCap: Introduce Intel RAPL power capping driver
bitops: Introduce BIT_ULL
x86 / msr: add 64bit _on_cpu access functions
PowerCap: Add to drivers Kconfig and Makefile
PowerCap: Add class driver
PowerCap: Documentation
* acpi-assorted:
ACPI: Add Toshiba NB100 to Vista _OSI blacklist
ACPI / osl: remove an unneeded NULL check
ACPI / platform: add ACPI ID for a Broadcom GPS chip
ACPI: improve acpi_extract_package() utility
ACPI / LPSS: fix UART Auto Flow Control
ACPI / platform: Add ACPI IDs for Intel SST audio device
x86 / ACPI: fix incorrect placement of __initdata tag
ACPI / thermal: convert printk(LEVEL...) to pr_<lvl>
ACPI / sysfs: make GPE sysfs attributes only accept correct values
ACPI / EC: Convert all printk() calls to dynamic debug function
ACPI / button: Using input_set_capability() to mark device's event capability
ACPI / osl: implement acpi_os_sleep() with msleep()
* acpi-hotplug:
ACPI / memhotplug: Use defined marco METHOD_NAME__STA
ACPI / hotplug: Use kobject_init_and_add() instead of _init() and _add()
ACPI / hotplug: Don't set kobject parent pointer explicitly
ACPI / hotplug: Set kobject name via kobject_add(), not kobject_set_name()
hotplug, powerpc, x86: Remove cpu_hotplug_driver_lock()
hotplug / x86: Disable ARCH_CPU_PROBE_RELEASE on x86
hotplug / x86: Add hotplug lock to missing places
hotplug / x86: Fix online state in cpu0 debug interface
Since the beginning of the parisc-linux port, sometimes 64bit SMP kernels were
not able to bring up other CPUs than the monarch CPU and instead crashed the
kernel. The reason was unclear, esp. since it involved various machines (e.g.
J5600, J6750 and SuperDome). Testing showed, that those crashes didn't happened
when less than 4GB were installed, or if a 32bit Linux kernel was booted.
In the end, the fix for those SMP problems is trivial:
During the early phase of the initialization of the CPUs, including the monarch
CPU, the PDC_PSW firmware function to enable WIDE (=64bit) mode is called.
It's documented that this firmware function may clobber various registers, and
one one of those possibly clobbered registers is %cr30 which holds the task
thread info pointer.
Now, if %cr30 would always have been clobbered, then this bug would have been
detected much earlier. But lots of testing finally showed, that - at least for
%cr30 - on some machines only the upper 32bits of the 64bit register suddenly
turned zero after the firmware call.
So, after finding the root cause, the explanation for the various crashes
became clear:
- On 32bit SMP Linux kernels all upper 32bit were zero, so we didn't faced this
problem.
- Monarch CPUs in 64bit mode always booted sucessfully, because the inital task
thread info pointer was below 4GB.
- Secondary CPUs booted sucessfully on machines with less than 4GB RAM because
the upper 32bit were zero anyay.
- Secondary CPus failed to boot if we had more than 4GB RAM and the task thread
info pointer was located above the 4GB boundary.
Finally, the patch to fix this problem is trivial by saving the %cr30 register
before the firmware call and restoring it afterwards.
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: John David Anglin <dave.anglin@bell.net>
Cc: <stable@vger.kernel.org> # 2.6.12+
Signed-off-by: Helge Deller <deller@gmx.de>
Remove the unused x86 implementation of this_cpu_xor().
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Even though the omission was found only during code review
(originally in the Xen hypervisor, looking through ACPI v5 flags
and their meanings and uses), we shouldn't be creating a
corresponding platform device in that case.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Cc: John Stultz <john.stultz@linaro.org>
Link: http://lkml.kernel.org/r/5265029D02000078000FC4D2@nat28.tlf.novell.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
struct cpu_dev's c_models is only ever set inside CONFIG_X86_32
conditionals (or code that's being built for 32-bit only), so
there's no use of reserving the (empty) space for the model
names in a 64-bit kernel.
Similarly, c_size_cache is only used in the #else of a
CONFIG_X86_64 conditional, so reserving space for (and in one
case even initializing) that field is pointless for 64-bit
kernels too.
While moving both fields to the end of the structure, I also
noticed that:
- the c_models array size was one too small, potentially causing
table_lookup_model() to return garbage on Intel CPUs (intel.c's
instance was lacking the sentinel with family being zero), so the
patch bumps that by one,
- c_models' vendor sub-field was unused (and anyway redundant
with the base structure's c_x86_vendor field), so the patch deletes it.
Also rename the legacy fields so that their legacy nature stands out
and comment their declarations.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Link: http://lkml.kernel.org/r/5265036802000078000FC4DB@nat28.tlf.novell.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Similarly to copy_from_user(), where the range check is to
protect against kernel memory corruption, copy_to_user() can
benefit from such checking too: Here it protects against kernel
information leaks.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Cc: <arjan@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/5265059502000078000FC4F6@nat28.tlf.novell.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Commits 4a31276930 ("x86: Turn the
copy_from_user check into an (optional) compile time warning")
and 63312b6a6f ("x86: Add a
Kconfig option to turn the copy_from_user warnings into errors")
touched only the 32-bit variant of copy_from_user(), whereas the
original commit 9f0cf4adb6 ("x86:
Use __builtin_object_size() to validate the buffer size for
copy_from_user()") also added the same code to the 64-bit one.
Further the earlier conversion from an inline WARN() to the call
to copy_from_user_overflow() went a little too far: When the
number of bytes to be copied is not a constant (e.g. [looking at
3.11] in drivers/net/tun.c:__tun_chr_ioctl() or
drivers/pci/pcie/aer/aer_inject.c:aer_inject_write()), the
compiler will always have to keep the funtion call, and hence
there will always be a warning. By using __builtin_constant_p()
we can avoid this.
And then this slightly extends the effect of
CONFIG_DEBUG_STRICT_USER_COPY_CHECKS in that apart from
converting warnings to errors in the constant size case, it
retains the (possibly wrong) warnings in the non-constant size
case, such that if someone is prepared to get a few false
positives, (s)he'll be able to recover the current behavior
(except that these diagnostics now will never be converted to
errors).
Since the 32-bit variant (intentionally) didn't call
might_fault(), the unification results in this being called
twice now. Adding a suitable #ifdef would be the alternative if
that's a problem.
I'd like to point out though that with
__compiletime_object_size() being restricted to gcc before 4.6,
the whole construct is going to become more and more pointless
going forward. I would question however that commit
2fb0815c9e ("gcc4: disable
__compiletime_object_size for GCC 4.6+") was really necessary,
and instead this should have been dealt with as is done here
from the beginning.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/5265056D02000078000FC4F3@nat28.tlf.novell.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Since the paravirt spinlock optimizations went into the v3.12 kernel
we have a very good performance benefit for paravirtualized KVM / Xen
kernels. Also we no longer suffer from 5% side effect on native
kernel that is mentioned in the Kconfig entry.
So update the Kconfig entry accordingly.
pvspinlock benefit on KVM link:
https://lkml.org/lkml/2013/8/6/178
Attilio's tests on native kernel impact:
http://blog.xen.org/index.php/2012/05/11/benchmarking-the-new-pv-ticketlock-implementation/
Signed-off-by: Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com>
Cc: <konrad.wilk@oracle.com>
Cc: <linux@eikelenboom.it>
Cc: <gleb@redhat.com>
Cc: <pbonzini@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1382371508-3843-1-git-send-email-raghavendra.kt@linux.vnet.ibm.com
[ Updated the changelog. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Pull MCE updates from Tony Luck:
"There is a enhanced error logging mechanism for Xeon processors.
Full description is here:
http://www.intel.com/content/www/us/en/architecture-and-technology/enhanced-mca-logging-xeon-paper.html
This patch series provides a module (and support code) to
check for an extended error log and print extra details about
the error on the console.
"
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Currently, the prototype of cpufreq_drivers target routines is:
int target(struct cpufreq_policy *policy, unsigned int target_freq,
unsigned int relation);
And most of the drivers call cpufreq_frequency_table_target() to get a valid
index of their frequency table which is closest to the target_freq. And they
don't use target_freq and relation after that.
So, it makes sense to just do this work in cpufreq core before calling
cpufreq_frequency_table_target() and simply pass index instead. But this can be
done only with drivers which expose their frequency table with cpufreq core. For
others we need to stick with the old prototype of target() until those drivers
are converted to expose frequency tables.
This patch implements the new light weight prototype for target_index() routine.
It looks like this:
int target_index(struct cpufreq_policy *policy, unsigned int index);
CPUFreq core will call cpufreq_frequency_table_target() before calling this
routine and pass index to it. Because CPUFreq core now requires to call routines
present in freq_table.c CONFIG_CPU_FREQ_TABLE must be enabled all the time.
This also marks target() interface as deprecated. So, that new drivers avoid
using it. And Documentation is updated accordingly.
It also converts existing .target() to newly defined light weight
.target_index() routine for many driver.
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Russell King <linux@arm.linux.org.uk>
Acked-by: David S. Miller <davem@davemloft.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rjw@rjwysocki.net>
Since Operating Performance Points (OPP) functions are specific
to device specific power management, be specific and rename opp.h
to pm_opp.h
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Since Operating Performance Points (OPP) data structures are specific
to device specific power management, be specific and rename opp_* data
structures in OPP library with dev_pm_opp_* equivalent.
Affected structures are:
struct opp
enum opp_event
Minor checkpatch warning resulting of this change was fixed as well.
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Since Operating Performance Points (OPP) functions are specific to
device specific power management, be specific and rename opp_*
accessors in OPP library with dev_pm_opp_* equivalent.
Affected functions are:
opp_get_voltage
opp_get_freq
opp_get_opp_count
opp_find_freq_exact
opp_find_freq_floor
opp_find_freq_ceil
opp_add
opp_enable
opp_disable
opp_get_notifier
opp_init_cpufreq_table
opp_free_cpufreq_table
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This patch moves the handling of the chip's enable pin from the board
code into the driver. It also updates all board-code files using the
driver to incorporate this change.
This is needed for device tree support of the enable pin.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Bryan Wu <cooloney@gmail.com>
This patch fixes ARMV8_EVTYPE_* macros since evtCount (event number)
field width is 10bits in event selection register.
Signed-off-by: Vinayak Kale <vkale@apm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch wires up CONFIG_CPU_BIG_ENDIAN for the AArch64 kernel
configuration.
Selecting this option builds a big-endian kernel which can boot into a
big-endian userspace.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The owner and next members of the arch_spinlock_t structure need to be
swapped when compiling for big endian.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Matthew Leach <matthew.leach@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Currently when CPUs are brought online via a spin-table, the address
they should jump to is written to the cpu-release-addr in the kernel's
native endianness. As the kernel may switch endianness, secondaries
might read the value byte-reversed from what was intended, and they
would jump to the wrong address.
As the only current arm64 spin-table implementations are
little-endian, stricten up the arm64 spin-table definition such that
the value written to cpu-release-addr is _always_ little-endian
regardless of the endianness of any CPU. If a spinning CPU is
operating big-endian, it must byte-reverse the value before jumping to
handle this.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The endianness of memory accesses at EL2 and EL1 are configured by
SCTLR_EL2.EE and SCTLR_EL1.EE respectively. When the kernel is booted,
the state of SCTLR_EL{2,1}.EE is unknown, and thus the kernel must
ensure that they are set before performing any memory accesses.
This patch ensures that SCTLR_EL{2,1} are configured appropriately at
boot for kernels of either endianness.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
[catalin.marinas@arm.com: fix SCTLR_EL1.E0E bit setting in head.S]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Currently, the code for setting the __cpu_boot_mode flag is munged in
with el2_setup. This makes things difficult on a BE bringup as a
memory access has to have occurred before el2_setup which is the place
that we'd like to set the endianess on the current EL.
Create a new function for setting __cpu_boot_mode and have el2_setup
return the mode the CPU. Also define a new constant in virt.h,
BOOT_CPU_MODE_EL1, for readability.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add CPU_LE and CPU_BE to select assembler code in little and big
endian configurations respectively.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Currently the sigreturn compat code is copied to an offset in the
vectors table. When using a BE kernel this data will be stored in the
wrong endianess so when returning from a signal on a 32-bit BE system,
arbitrary code will be executed.
Instead of declaring the code inside a struct and copying that, use
the assembler's .byte directives to store the code in the correct
endianess regardless of platform endianess.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The arm64 port contains wrappers for arm32 syscalls that pass 64-bit
values. These wrappers concatenate the two registers to hold a 64-bit
value in a single X register. On BE, however, the lower and higher
words are swapped.
Create a new assembler macro, regs_to_64, that when on BE systems
swaps the registers in the orr instruction.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch adds support for BE8 AArch32 tasks to the compat layer.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
uname -m reports the machine field from the current utsname, which should
reflect the endianness of the system.
This patch reports ELF_PLATFORM for the field, so that everything appears
consistent from userspace.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch adds support for the aarch64_be ELF format to the AArch64 ELF
loader.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
For big-endian processors, we must include
linux/byteorder/big_endian.h to get the relevant definitions for
swabbing between CPU order and a defined endianness.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch adds big-endian support to the AArch64 top-level Makefile.
This currently just passes the relevant flags to the toolchain and is
predicated on a Kconfig option that will be introduced later on.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
There's really only one bugfix in this branch, which is a fix for timers on
the integrator platform. Since Linus Walleij is resurrecting support for
the platform it seems valuable to get the fix into 3.12 even though the
regression has been around a while.
The rest are a handful of maintainers updates. If you prefer to hold those
until 3.13 then just merge the first patch on the branch which is the fix.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"There's really only one bugfix in this branch, which is a fix for
timers on the integrator platform. Since Linus Walleij is
resurrecting support for the platform it seems valuable to get the fix
into 3.12 even though the regression has been around a while.
The rest are a handful of maintainers updates. If you prefer to hold
those until 3.13 then just merge the first patch on the branch which
is the fix"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
MAINTAINERS: Add maintainers entry for Rockchip SoCs
MAINTAINERS: Tegra updates, and driver ownership
MAINTAINERS: ARM: mvebu: add Sebastian Hesselbarth
ARM: integrator: deactivate timer0 on the Integrator/CP
This branch includes:
* SoC fuse values are used as device randomness at boot.
* Initial support for the Tegra124 SoC is added. When coupled with an
appropriate clock driver, which should also be merged for 3.13, we are
able to boot to user-space using an initrd.
* The powergate code gains support for Tegra114.
This branch is based on previous pull request tegra-for-3.13-cleanup.
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Merge tag 'tegra-for-3.13-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: core SoC support changes for 3.13
This branch includes:
* SoC fuse values are used as device randomness at boot.
* Initial support for the Tegra124 SoC is added. When coupled with an
appropriate clock driver, which should also be merged for 3.13, we are
able to boot to user-space using an initrd.
* The powergate code gains support for Tegra114.
This branch is based on previous pull request tegra-for-3.13-cleanup.
* tag 'tegra-for-3.13-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: Add Tegra114 powergate support
ARM: tegra: Constify list of CPU domains
ARM: tegra: Remove duplicate powergate defines
ARM: tegra: add LP1 support code for Tegra124
ARM: tegra: re-calculate the LP1 data for Tegra30/114
ARM: tegra: enable CPU idle for Tegra124
ARM: tegra: make tegra_resume can work with current and later chips
ARM: tegra: CPU hotplug support for Tegra124
ARM: tegra: add PMC compatible value for Tegra124
ARM: tegra: add Tegra124 SoC support
ARM: tegra: add fuses as device randomness
ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
ARM: tegra: make tegra_init_fuse() __init
ARM: tegra: remove much of iomap.h
ARM: tegra: move resume vector define to irammap.h
ARM: tegra: delete gpio-names.h
ARM: tegra: delete stale header content
ARM: tegra: remove common.c
ARM: tegra: split tegra_pmc_init() in two
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This is similar to what it is done on X86: biovecs are prevented from merging
otherwise every dma requests would be forced to bounce on the swiotlb buffer.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Changes in v7:
- remove the extra autotranslate check in biomerge.c.
Introduce xen_dma_map_page, xen_dma_unmap_page,
xen_dma_sync_single_for_cpu and xen_dma_sync_single_for_device.
They have empty implementations on x86 and ia64 but they call the
corresponding platform dma_ops function on arm and arm64.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Changes in v9:
- xen_dma_map_page return void, avoid page_to_phys.
This patch adds support for using PSCI CPU_OFF calls for CPU hotplug.
With this code it is possible to hot unplug CPUs with "psci" as their
boot-method, as long as there's an appropriate cpu_off function id
specified in the psci node.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch adds the basic infrastructure necessary to support
CPU_HOTPLUG on arm64, based on the arm implementation. Actual hotplug
support will depend on an implementation's cpu_operations (e.g. PSCI).
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
With the advent of CPU_HOTPLUG, the enable-method property for CPU0 may
tells us something useful (i.e. how to hotplug it back on), so we must
read it along with all the enable-method for all the other CPUs. Even
on UP the enable-method may tell us useful information (e.g. if a core
has some mechanism that might be usable for cpuidle), so we should
always read it.
This patch factors out the reading of the enable method, and ensures
that CPU0's enable method is read regardless of whether the kernel is
built with SMP support.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
For hotplug support, we're going to want a place to store operations
that do more than bring CPUs online, and it makes sense to group these
with our current smp_enable_ops. For cpuidle support, we'll want to
group additional functions, and we may want them even for UP kernels.
This patch renames smp_enable_ops to the more general cpu_operations,
and pulls the definitions out of smp code such that they can be used in
UP kernels. While we're at it, fix up instances of the cpu parameter to
be an unsigned int, drop the init markings and rename the *_cpu
functions to cpu_* to reduce future churn when cpu_operations is
extended.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The functions in psci.c are only used from smp_psci.c, and smp_psci
cannot function without psci.c. Additionally psci.c is built when !SMP,
where it's expected that cpu_suspend may be useful.
This patch unifies the two files, removing pointless duplication and
paving the way for PSCI support in UP systems.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Final conversions to configfs for mass storage, acm_ms, and
multi gadgets.
MUSB should now work out of the box on AM335x-based boards
(beagle bone white and black) with DMA thanks to Sebastian's
work.
We can now enable VERBOSE_DEBUG on builds of drivers/usb/gadget/
by selecting CONFIG_USB_GADGET_VERBOSE.
s3c-hsotg got quite a few non-critical fixes but also learned
a few new tricks (isochronous transfers, multi count support).
The Marvel USB3 Controller driver got a memory leak fix.
devm_usb_get_phy() learned not to return NULL, ever.
Other than these patches, we have the usual set of cleanups
ranging from removal of unnecessary *_set_drvdata() to using
SIMPLE_DEV_PM_OPS.
Signed-of-by: Felipe Balbi <balbi@ti.com>
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Merge tag 'usb-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes:
usb: patches for v3.13
Final conversions to configfs for mass storage, acm_ms, and
multi gadgets.
MUSB should now work out of the box on AM335x-based boards
(beagle bone white and black) with DMA thanks to Sebastian's
work.
We can now enable VERBOSE_DEBUG on builds of drivers/usb/gadget/
by selecting CONFIG_USB_GADGET_VERBOSE.
s3c-hsotg got quite a few non-critical fixes but also learned
a few new tricks (isochronous transfers, multi count support).
The Marvel USB3 Controller driver got a memory leak fix.
devm_usb_get_phy() learned not to return NULL, ever.
Other than these patches, we have the usual set of cleanups
ranging from removal of unnecessary *_set_drvdata() to using
SIMPLE_DEV_PM_OPS.
Signed-of-by: Felipe Balbi <balbi@ti.com>
Cleanup function information block used as a modify pci function
parameter. Change reserved members to be anonymous. Fix the size
of the struct and add proper alignment information. Also put the
FIB on the stack.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Add debugfs entries regardless of CONFIG_PCI_DEBUG.
Reviewed-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cleanup arch specific pci messages. Remove unhelpful messages and
replace others with entries in the debugfs.
Reviewed-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Add four more defconfigs which we maintained outside of
the kernel tree for no good reason.
Inside of the kernel tree they can be easily used:
make whatever_defconfig
"make help" shows the available defconfigs.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Optimize this_cpu_* functions for 64 bit by making use of new instructions
that came with the interlocked-access facility 1 (load-and-*) and the
general-instructions-extension facility (asi, agsi).
That way we get rid of the compare-and-swap loop in most cases.
Code size reduction (defconfig, -march=z196): 11,555 bytes.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Remove the special cases for the this_cpu_* functions for 32 bit
in order to make it easier to add additional code for 64 bit.
32 bit will use the generic implementation.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Make psw32_user_bits a constant value again.
This is a leftover of the code which allowed to run the kernel either
in primary or home space which got removed with 9a905662 "s390/uaccess:
always run the kernel in home space".
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Fix the following bugs:
- When returning from a signal the signal handler copies the saved psw mask
from user space and uses parts of it. Especially it restores the RI bit
unconditionally. If however the machine doesn't support RI, or RI is
disabled for the task, the last lpswe instruction which returns to user
space will generate a specification exception.
To fix this check if the RI bit is allowed to be set and kill the task
if not.
- In the compat mode signal handler code the RI bit of the psw mask gets
propagated to the mask of the return psw: if user space enables RI in the
signal handler, RI will also be enabled after the signal handler is
finished.
This is a different behaviour than with 64 bit tasks. So change this to
match the 64 bit semantics, which restores the original RI bit value.
- Fix similar oddities within the ptrace code as well.
Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
The FPC_VALID_MASK has been used to check the validity of the value
to be loaded into the floating-point-control register. With the
introduction of the floating-point extension facility and the
decimal-floating-point additional bits have been defined which need
to be checked in a non straight forward way. So far these bits have
been ignored which can cause an incorrect results for decimal-
floating-point operations, e.g. an incorrect rounding mode to be
set after signal return.
The static check with the FPC_VALID_MASK is replaced with a trial
load of the floating-point-control value, see test_fp_ctl.
In addition an information leak with the padding word between the
floating-point-control word and the floating-point registers in
the s390_fp_regs is fixed.
Reported-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Reviewed-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
If a machine has no hardware support for the xts-aes or ctr-aes algorithms
they are not registered in aes_s390_init. But aes_s390_fini unconditionally
unregisters the algorithms which causes crypto_remove_alg to crash.
Add two flag variables to remember if xts-aes and ctr-aes have been added.
Signed-off-by: Ingo Tuchscherer <ingo.tuchscherer@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Just change the type of "len" to unsigned int so the compiler can prove
that we don't have a buffer overflow (and generates less code).
We get rid of these:
In function 'copy_from_user',
inlined from 'appldata_interval_handler' at
arch/s390/appldata/appldata_base.c:265:
uaccess.h:303: warning: call to 'copy_from_user_overflow' declared
with attribute warning: copy_from_user() buffer size is not provably
correct
In function 'copy_from_user',
inlined from 'appldata_timer_handler' at
arch/s390/appldata/appldata_base.c:225:
uaccess.h:303: warning: call to 'copy_from_user_overflow' declared
with attribute warning: copy_from_user() buffer size is not provably
correct
In function 'copy_from_user',
inlined from 'appldata_generic_handler' at
arch/s390/appldata/appldata_base.c:333:
uaccess.h:303: warning: call to 'copy_from_user_overflow' declared
with attribute warning: copy_from_user() buffer size is not provably
correct
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Get rid of these two warnings:
In function 'copy_from_user',
inlined from 'cmm_timeout_handler' at arch/s390/mm/cmm.c:310:
uaccess.h:303: warning: call to 'copy_from_user_overflow' declared
with attribute warning: copy_from_user() buffer size is not provably
correct
In function 'copy_from_user',
inlined from 'cmm_pages_handler' at arch/s390/mm/cmm.c:270:
uaccess.h:303: warning: call to 'copy_from_user_overflow' declared
with attribute warning: copy_from_user() buffer size is not provably
correct
Change the "len" type to unsigned int, so we can make sure that there is no
buffer overflow. This also generates less code.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Get rid of this one:
arch/s390/kernel/cache.c: In function 'cache_build_info':
arch/s390/kernel/cache.c:144: warning: 'private' may be used uninitialized
in this function
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Instead of returnin the number of bytes not copied and/or -EFAULT let the
signal handler helper functions always return -EFAULT if a user space
access failed.
This doesn't fix a bug in the current code, but makes is harder to get it
wrong in the future.
Also "smatch" won't complain anymore about the fact that the number of
remaining bytes gets returned instead of -EFAULT.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Missing parenthesis may cause problems when using the defines
together with operations of higher precedence.
Signed-off-by: Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Currently zfpcdump can only collect registers for up to CONFIG_NR_CPUS
CPUss. This dependency is not necessary. So remove it by dynamically
allocating the save area array.
Signed-off-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
Reviewed-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Steven Rostedt noted that s390 is the only architecture which calls
ftrace_push_return_trace() before ftrace_graph_entry() and therefore has
the small advantage that trace.depth gets initialized automatically.
However this small advantage isn't worth the difference and possible subtle
breakage that may result from this.
So change s390 to have the same function call order like all other
architectures: first ftrace_graph_entry(), then ftrace_push_return_trace()
Reported-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Get rid of this compile warning:
arch/s390/kernel/crash_dump.c: In function 'copy_from_realmem':
arch/s390/kernel/crash_dump.c:48:6: warning: unused variable 'rc'
[-Wunused-variable]
int rc;
^
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
The type of 'v->counter' is always 'int', and related inline assembly
code also process 'int', so use 'unsigned int' instead of 'unsigned
long' for the 'mask'.
Signed-off-by: Chen Gang <gang.chen@asianux.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
If [__]get_user_pages_fast() gets called with nr_pages == 0, the current
code would walk the page tables and pin as many pages until the first
invalid pte (or the kernel crashed while writing struct page pointers to
the pages array).
So let's handle at least the nr_pages == 0 case correctly and exit early.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Just call __get_user_pages_fast() from get_user_pages_fast() like powerpc.
This saves a lot of duplicated code.
Reviewed-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
With dirty and referenced bits implemented in software it is unnecessary
to initialize the storage key for every page. With this patch not a single
storage key operation is done for a system that does not use KVM.
For KVM set_pte_at/pgste_set_key will do the initialization for the guest
view of the storage key when the mapping for the page is established in
the host.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
The prolog of functions generated by the bpf jit compiler uses an
instruction sequence with an "ahi" instruction to create stack space
instead of using an "aghi" instruction. Using the 32-bit "ahi" is not
wrong as the stack we are operating on is an order-4 allocation which
is always aligned to 16KB. But it is more consistent to use an "aghi"
as the stack pointer is a 64-bit value.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
- turn some macros into functions
- merge two almost identical versions for 32/64 bit
- add BUILD_BUG_ON() check to make sure the passed in array is large enough
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Implement architecture-specific functionality when a PCI device is
doing a hibernate transition.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Simplify the uaccess code by removing the user_mode=home option.
The kernel will now always run in the home space mode.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
find_first_bit_left() and friends have nothing to do with the normal
LSB0 bit numbering for big endian machines used in Linux (least
significant bit has bit number 0).
Instead they use MSB0 bit numbering, where the most signficant bit has
bit number 0. So rename find_first_bit_left() and friends to
find_first_bit_inv(), to avoid any confusion.
Also provide inv versions of set_bit, clear_bit and test_bit.
This also removes the confusing use of e.g. set_bit() in airq.c which
uses a "be_to_le" bit number conversion, which could imply that instead
set_bit_le() could be used. But that is entirely wrong since the _le
bitops variant uses yet another bit numbering scheme.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Since z9 109 we have the flogr instruction which can be used to implement
optimized versions of __ffs, ffs, __fls, fls and fls64.
So implement and use them, instead of the generic variants.
This reduces the size of the kernel image (defconfig, -march=z9-109)
by 19,648 bytes.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Just like all other architectures we should use out-of-line find bit
operations, since the inline variant bloat the size of the kernel image.
And also like all other architecures we should only supply optimized
variants of the __ffs, ffs, etc. primitives.
Therefore this patch removes the inlined s390 find bit functions and uses
the generic out-of-line variants instead.
The optimization of the primitives follows with the next patch.
With this patch also the functions find_first_bit_left() and
find_next_bit_left() have been reimplemented, since logically, they are
nothing else but a find_first_bit()/find_next_bit() implementation that
use an inverted __fls() instead of __ffs().
Also the restriction that these functions only work on machines which
support the "flogr" instruction is gone now.
This reduces the size of the kernel image (defconfig, -march=z9-109)
by 144,482 bytes.
Alone the size of the function build_sched_domains() gets reduced from
7 KB to 3,5 KB.
We also git rid of unused functions like find_first_bit_le()...
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Add the debug_level_enabled() function to check if debug events for
a particular level would be logged. This might help to save cycles
for debug events that require additional information collection.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Since zEC12 we have the interlocked-access facility 2 which allows to
use the instructions ni/oi/xi to update a single byte in storage with
compare-and-swap semantics.
So change set_bit(), clear_bit() and change_bit() to generate such code
instead of a compare-and-swap loop (or using the load-and-* instruction
family), if possible.
This reduces the text segment by yet another 8KB (defconfig).
Alternatively the long displacement variants niy/oiy/xiy could have
been used, but the extended displacement field is usually not needed
and therefore would only increase the size of the text segment again.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Remove CONFIG_SMP from bitops code. This reduces the C code significantly
but also generates better code for the SMP case.
This means that for !CONFIG_SMP set_bit() and friends now also have
compare and swap semantics (read: more code). However nobody really cares
for !CONFIG_SMP and this is the trade-off to simplify the SMP code which we
do care about.
The non-atomic bitops like __set_bit() now generate also better code
because the old code did not have a __builtin_contant_p() check for the
CONFIG_SMP case and therefore always generated the inline assembly variant.
However the inline assemblies for the non-atomic case now got completely
removed since gcc can produce better code, which accesses less memory
operands.
test_bit() got also a bit simplified since it did have a
__builtin_constant_p() check, however two identical code pathes for each
case (written differently).
In result this mainly reduces the to be maintained code but is not very
relevant for code generation, since there are not many non-atomic bitops
usages that we care about.
(code reduction defconfig kernel image before/after: 560 bytes).
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
- add a typecheck to the defines to make sure they operate on an atomic_t
- simplify inline assembly constraints
- keep variable names common between functions
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
If the interlocked-access facility 1 is available we can use the asi
and agsi instructions for interlocked updates if the to be added
value is a contanst and small (in the range of -128..127).
asi and agsi do not not return the old or new value, therefore these
instructions can only be used for atomic_(add|sub|inc|dec)[64].
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Since we have an in-kernel disassembler we can make sure that
there won't be any kprobes set on random data.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Now that the in-kernel disassembler has an own header file move the
disassembler related function prototypes to that header file.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
The patch moves some of the definitions to a
header file. No functional changes involved.
I have retained the Copyright Statement from the
original file.
Signed-off-by: Suzuki K Poulose <suzuki@in.ibm.com>
[Heiko Carstens: rename s390-dis.h to dis.h]
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Rename 'insn' and 'operand' structures to more canonical names
to avoid conflicts.
struct insn represents information about an instruction, including
the mnemonics, format and opcode.
struct operand represents the 'properties' and information on howto
interpret the operand value and doesn't contain the value.
We rename these structures for avoiding a global conflict.
i.e,
1,$s/struct insn/struct s390_insn/g
1,$s/struct operand/struct s390_operand/g
Signed-off-by: Suzuki K Poulose <suzuki@in.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Same as for bitops: make use of the interlocked-access facility 1
instructions which allow to atomically update storage locations
without a compare-and-swap loop.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Get rid of the own atomic_sub_return() implementation. Otherwise we can't
make use of the interlocked-access facility 1 instructions for
atomic_sub_return(), since there is no "load and subtract" instruction
available.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
When checking the insn address wether it is a kernel image or module
address it should be an if-else-if statement not two independent if
statements.
This doesn't really fix a bug, but matches s390_free_insn_slot().
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Currently we only set the -march compiler option if the kbuild
system figured out that the compiler actually supports the selected
architecture (cc-option test).
In result this means that no -march compiler option is set when an
unsupported cpu architecture of the current compiler is selected.
The kernel compile will afterwards succeed but with the default
architecture instead of the (unsupported) selected one.
Change this behaviour, so compiles will fail if the compiler does
not support the selected cpu architecture.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Make use of the interlocked-access facility 1 that got added with the
z196 architecure.
This facilility added new instructions which can atomically update a
storage location without a compare-and-swap loop. E.g. setting a bit
within a "long" can be done with a single instruction.
The size of the kernel image gets ~30kb smaller. Considering that there
are appr. 1900 bitops call sites this means that each one saves about
15-16 bytes per call site which is expected.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.
I believe the same issue is there for other dpll4_mx_ck clocks, but as
I'm not familiar with them, I didn't touch them.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Set CLK_SET_RATE_PARENT flag for dss1_alwon_fck_3430es2,
dss1_alwon_fck_3430es1 and dpll4_m4x2_ck so that the DSS's fclk can be
configured without the need to get the parent's parent of the fclk.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This function may be called from loadable modules, so it needs
exporting.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Loc Ho <lho@apm.com>
This patch introduces cmpxchg64_relaxed for arm64 using the existing
cmpxchg_local macro, which performs a cmpxchg operation (up to 64 bits)
without barrier semantics.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Our spinlocks are only 32-bit (2x16-bit tickets) and our cmpxchg can
deal with 8-bytes (as one would hope!).
This patch wires up the cmpxchg-based lockless lockref implementation
for arm64.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch introduces a ticket lock implementation for arm64, along the
same lines as the implementation for arch/arm/.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The Microblaze PCI code copied the PowerPC irq handling, but powerpc
needs to handle broken device trees that are not present on Microblaze.
This patch removes the powerpc special case and replaces it with a
direct of_irq_parse_and_map_pci() call.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Several architectures open code effectively the same code block for
finding and mapping PCI irqs. This patch consolidates it down to a
single function.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Replace some instances of of_irq_map_one()/irq_create_of_mapping() and
of_irq_to_resource() by the simpler equivalent irq_of_parse_and_map().
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
[grant.likely: resolved conflicts with core code renames]
Signed-off-by: Grant Likely <grant.likely@linaro.org>
This patch extends the DT selftest code with some test cases for the
interrupt parsing functions.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
All the users of of_irq_parse_raw pass in a raw interrupt specifier from
the device tree and expect it to be returned (possibly modified) in an
of_phandle_args structure. However, the primary function of
of_irq_parse_raw() is to check for translations due to the presence of
one or more interrupt-map properties. The actual placing of the data
into an of_phandle_args structure is trivial. If it is refactored to
accept an of_phandle_args structure directly, then it becomes possible
to consume of_phandle_args from other sources. This is important for an
upcoming patch that allows a device to be connected to more than one
interrupt parent. It also simplifies the code a bit.
The biggest complication with this patch is that the old version works
on the interrupt specifiers in __be32 form, but the of_phandle_args
structure is intended to carry it in the cpu-native version. A bit of
churn was required to make this work. In the end it results in tighter
code, so the churn is worth it.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
All the callers of irq_create_of_mapping() pass the contents of a struct
of_phandle_args structure to the function. Since all the callers already
have an of_phandle_args pointer, why not pass it directly to
irq_create_of_mapping()?
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
struct of_irq and struct of_phandle_args are exactly the same structure.
This patch makes the kernel use of_phandle_args everywhere. This in
itself isn't a big deal, but it makes some follow-on patches simpler.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The OF irq handling code has been overloading the term 'map' to refer to
both parsing the data in the device tree and mapping it to the internal
linux irq system. This is probably because the device tree does have the
concept of an 'interrupt-map' function for translating interrupt
references from one node to another, but 'map' is still confusing when
the primary purpose of some of the functions are to parse the DT data.
This patch renames all the of_irq_map_* functions to of_irq_parse_*
which makes it clear that there is a difference between the parsing
phase and the mapping phase. Kernel code can make use of just the
parsing or just the mapping support as needed by the subsystem.
The patch was generated mechanically with a handful of sed commands.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
DMA mapping permissions were being derived from pgprot_kernel directly
without using PAGE_KERNEL. This causes them to be marked with executable
permission, which is not what we want. Fix this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Conflicts:
drivers/net/usb/qmi_wwan.c
include/net/dst.h
Trivial merge conflicts, both were overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Ingo Molnar <mingo@redhat.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: "H. Peter Anvin" <hpa@zytor.com>
CC: x86@kernel.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Guan Xuetao <gxt@mprc.pku.edu.cn>
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: "David S. Miller" <davem@davemloft.net>
CC: sparclinux@vger.kernel.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Paul Mundt <lethal@linux-sh.org>
CC: linux-sh@vger.kernel.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Paul Mackerras <paulus@samba.org>
CC: linuxppc-dev@lists.ozlabs.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
CC: linux-mips@linux-mips.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Michal Simek <monstr@monstr.eu>
CC: microblaze-uclinux@itee.uq.edu.au
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked by: Geert Uytterhoeven <geert@linux-m68k.org>
CC: linux-m68k@lists.linux-m68k.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Tony Luck <tony.luck@intel.com>
CC: Fenghua Yu <fenghua.yu@intel.com>
CC: linux-ia64@vger.kernel.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: linux-arm-kernel@lists.infradead.org
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Richard Henderson <rth@twiddle.net>
CC: linux-alpha@vger.kernel.org
In latest UEFI spec(by now it is 2.4) memory error definition
for CPER (UEFI 2.4 Appendix N Common Platform Error Record)
adds some new fields. These fields help people to locate
memory error to an actual DIMM location.
Original-author: Tony Luck <tony.luck@intel.com>
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This patch adds a new interface to decode memory device (type 17)
to help error reporting on DIMMs.
Original-author: Tony Luck <tony.luck@intel.com>
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Acked-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This H/W error log driver (a.k.a eMCA driver) is implemented based on
http://www.intel.com/content/www/us/en/architecture-and-technology/enhanced-mca-logging-xeon-paper.html
After errors are captured, more detailed platform specific information
can be got via this new enhanced H/W error log driver. Most notably we
can track memory errors back to the DIMM slot silk screen label.
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
In ftrace_syscall_enter(),
syscall_get_arguments(..., 0, n, ...)
if (i == 0) { <handle orig_x0> ...; n--;}
memcpy(..., n * sizeof(args[0]));
If 'number of arguments(n)' is zero and 'argument index(i)' is also zero in
syscall_get_arguments(), none of arguments should be copied by memcpy().
Otherwise 'n--' can be a big positive number and unexpected amount of data
will be copied. Tracing system calls which take no argument, say sync(void),
may hit this case and eventually make the system corrupted.
This patch fixes the issue both in syscall_get_arguments() and
syscall_set_arguments().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Commit de79f7b9f6 ("powerpc: Put FP/VSX and VR state into structures")
modified load_up_fpu() and load_up_altivec() in such a way that they
now use r7 and r8. Unfortunately, the callers of these functions on
32-bit machines then return to userspace via fast_exception_return,
which doesn't restore all of the volatile GPRs, but only r1, r3 -- r6
and r9 -- r12. This was causing userspace segfaults and other
userspace misbehaviour on 32-bit machines.
This fixes the problem by changing the register usage of load_up_fpu()
and load_up_altivec() to avoid using r7 and r8 and instead use r6 and
r10. This also adds comments to those functions saying which registers
may be used.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Tested-by: Scott Wood <scottwood@freescale.com> (on e500mc, so no altivec)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The CODEC power supplies should be looked up on the Arizona device as
they will be created here by device tree also update the only user of
non-device tree bindings.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
The Armada 370/XP SoC has a clock provider called "Core Divider",
that is derived from a fixed 2 GHz PLL clock.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed
other clocks. This commit adds a DT representation of this clock
through a fixed-clock compatible node.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add OPP table to OMAP5/DRA7
Add support for Newflow NanoBone board
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Merge tag 'for_3.13_super_late/dts_signed' of git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt into omap-for-v3.13/dt
Add a lot of N900 nodes
Add OPP table to OMAP5/DRA7
Add support for Newflow NanoBone board
When the omap5-evm.dts file has been renamed to omap5-uevm.dts and the sEVM
support got deprecated in favor of uEVM (or Panda5) the content was not
validated.
Panda5 does not have support for digital microphones so remove the pinmux
section for it.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
When the omap5-evm.dts file has been renamed to omap5-uevm.dts and the sEVM
support got deprecated in favor of uEVM (or Panda5) the content was not
validated.
On uEVM the twl6040 reset GPIO is from gpio5_141 and not via gpio5_145, which
was the case in sEVM.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
This patch adds support for Nokia N900 TLV320AIC3X chips.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add RX51_LCD_RESET_GPIO pin mux information to
display.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
This patch adds supports for Nokia N900 NAND memory.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add regulator names and voltage information to
the Nokia N900 DTS file.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
The twl4030.dtsi is missing some regulators. This patch adds
the missing ones and orders the regulators alphabetically.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add device tree node for the GPIO keys provided by the
N900 board. This is a simple conversion of the existing
board code.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add pin muxing support for the Nokia N900 i2c controllers.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Pull s390 fixes from Martin Schwidefsky:
"Several last minute bug fixes.
Two of them are on the larger side for rc7, the dasd format patch for
older storage devices and the store-clock-fast patch where we have
been to optimistic with an optimization"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux:
s390/time: correct use of store clock fast
s390/vmlogrdr: fix array access in vmlogrdr_open()
s390/compat,signal: fix return value of copy_siginfo_(to|from)_user32()
s390/dasd: check for availability of prefix command during format
s390/mm,kvm: fix software dirty bits vs. kvm for old machines
Pull networking fixes from David Miller:
"Sorry I let so much accumulate, I was in Buffalo and wanted a few
things to cook in my tree for a while before sending to you. Anyways,
it's a lot of little things as usual at this stage in the game"
1) Make bonding MAINTAINERS entry reflect reality, from Andy
Gospodarek.
2) Fix accidental sock_put() on timewait mini sockets, from Eric
Dumazet.
3) Fix crashes in l2tp due to mis-handling of ipv4 mapped ipv6
addresses, from François CACHEREUL.
4) Fix heap overflow in __audit_sockaddr(), from the eagle eyed Dan
Carpenter.
5) tcp_shifted_skb() doesn't take handle FINs properly, from Eric
Dumazet.
6) SFC driver bug fixes from Ben Hutchings.
7) Fix TX packet scheduling wedge after channel change in ath9k driver,
from Felix Fietkau.
8) Fix user after free in BPF JIT code, from Alexei Starovoitov.
9) Source address selection test is reversed in
__ip_route_output_key(), fix from Jiri Benc.
10) VLAN and CAN layer mis-size netlink attributes, from Marc
Kleine-Budde.
11) Fix permission checks in sysctls to use current_euid() instead of
current_uid(). From Eric W Biederman.
12) IPSEC policies can go away while a timer is still pending for them,
add appropriate ref-counting to fix, from Steffen Klassert.
13) Fix mis-programming of FDR and RMCR registers on R8A7740 sh_eth
chips, from Nguyen Hong Ky and Simon Horman.
14) MLX4 forgets to DMA unmap pages on RX, fix from Amir Vadai.
15) IPV6 GRE tunnel MTU upper limit is miscalculated, from Oussama
Ghorbel.
16) Fix typo in fq_change(), we were assigning "initial quantum" to
"quantum". From Eric Dumazet.
17) Set a more appropriate sk_pacing_rate for non-TCP sockets, otherwise
FQ packet scheduler does not pace those flows properly. Also from
Eric Dumazet.
18) rtlwifi miscalculates packet pointers, from Mark Cave-Ayland.
19) l2tp_xmit_skb() can be called from process context, not just softirq
context, so we must always make sure to BH disable around it. From
Eric Dumazet.
20) On qdisc reset, we forget to purge the RB tree of SKBs in netem
packet scheduler. From Stephen Hemminger.
21) Fix info leak in farsync WAN driver ioctl() handler, from Dan
Carpenter and Salva Peiró.
22) Fix PHY reset and other issues in dm9000 driver, from Nikita
Kiryanov and Michael Abbott.
23) When hardware can do SCTP crc32 checksums, we accidently don't
disable the csum offload when IPSEC transformations have been
applied. From Fan Du and Vlad Yasevich.
24) Tail loss probing in TCP leaves the socket in the wrong congestion
avoidance state. From Yuchung Cheng.
25) In CPSW driver, enable NAPI before interrupts are turned on, from
Markus Pargmann.
26) Integer underflow and dual-assignment in YAM hamradio driver, from
Dan Carpenter.
27) If we are going to mangle a packet in tcp_set_skb_tso_segs() we must
unclone it. This fixes various hard to track down crashes in
drivers where the SKBs ->gso_segs was changing right from underneath
the driver during TX queueing. From Eric Dumazet.
28) Fix the handling of VLAN IDs, and in particular the special IDs 0
and 4095, in the bridging layer. From Toshiaki Makita.
29) Another info leak, this time in wanxl WAN driver, from Salva Peiró.
30) Fix race in socket credential passing, from Daniel Borkmann.
31) WHen NETLABEL is disabled, we don't validate CIPSO packets properly,
from Seif Mazareeb.
32) Fix identification of fragmented frames in ipv4/ipv6 UDP
Fragmentation Offload output paths, from Jiri Pirko.
33) Virtual Function fixes in bnx2x driver from Yuval Mintz and Ariel
Elior.
34) When we removed the explicit neighbour pointer from ipv6 routes a
slight regression was introduced for users such as IPVS, xt_TEE, and
raw sockets. We mix up the users requested destination address with
the routes assigned nexthop/gateway. From Julian Anastasov and
Simon Horman.
35) Fix stack overruns in rt6_probe(), the issue is that can end up
doing two full packet xmit paths at the same time when emitting
neighbour discovery messages. From Hannes Frederic Sowa.
36) davinci_emac driver doesn't handle IFF_ALLMULTI correctly, from
Mariusz Ceier.
37) Make sure to set TCP sk_pacing_rate after the first legitimate RTT
sample, from Neal Cardwell.
38) Wrong netlink attribute passed to xfrm_replay_verify_len(), from
Steffen Klassert.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (152 commits)
ax88179_178a: Add VID:DID for Samsung USB Ethernet Adapter
ax88179_178a: Correct the RX error definition in RX header
Revert "bridge: only expire the mdb entry when query is received"
tcp: initialize passive-side sk_pacing_rate after 3WHS
davinci_emac.c: Fix IFF_ALLMULTI setup
mac802154: correct a typo in ieee802154_alloc_device() prototype
ipv6: probe routes asynchronous in rt6_probe
netfilter: nf_conntrack: fix rt6i_gateway checks for H.323 helper
ipv6: fill rt6i_gateway with nexthop address
ipv6: always prefer rt6i_gateway if present
bnx2x: Set NETIF_F_HIGHDMA unconditionally
bnx2x: Don't pretend during register dump
bnx2x: Lock DMAE when used by statistic flow
bnx2x: Prevent null pointer dereference on error flow
bnx2x: Fix config when SR-IOV and iSCSI are enabled
bnx2x: Fix Coalescing configuration
bnx2x: Unlock VF-PF channel on MAC/VLAN config error
bnx2x: Prevent an illegal pointer dereference during panic
bnx2x: Fix Maximum CoS estimation for VFs
drivers: net: cpsw: fix kernel warn during iperf test with interrupt pacing
...
Add DT OPP table for DRA7xx family of devices. This data is decoded by
OF with of_init_opp_table() helper function.
The data is based on DRA75x, DRA74x Data Manual revision F (Sept 2013).
TODO: add OPP_HIGH after AVS-Class0 is functional
NOTE: The voltage and frequency values work well only on NOM samples
and it is mandatory to use ABB/AVS Class 0 support for all OPPs.
Clock nodes are pending clock node alignment.
[nm@ti.com: cleanups and rebase to latest]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add DT OPP table for OMAP54xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
The data is based on OMAP543x ES2.0 DM Operating Condition Addendum
Version 0.6(April 2013)
NOTE: The voltage and frequency values work well only on NOM samples
and are supposed to work properly only with ABB/AVS for ALL OPPs.
TODO: Add SPEED BIN OPP after ABB and AVS support so the cpufreq works
on all samples seamlessly. Clock node is pending alignment for clock
dts conversion
[nm@ti.com: sync to latest and fixes]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
regulator smps123 supply from Palmas PMIC powers CPU0 on OMAP5uEVM.
Based on a patch by J Keerthy <j-keerthy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
With OMAP3+ and AM33xx supported SoC having defined CPU device tree
entries with operating-points and clock nodes defined, we can now use
the SoC generic cpufreq-cpu0 driver by registering appropriate device.
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM335x, AM43xx, OMAP5 and DRA7 have missing late init hook. Introduce
SoC specific hook with a call to OMAP2+ generic lateinit hook. This
allows the generic late initializations such as cpufreq hooks to be
active.
Based on out-of-tree patches that need to be introduced in
mainline, this introduction allows us to provide the foundation for
further SoC specific features as they are developed.
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP3+ supports both device tree and non-device tree boot.
Device tree bindings for OMAP3+ is supposed to be added via dts following:
Documentation/devicetree/bindings/power/opp.txt
Since we now have device tree entries for OMAP3+ cpu OPPs,
The current code wrongly adds duplicate OPPs. So, dont register OPPs
when booting using device tree.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The KVM PSCI code blindly assumes that vcpu_id and MPIDR are
the same thing. This is true when vcpus are organized as a flat
topology, but is wrong when trying to emulate any other topology
(such as A15 clusters).
Change the KVM PSCI CPU_ON code to look at the MPIDR instead
of the vcpu_id to pick a target CPU.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Now that the KVM/arm code knows about affinity, remove the hard
limit of 4 vcpus per VM.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
The L2CTLR register contains the number of CPUs in this cluster.
Make sure the register content is actually relevant to the vcpu
that is being configured by computing the number of cores that are
part of its cluster.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
In order to be able to support more than 4 A7 or A15 CPUs,
we need to fix the MPIDR computing to reflect the fact that
both A15 and A7 can only exist in clusters of at most 4 CPUs.
Fix the MPIDR computing to allow virtual clusters to be exposed
to the guest.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Correct mcspi pin descriptions to match corresponding node name and
add chip select number to be consistent with OMAP5 TRM.
Signed-off-by: Eric Witcher <ewitcher@mindspring.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Control module is not usb specific.
Changes the label to usb_ctrl_mod.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
am33xx has a INTC_PENDING_IRQ3 register that is not checked for pending
interrupts. This patch adds AM33XX to the ifdef of SOCs that have to
check this register.
Cc: stable@vger.kernel.org
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM43x has 224 interrupts and 7 banks, make it as maximum values. Keep
default values as earlier, if am43x is detected, update interrupts and
banks accordingly.
Also AM43x has only one cpu, ensure that clearing bitmask at wakeupgen
is done only for the single existing cpu, existing code assumes that
there are two cpu's.
If bitmask is cleared in wakeupgen for the nonexistent second cpu,
an imprecise abort happens as soon as Kernel switches to user space.
It was rootcaused by Sekhar Nori <nsekhar@ti.com>.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
NanoBone Specification:
-----------------------
CPU:
TI AM335x
Memory:
256MB DDR3
128MB NOR flash
128KB FRAM
Ethernet:
2 x 10/100 connected to SMSC LAN8710 PHY
USB:
1 x USB2.0 Type A
I2C:
2Kbit EEPROM (Microchip 24AA02)
RTC (Maxim DS1338)
GPIO Expander (Microchip MCP23017)
Expansion connector:
6 x UART
1 x MMC/SD
1 x USB2.0
Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Looks like omap3 is still relying on hwmod data for some basic
device tree information. Let's add the information to omap3.dtsi
so we can remove the related hwmod data once omap3 is DT only.
Acked-by: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Provide alias to allow ordering the i2c devices correctly.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Currently, on OMAP5, i2c1 and i2c5 defer probe due to pinctrl
dependencies. This changes the i2c ID each bus is registered with in
i2c-dev interface. As a result of this, many userspace tools break and
there is no consistent manner to fix the same if the i2c dev interface
have no consistent numbering.
Since this could happen for other OMAP derivatives, provide i2c alias
for all OMAP3+ SoCs to allow ordering the i2c devices correctly.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add nodes for McASP0 and McASP1 for AM43xx.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
The result of the store-clock-fast (STCKF) instruction is a bit fuzzy.
It can happen that the value stored on one CPU is smaller than the value
stored on another CPU, although the order of the stores is the other
way around. This can cause deltas of get_tod_clock() values to become
negative when they should not be.
We need to be more careful with store-clock-fast, this patch partially
reverts git commit e4b7b4238e666682555461fa52eecd74652f36bb "time:
always use stckf instead of stck if available". The get_tod_clock()
function now uses the store-clock-extended (STCKE) instruction.
get_tod_clock_fast() can be used if the fuzziness of store-clock-fast
is acceptable e.g. for wait loops local to a CPU.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Several configurations are selecting errata 798181 without SMP
being selected. This causes a warning from Kconfig:
warning: (ARCH_HIGHBANK && ARCH_KEYSTONE && SOC_OMAP5 && ARCH_TEGRA_114_SOC) selects ARM_ERRATA_798181 which has unmet direct dependencies (CPU_V7 && SMP)
The dependencies are compile time dependencies; select violates these,
resulting in:
arch/arm/kernel/built-in.o: In function `setup_processor':
psci.c:(.init.text+0x808): undefined reference to `erratum_a15_798181_init'
at build time. Fix this by fixing the select statements for Tegra and
Highbank.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The imx6sl low power mode implementation inherits imx6q/dl one,
and pm-imx6q.c can just work for imx6sl with some minor updates.
Let's enable imx6sl suspend support by reusing pm-imx6q.c and use
cpu_is_imxXX() to handle the those minor differences between imx6sl
and imx6q/dl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There is a defect in imx6 LPM design. When SW tries to enter low power
mode with following sequence, the chip will enter low power mode before
A9 CPU execute WFI instruction:
1. Set CCM_CLPCR[1:0] to 2'b00;
2. ARM CPU enters WFI;
3. ARM CPU wakeup from an interrupt event, which is masked by GPC or not
visible to GPC, such as interrupt from local timer;
4. Set CCM_CLPCR[1:0] to 2'b01 or 2'b10;
5. ARM CPU execute WFI.
Before the last step, the chip will enter WAIT mode if CCM_CLPCR[1:0] is
set to 2'b01, or enter STOP mode if CCM_CLPCR[1:0] is set to 2'b10.
The patch implements a recommended workaround for this issue.
1. SW triggers irq #32(IOMUX) to be always pending manually by setting
IOMUX_GPR1_GINT bit;
2. SW should then unmask it in GPC before setting CCM LPM;
3. SW should mask it right after CCM LPM is set (bit0-1 of CCM_CLPCR).
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The WB and RBC configuration calls are currently made from
imx6q_set_lpm() for WAIT_CLOCKED and WAIT_UNCLOCKED mode with a simple
state tracking. This becomes unnecessary since we can make the calls
from imx6q_pm_enter() directly now for suspend.
More importantly, the current call of imx6q_enable_wb() from
imx6q_set_lpm() is buggy. The CLPCR register bits configured by
imx6q_enable_wb() will get lost, because imx6q_set_lpm() caches the same
register and write it back at the end of the function. That's why the
imx6dl suspend/resume does not work currently - the wakeup from suspend
triggers a reset on imx6dl.
Moves the WB and RBC calls into imx6q_pm_enter() to save the state
tracking and fixes above bug, so that suspend/resume can start working
on imx6dl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The LPM (Low Power Mode) code that currently sits in imx6q clock driver
will be reused by imx6sl. Let's move it into pm-imx6q.c, so that we
can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl.
In order to avoid adding another ioremap for CCM block,
imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base
for pm code.
During the move, the unused CCGR macros get removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since commit 70dc8a4 (checkpatch: warn when using extern with function
prototypes in .h files), we will get checkpatch warning when updating
common.h following the existing convention which has extern for function
prototypes.
Let's change the convention to not use extern with function prototypes
in this header.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
From hotplug stress test result, resetting core during enable/disable
operation can improve cpu hotplug stability. So let's set
SRC reset bit in imx_enable_cpu() for the core when its enable bit is
accessed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
When imx_cpu_die() is being called, the cpu should never return from the
call but just in WFI and wait for hardware to take it down. So let's
do cpu_do_idle() repeatly in the call. Doing this help improve the
relibility of hotplug operation.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This is very useful for detecting 'circular locking dependency' issues.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Having CONFIG_DEBUG_GPIO=y leads to several debug messages polluting kernel log:
[ 0.580325] of_get_named_gpio_flags: can't parse gpios property of node '/regulators/3p3v[0]'
[ 0.581185] 3P3V: 3300 mV
[ 0.584827] of_get_named_gpio_flags exited with status 124
[ 0.585852] vddio-sd0: 3300 mV
[ 0.590023] of_get_named_gpio_flags exited with status 79
[ 0.590770] fec-3v3: 3300 mV
[ 0.594805] of_get_named_gpio_flags exited with status 105
[ 0.595491] usb0_vbus: 5000 mV
[ 0.599687] of_get_named_gpio_flags exited with status 104
[ 0.600380] usb1_vbus: 5000 mV
[ 0.604463] of_get_named_gpio_flags exited with status 126
[ 0.605153] lcd-3v3: 3300 mV
[ 0.608970] of_get_named_gpio_flags exited with status 77
Turn this option off, as these messages are not really useful for normal usage.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The imx6q_restart() works fine with normal reboot but will run into
problem with emergency reboot like sysrq-b. In that case, of_iomap()
gets called from interrupt context and hence triggers the BUG_ON in
__get_vm_area_node().
Actually, since commit c1e31d1 (ARM: imx: create
mxc_arch_reset_init_dt() for DT boot), imx6q/dl should try to use
mxc_restart() by calling mxc_arch_reset_init_dt() beforehand, where
things like of_iomap() can be done.
The patch updates mxc_restart() a little bit to get it work for imx6q/dl
and kill imx6q_restart() completely.
Reported-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As mx53 is a dt-only SoC, we should retrieve the iomuxc base address from the
device tree, instead of using the old MX53_IO_ADDRESS method.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As mx53 is a dt-only SoC, we should retrieve the tzic base address from the
device tree, instead of using the old MX53_IO_ADDRESS method.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As mx53 is a dt-only SoC, we should retrieve the gpt base address and irq
from the device tree, instead of using the old MX53_IO_ADDRESS method.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The IS_ERR() macro is defined in the linux/err.h header file, so include
it explicitly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 has two general-purpose LVDS clocks that can be driven
from a variety of sources. This patch adds a mux and a gate for
both of these clocks.
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The patch enables soc bus infrastructure and adds a function
imx_soc_device_init() to report soc info via soc device interface for
imx6qdl and imx6sl. With the support, user space can get soc related
info by looking at sysfs like below.
$ cat /sys/devices/soc0/machine
Freescale i.MX6 Quad SABRE Smart Device Board
$ cat /sys/devices/soc0/family
Freescale i.MX
$ cat /sys/devices/soc0/soc_id
i.MX6Q
$ cat /sys/devices/soc0/revision
1.2
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add imx6sl support into imx_init_revision_from_anatop(), so that it can
be used to initialize cpu type and revision on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The patch creates a common function imx_init_revision_from_anatop() by
merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any
SoC that encodes revision info in anatop can use it to initialize
revision.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It calls imx_set_soc_revision() to set up soc revision in
imx6q_init_revision(), and replaces all the occurrences of
imx6q_revision() with common helper imx_get_soc_revision().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Similar to what we do for cpu type, the patch adds helper functions
imx_set_soc_revision() and imx_get_soc_revision() to maintain
imx_soc_revision in cpu.c.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add low-level debug support for vybrid, so that earlyprintk can be
enabled for debugging early boot issue.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This flag is a NOOP since 2.6.35 and can be removed.
This is an update for 3.11 of a patch already sent for 3.10
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Config iomux-gpr1 to select clock source for fec system clock.
Clear gpr1[14], gpr1[18-17] bit to select the fec clock source
from internal anatop PLL.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There's a pll4_audio_div clock, an extra divider for pll4, missing
in current clock tree, thus add it.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
EXYNOS is now Device Tree (DT) only platform so it makes no sense to have
config options responsible for enabling platform specific DT support.
Moreover the kernel image won't even link if neither CONFIG_MACH_EXYNOS4_DT
nor CONFIG_MACH_EXYNOS5_DT config option is enabled (linker fails with "no
machine record defined" error).
Remove CONFIG_MACH_EXYNOS[4,5]_DT config options and just use the standard
CONFIG_ARCH_EXYNOS[4,5] ones instead.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
s3c2410 and s3c2442 share the same dma channels while s3c2440 has
slight differences. But on all three the reachable sources per dma
channel has constraints attached and thus encodes the usable
combinations using the S3C24XX_DMA_CHANREQ macro.
This also fixes the warning about s3c2410_dma_resource being unused
as reported by Olof Johansson.
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Currently the s3c sound support selects CONFIG_S3C2410_DMA on s3c24xx
architectures while the generic dma config is enabled by CONFIG_S3C24XX_DMA.
With the way the Kconfig options are layed out currently it is possible
to enable Samsung sound support without enabling the necessary dma support
resulting in warnings like
warning: (SND_SOC_SAMSUNG && SND_S3C24XX_I2S && SND_S3C2412_SOC_I2S &&
SND_SOC_SAMSUNG_SMDK2443_WM9710 && SND_SOC_SAMSUNG_LN2440SBC_ALC650)
selects S3C2410_DMA which has unmet direct dependencies (ARCH_S3C24XX &&
S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442))
Therefore bring the s3c2410 dma support in line with the way the other
s3c24xx SoCs handle this by having the SoC dma-support selected if the generic
s3c dma support is enabled and have the sound support depend on S3C24XX_DMA
on these arches. The s3c2442 is using the same dma descriptors and therefore
also selected S3C2410_DMA.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on beagle after the Generic PHY framework was
merged in greg/usb-next. [1]
[1] - https://lkml.org/lkml/2013/9/27/581
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
AM335x EVM-SK have only support for audio playback (stereo jack on the
board) via tlv320aic3106 codec connected to McASP1.
Enable the support for audio playback on the board:
- McASP1 configuration
- tlv320aic3106 configuration
- Machine driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
This patch adds a second tuple to reg property. The new property tuple
describes the memory location for data port registers mapped trough
L3 bus on am33xx. The both property tuples are named accordingly in
the reg-names property.
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Darren Etheridge <detheridge@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
-> Adding pinmux for cpsw, i2c0.
-> Enabling the modules that are present in AM4372 EPOS EVM
These modules are tested on AM4372 EPOS EVM.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Populate nodes for l2-cache-controller, EDMA, mailbox,
mmc, sham.
Update as well DT properties for epwmss, aes, des.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Added dr_mode property in dwc3 and set its default mode to device.
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
smps10 should be enabled only in the case of host mode. So stop
doing always_on, boot_on from smps10_out1. The driver will enable
it in host mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Do not reset GPIO1 at boot-up because GPIO 7 in GPIO1 block is used on
OMAP4460 PandaBoard-ES to select voltage register in TPS62361 which
supplies VDD_MPU.
Without this, OMAP4460 PandaBoard-ES boards fail to boot-up because
MPU voltage switches over to VSET0 voltage value (boot voltage) which
is not sufficient to operate the device at OPP100.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Do not reset GPIO0 at boot-up because GPIO0 is used
on AM335x EVM-SK to control VTT regulators on DDR3.
Without this EVM-SK boards fail to boot-up because
of DDR3 corruption.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to pass this information from DT.
Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on GAT04 and N900 after the Generic PHY framework was
merged in greg/usb-next. [1]
[1] - https://lkml.org/lkml/2013/9/27/581
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
The arm arch timers frequency are now programmed in the CNTFREQ
per-cpu register by the timer code using the secure API [1].
So remove the redundant entry from the dts.
[1] http://marc.info/?l=linux-omap&m=138139106312786&w=2
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
net_get_random_once(intrduced in the next patch) uses static_keys in
a way that they get enabled on boot-up instead of replaced with an
ideal_nop. So check for default_nop on initial enabling.
Other architectures don't check for this.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Jason Baron <jbaron@redhat.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Eric Dumazet <edumazet@google.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: x86@kernel.org
Signed-off-by: Hannes Frederic Sowa <hannes@stressinduktion.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Generate ep93xx_defconfig by doing:
make ep93xx_defconfig
make savedefconfig
mv defconfig arch/arm/configs/ep93xx_defconfig
No function change. This just refreshes the ep93xx_defconfig to make it
easier and cleaner when adding new entries.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Ryan Mallon <rmallon@gmail.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Olof Johansson <olof@lixom.net>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In order for ASID macro to be used as expression passed to
inline asm as 'r' operand it needs to give 32 bit unsigned result,
not unsigned 64bit expression.
Otherwise when 64bit ASID is passed to inline assembler statement
as 'r' operand (32bit) compiler behavior is not well specified.
For example when __flush_tlb_mm function compiled in big endian
case, and ASID is passed to tlb_op macro directly, 0 will be passed
as 'mcr 15, 0, r4, cr8, cr3, {2}' argument in r4, unless ASID
macro changed to produce 32 bit result.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
In big endian mode mcpm_entry_point is first function
that called on secondaries CPU. First it should switch
CPU into big endian code.
[ben.dooks@codethink.co.uk: merge fix patch from Victor into this]
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
In case of BE8 kernel data is in BE order whereas code stays in LE
order. Move sigreturn_codes to separate .S file and use proper
assembler mnemonics for these code snippets. In this case compiler
will take care of proper instructions byteswaps for BE8 case.
Change assumes that sufficiently Thumb-capable tools are used to
build kernel.
Problem was discovered during ltp testing of BE system: all rt_sig*
tests failed. Tested against the same tests in both BE and LE modes.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Fix inline asm for atomic64_xxx functions in arm atomic.h. Instead of
%H operand specifiers code should use %Q for least significant part
of the value, and %R for the most significant part of the value. %H
always returns the higher of the two register numbers, and therefore
it is not endian neutral. %H should be used with ldrexd and strexd
instructions.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
The arch_kgdb_breakpoint() function uses an inline assembly directive
to assemble a specific instruction using .word. This means the linker
will not treat is as an instruction, and therefore incorrectly swap
the endian-ness if running BE8.
As noted, this code means that kgdb is really only usable on arm32
kernels, and should be made dependant on not being a thumb2 kernel
until fixed. However this is not something to be added to this patch.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Currently BUG() uses .word or .hword to create the necessary illegal
instructions. However if we are building BE8 then these get swapped
by the linker into different illegal instructions in the text. This
means that the BUG() macro does not get trapped properly.
Change to using <asm/opcodes.h> to provide the necessary ARM instruction
building as we cannot rely on gcc/gas having the `.inst` instructions
which where added to try and resolve this issue (reported by Dave Martin
<Dave.Martin@arm.com>).
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Use <asm/opcodes.h> to correctly transform instruction byte ordering
into in-memory ordering.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
The <hardware/coresight.h> needs to take into account the endian-ness
of the processor when reading and writing data, so change to using
the readl/writel relaxed variants from the raw ones.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
To avoid having to make every text section swap the instruction order
of all instructions, make sure modules are built also built with --be8
(as is the current kernel final link).
If we do not do this, we would end up having to swap all instructions
when loading a module, instead of just the instructions that we are
applying ELF relocations to.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
When in BE8 mode, our instructions are not in the same ordering as the
data, so use <asm/opcodes.h> to take this into account.
Note, also requires modules to be built --be8
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
The trap handler needs to take into account the endian configuration of
the system when loading instructions. Use <asm/opcodes.h> to provide the
necessary conversion functions.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
If we are in BE8 mode, we must deal with the instruction stream being
in LE order when data is being loaded in BE order. Ensure the data is
swapped before processing to avoid thre following:
Change to using <asm/opcodes.h> to provide the necessary conversion
functions to change the byte ordering.
This stops the following warning messages from the kernel on a fault:
Unhandled fault: alignment exception (0x001) at 0xbfa09567
Alignment trap: not handling instruction 030091e8 at [<80333e8c>]
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Apart from a xgmac driver issue, the highbank seems to work correctly in
big-endian mode. Allow the selection of big-endian in the system.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Rob Herring <rob.herring@calxeda.com>
The smp_scu driver needs to use the relaxed readl/write accessors
to avoid any issues with the endian mode the processor core is in.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Ensure the twd driver uses the correct calls to access the hardware
to ensure that we do not end up with data in the wrong endian format.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
The PL01X debug code needs to take into account which endian mode the
processor is running in. If it is big-endian, ensure the data is swapped
appropriately.
Note, we could do this slightly more efficiently if we have an macro to
do the necessary swap for the bits used by test.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
If we are booting in LE and compiled for BE8, then add code to
set the state to bE8. Since the instruction stream is always LE,
we do not need to do anything special to the instruction.
Also ensure that the secondary processors are started in the same mode.
Note, we do add about 20 bytes to the kernel image, but it seems easier
to do this than adding another configuration to change.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The fixup_pv_table assumes that the instructions are in the same
endian configuration as the data, but when the CPU is running in
BE8 the instructions stay in little-endian format.
Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the
alterations to the instructions taking in to account the LDR/STR
will be swapping the data endian-ness.
Since the code is only modifying a byte, we avoid dual-swapping
the data, and just change the bits we clear and ORR in (in the
case where the code is not thumb2).
For thumb2, we add the necessary rev16 instructions to ensure that
the instructions are processed in the correct format, as it was
easier than re-writing the code to contain a mask and shift.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Add ARM_BE8() helper to wrap any code conditional on being
compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
existing places where this is to use it.
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
The Kconfig for arch/arm/mach-ixp4xx has a local definition
of ARCH_SUPPORTS_BIG_ENDIAN which could be used elsewhere.
This means that if IXP4xx is selected and this symbol is
selected eleswhere then an warning is produced.
Clean the following error up by making the symbol be
selected by the main ARCH_IXP4XX definition and have a
common definition in arch/arm/mm/Kconfig
warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)
warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Latest udev requires that DEVTMPFS and DEVTMPFS_MOUNT are enabled, else
initrd will fail to find root filesystem. Enable missing BLK_DEV_INITRD
for B180 and C3000 machines.
Signed-off-by: Helge Deller <deller@gmx.de>
This reverts commit 320c90be7b.
Christoph Hellwig <hch@infradead.org> commented:
This one shouldn't go in - Geert sent it a bit prematurely, as Lustre
shouldn't use it just to reimplement core VM functionality (which it
shouldn't use either, but that's a separate story).
Signed-off-by: Helge Deller <deller@gmx.de>
OMAP3 PM core requires IVA2 bootmode to be set to idle during init. Currently,
a direct register write is used for this. Add a new ctrl API for this purpose
instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP3 PM code for off-mode currently saves the scratchpad contents for CM
registers within OMAP control module driver. However, as we are separating
CM code into its own driver, this must be moved also. This patch adds a
new API for saving the CM scratchpad contents and uses this from the high
level scratchpad save function.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
McBSP driver require special hacks to enable/disable the autoidle feature
for its interface clock for the proper function of the sidetone hardware.
Currently the driver just writes CM registers directly, which should be
avoided. Thus, changed the driver to use the new deny/allow_autoidle
clock API calls.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some drivers require direct access to the autoidle functionality of the
interface clocks. Added clock APIs for these, so that the drivers do not
need to access CM registers directly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Users of the CM funtionality should not access the CM registers directly
by themselves. Thus, added new CM driver APIs for the OMAP2 specific
functionalities which support the existing direct register accesses, and
changed the platform code to use these. This is done in preparation
for moving the CM code into its own individual driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
BookE version of user_disable_single_step() clears DBCR0_IC for the
instruction completion debug, but did not also clear DBCR0_BT for the
branch taken exception. This behavior was lost by the 2/2010 patch.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
KVM need this function when switching from vcpu to user-space
thread. My subsequent patch will use this function.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Acked-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This way we can use same data type struct with KVM and
also help in using other debug related function.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Acked-by: Michael Neuling <mikey@neuling.org>
[scottwood@freescale.com: removed obvious debug_reg comment]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use DEFINE_PER_CPU to allocate thread_info statically instead of kmalloc().
This can avoid introducing more memory check codes.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
[scottwood@freescale.com: wrapped long line]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Extend the list of power gates found on Tegra114. Note that there are
now holes in the list, so perhaps a simple array is no longer the best
data structure to represent it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
There's no need to modify these at runtime, it is static data and never
needs to change.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Instead of duplicating powergate defines, reuse the ones from the
include/linux/tegra-powergate.h header file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch re-calculates the LP1 data of tegra30/114_sdram_pad_address
to base on its label not rely on others. This can make easier to
maintain if some other Tegra chips keep re-using these codes in the
future. And change the name of tegra30_sdram_pad_save to
tegra_sdram_pad_save to make it more common to other chips.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The CPUIdle function of Tegra124 is identical to Tegra114, so we share
the same driver with Tegra114.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Because the CPU0 was the first up and the last down core when cluster
power up/down or platform suspend. So only CPU0 needs the rest of the
functions to reset flow controller and re-enable SCU and L2. We also
move the L2 init function for Cortex-A15 to there. The secondery CPU
can just call cpu_resume.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The procedure of CPU hotplug for Tegra124 is same with Tegra114. We
re-use the same function with it.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The PMC HW is not identical to the existing Tegra SoC. Hence add to it.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add Tegra124 SoC support that base on CortexA15MP Core. And enable the
SMP function that can re-use the same procedure with Tegra114.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Various fuses on Tegra include information that's unique to an individual
chip, or a subset of chips. Call add_device_randomness() with this data
to perturb the initial state of the random pool.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
omap3 boards.
Note that that these are based on a merge of the
following for the dependencies:
- v3.12-rc5 for fixes to pinctrl mask
- omap-for-v3.13/dt-signed to avoid pointless merge conflicts
- omap-for-v3.13/quirk-signed for legacy pdata handling
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Merge tag 'omap-for-v3.13/board-removal-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Changes needed to drop legacy booting support for some
omap3 boards.
Note that that these are based on a merge of the
following for the dependencies:
- v3.12-rc5 for fixes to pinctrl mask
- omap-for-v3.13/dt-signed to avoid pointless merge conflicts
- omap-for-v3.13/quirk-signed for legacy pdata handling
* tag 'omap-for-v3.13/board-removal-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (125 commits)
ARM: OMAP2+: remove legacy support for IGEP boards
ARM: OMAP2+: Remove legacy support for zoom platforms
ARM: OMAP2+: Remove legacy booting support for omap3 EVM
ARM: OMAP2: delete board-rm680
ARM: dts: add minimal DT support for Nokia N950 & N9 phones
ARM: dts: Add basic support for zoom3
ARM: dts: Add basic support for TMDSEVM3730 (Mistral AM/DM37x EVM)
ARM: dts: Add common support for omap3-evm
ARM: dts: Shared file for omap GPMC connected smsc911x
+Linux 3.12-rc5
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Commit f8e7ba66 (ARM: OMAP1: fix incorrect placement of
__initdata tag) fixed things but we started seeing section
warnings. Looks like I missed those in my automatic
build scripts:
Section mismatch in reference from the variable omap7xx_gpio6 to the (unknown reference) .init.data:(unknown)
Section mismatch in reference from the variable omap7xx_gpio6 to the (unknown reference) .init.data:(unknown)
Section mismatch in reference from the variable omap7xx_gpio5 to the (unknown reference) .init.data:(unknown)
...
Fix the issue by removing __initdata for the resources.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Device Tree support for IGEP boards in mainline is almost
finished. The only remaining bits are support for the
Marvell SD8686 wifi + BT and TFP410 DVI chips.
Adding support for these should be straightforward so let's
not block OMAP3 moving to Device Tree only boot and remove
the board file for IGEP boards.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We now have pretty decent device tree based support for
zoom platforms. It's not complete, but basics work for
me so adding more features should be quite trivial.
Looks like also 3630 sdp is zoom based, and looking
at it's board file should also be trivial to support
with the device tree based booting.
Patches are welcome if people are still using these.
Signed-off-by: Tony Lindgren <tony@atomide.com>
We now have pretty decent support with the device tree
based booting. Patches to add more features are welcome.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Delete board file for Nokia RM-680/RM-696 (N950/N9). DT-based booting
should be used for further development on this HW.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add minimal DT support for Nokia N950 & N9 phones. The same functionality
that is provided by the current board file should work: serial console,
USB, OneNAND and MMC.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
I've tested serial, MMC, smsc911x and wl12xx on zoom3. As my
omap is an early ES revision, I have not been able to test
off-idle on this one. But anyways, I'd say we have enough
device tree support for the zoom to be able to drop the
board-zoom files. Patches are welcome to add further features
to this .dts file.
Signed-off-by: Tony Lindgren <tony@atomide.com>
The imx6sl iomuxc syscon is compatible to imx6q, so let's add
compatible string 'fsl,imx6q-iomuxc-gpr' for imx6sl iomuxc syscon node.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
- addition of sound for at91sam9n12
- a little fix for MMC vs. SPI on at91sam9g20ek
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Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre:
First DT series for 3.13
- addition of sound for at91sam9n12
- a little fix for MMC vs. SPI on at91sam9g20ek
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91: remove pinctrl conflict between mmc and SPI for at91sam9g20ek
ARM: at91: add sound support on at91sam9n12ek board
ARM: at91: enable ssc on at91sam9n12ek board
ARM: at91: enable wm8904 on at91sam9n12ek board
ARM: at91: add ssc dma parameter for at91sam9n12
ARM: at91: add at91sam9n12 ssc clock in look up table
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- a little non-urgent fix
- addition of DT files to MAINTAINERS
- more important, the splitting of .dtsi files
that allows to precisely choose the peripherals
that are present for a particular SoC.
It is useful for upcoming move to common cloks.
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Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
From Nicolas Ferre:
First cleanup series for 3.13
- a little non-urgent fix
- addition of DT files to MAINTAINERS
- more important, the splitting of .dtsi files
that allows to precisely choose the peripherals
that are present for a particular SoC.
It is useful for upcoming move to common cloks.
* tag 'at91-cleanup' of git://github.com/at91linux/linux-at91:
MAINTAINERS: Add patterns for DTS files for AT91
ARM: at91: remove init_machine() as default is suitable
ARM: at91/dt: split sama5d3 peripheral definitions
ARM: at91/dt: split sam9x5 peripheral definitions
ARM: at91: cam60: fix incorrect placement of __initdata tag
This will be the last new set of hwmod data for any SoC
as future SoCs will use a driver and device tree based
approach. But before that can be dealt with, we need to
first sort out the pending driver/clk issues.
Queued by Paul Walmsley <paul@pwsan.com>:
Add hwmod and PRCM data for the TI AM43xx family of SoCs.
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
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Merge tag 'omap-for-v3.13/am43xx-hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
Changes needed for am43xx for the hwmod data.
This will be the last new set of hwmod data for any SoC
as future SoCs will use a driver and device tree based
approach. But before that can be dealt with, we need to
first sort out the pending driver/clk issues.
Queued by Paul Walmsley <paul@pwsan.com>:
Add hwmod and PRCM data for the TI AM43xx family of SoCs.
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
* tag 'omap-for-v3.13/am43xx-hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2: hwmod: Add qspi data for am437x.
ARM: OMAP2+: hwmod: Add USB hwmod data for AM437x.
ARM: OMAP2+: AM43x PRCM init
ARM: OMAP2+: AM43x: PRCM kbuild
ARM: OMAP2+: hwmod: AM43x operations
ARM: OMAP2+: hwmod: AM43x support
ARM: OMAP2+: CM: AM43x clockdomain data
ARM: OMAP2+: PM: AM43x powerdomain data
ARM: OMAP2+: PRCM: AM43x definitions
ARM: OMAP2+: hwmod: AM335x: remove static register offs
ARM: OMAP2+: hwmod: AM335x: runtime register update
ARM: OMAP2+: hwmod: AM335x/AM43x: move common data
ARM: OMAP2+: CM: cm_inst offset s16->u16
Signed-off-by: Kevin Hilman <khilman@linaro.org>
These MMC and SPI buses can't be configured at the same time because they
share the same traces on the EK board.
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
From Heiko Stübner:
Support for the RK3188 SoC, basic RK3188 based Radxa Rock board
and RK3066a based BQ Curie2 tablet.
* rockchip/boards:
ARM: rockchip: add support for rk3188 and Radxa Rock board
ARM: rockchip: add dts for bqcurie2 tablet
ARM: rockchip: enable arm-global-timer
ARM: rockchip: move shared dt properties to common source file
and fix for the selection of the TWD.
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Merge tag 'v3.13-rockchip-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes-non-critical
From Heiko Stübner:
Romoval of obsolete (never used) dt properties
and fix for the selection of the TWD.
* tag 'v3.13-rockchip-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: remove obsolete rockchip,config properties
ARM: rockchip: fix wrong use of non-existent CONFIG_LOCAL_TIMERS
This adds the SSP and SPI blocks to the device tree and makes
them active. Only this way can their clocks be properly gated
off at boot.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The PCLK for I2C4 is controlled by bit 10 in the PCKEN registers
while the KCLK is controlled by bit 9 on the KCKEN, it's
one of these odd assymetric things. Correct the PCLK bit to 10.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The clock assignment in the device tree for GPIO blocks 6
and 7 was incorrect, indicating this was managed by bit 1 on
PRCC 2 while it was in fact bit 11 on PRCC 2.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The clock assignment in the device tree for GPIO block 8 was
incorrect, indicating this was managed by bit 1 on PRCC 6
while it was in fact bit 1 on PRCC 5.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
add a pinctrl for ECSPI1. This pinctrl can be used in the imx6sl-evk board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The pwm-node is missing its #pwm-cells property. The pwm-framework will
complain about this.
Add the missing property.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Support transparent huge pages in KVM/ARM and KVM/ARM64. The
transparent_hugepage_adjust is not very pretty, but this is also how
it's solved on x86 and seems to be simply an artifact on how THPs
behave. This should eventually be shared across architectures if
possible, but that can always be changed down the road.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Support huge pages in KVM/ARM and KVM/ARM64. The pud_huge checking on
the unmap path may feel a bit silly as the pud_huge check is always
defined to false, but the compiler should be smart about this.
Note: This deals only with VMAs marked as huge which are allocated by
users through hugetlbfs only. Transparent huge pages can only be
detected by looking at the underlying pages (or the page tables
themselves) and this patch so far simply maps these on a page-by-page
level in the Stage-2 page tables.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
As Intel rolling out more SoC's after Moorestown, we need to
re-structure the code in a way that is backward compatible and easy to
expand. This patch implements a flexible way to support multiple boards
and devices.
This patch does not add any new functional support. It just refactors
the existing code to increase the modularity and decrease the code
duplication for supporting multiple soc's and boards.
Currently intel-mid.c has both board and soc related code in one file.
This patch moves the board related code to new files and let linker
script to create SFI devite table following this:
1. Move the SFI device specific code to
arch/x86/platform/intel-mid/device-libs/platform_<device>.*
A new device file is added for every supported device. This code will
get conditionally compiled by using corresponding device driver
CONFIG option.
2. Move the device_ids location to .x86_intel_mid_dev.init section by
using new sfi_device() macro.
This patch was based on previous code from Sathyanarayanan Kuppuswamy.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-13-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
When Intel mid uses SFI table to enumerate devices, it requires an extra
device table with further information about how to probe such devices.
This patch creates a section where the device table will stay if
CONFIG_X86_INTEL_MID is selected.
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-12-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Intel mid sfi code doesn't need struct devs_id.get_platform_data != NULL.
If the callback is not set, just assume there is no platform_data.
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-11-git-send-email-david.a.cohen@linux.intel.com
Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Moved SFI specific parsing/handling code to sfi.c. This will enable us
to reuse our intel-mid code for platforms that supports firmware
interfaces other than SFI (like ACPI).
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-10-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Added a custom handler for medfield based ipc devices and
moved devs_id structure defintion to header file.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-9-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This patch provides a means to add custom handler for
SFI devices. If you set device_handler as NULL in
device_id table standard SFI device handler will be used.
If its not NULL custom handler will be called.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-8-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
SFI device_id[] table parsing code is duplicated in every SFI
device handler. This patch removes this code duplication, by
adding a seperate function get_device_id() to parse through the
device table. Also this patch moves the SPI, I2C, IPC info code from
sfi_parse_devs() to respective device handlers.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-7-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
mrst is used as common name to represent all intel_mid type
soc's. But moorsetwon is just one of the intel_mid soc. So
renamed them to use intel_mid.
This patch mainly renames the variables and related
functions that uses *mrst* prefix with *intel_mid*.
To ensure that there are no functional changes, I have compared
the objdump of related files before and after rename and found
the only difference is symbol and name changes.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-6-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Function 'type1_access_ok' should return bool value, not 0/1.
This patch changes 'return 0/1' to 'return false/true'.
Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-5-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Following files contains code that is common to all intel mid
soc's. So renamed them as below.
mrst/mrst.c -> intel-mid/intel-mid.c
mrst/vrtc.c -> intel-mid/intel_mid_vrtc.c
mrst/early_printk_mrst.c -> intel-mid/intel_mid_vrtc.c
pci/mrst.c -> pci/intel_mid_pci.c
Also, renamed the corresponding header files and made changes
to the driver files that included these header files.
To ensure that there are no functional changes, I have compared
the objdump of renamed files before and after rename and found
that the only difference is file name change.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-4-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Fixed indentation issues reported by checkpatch script in
mrst related files.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-3-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Fixed printk and pr_* related issues in mrst related files.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-2-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
From Stephen Warren:
* tegra/dt:
ARM: tegra: Use symbolic names for gr3d clocks
ARM: tegra: Mark Tegra30 display controller compatible with Tegra20
ARM: tegra: add GPIO controller to tegra124.dtsi
ARM: tegra: enable LP1 suspend mode for Venice2
ARM: tegra: enable Tegra RTC as default for Tegra124
ARM: tegra: add Venice2 board support
ARM: tegra: Add initial device tree for Tegra124
ARM: tegra: add vcc supply for nct1008 to Cardhu
ARM: tegra: add DT entry for nct1008 to Dalmore
ARM: tegra: use dt-binding header for key code
ARM: tegra: add palmas pincontrol to Dalmore device tree
Signed-off-by: Kevin Hilman <khilman@linaro.org>
AT91 ADC hardware integrate touch screen support. So this patch add touch
screen support for at91 adc iio driver.
To enable touch screen support in adc, you need to add the dt parameters:
1. which type of touch are used? (4 or 5 wires), sample period time.
2. correct pressure detect threshold value.
In the meantime, since touch screen will use a interal period trigger of adc,
so it is conflict to other hardware triggers. Driver will disable the hardware
trigger support if touch screen is enabled.
This driver has been tested in AT91SAM9X5-EK and SAMA5D3x-EK.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
CC: devicetree@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This branch mainly removes dead code and defines that were useful only
when booting using board files. A few other misc cleanups are also
included.
This branch is based on previous pull request
tegra-for-3.13-deps-for-arm-init-time-cleanup.
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Merge tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup
ARM: tegra: cleanup for 3.13
This branch mainly removes dead code and defines that were useful only
when booting using board files. A few other misc cleanups are also
included.
This branch is based on previous pull request
tegra-for-3.13-deps-for-arm-init-time-cleanup.
* tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
ARM: tegra: make tegra_init_fuse() __init
ARM: tegra: remove much of iomap.h
ARM: tegra: move resume vector define to irammap.h
ARM: tegra: delete gpio-names.h
ARM: tegra: delete stale header content
ARM: tegra: remove common.c
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- convert Calxeda cpuidle driver to a platform driver and to use PSCI
- convert highbank smp_ops and suspend to PSCI
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Merge tag 'highbank-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next/soc
From Rob Herring:
Highbank platform updates for 3.13
- convert Calxeda cpuidle driver to a platform driver and to use PSCI
- convert highbank smp_ops and suspend to PSCI
* tag 'highbank-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dts: calxeda: add ARM PSCI binding
ARM: highbank: adapt to use ARM PSCI calls
ARM: PSCI: remove unnecessary include of arm-gic.h
cpuidle: calxeda: add support to use PSCI calls
ARM: highbank: cpuidle: convert to platform driver
cpuidle: calxeda: add cpu_pm_enter/exit calls
Vasant Hegde