The plat-orion GPIO driver would disable any pin blinking whenever
using a pin for output. Do the same here, as a blinking LED will
continue to blink regardless of what the GPIO pin level is.
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Fix a potential bit wrap issue in the Timberdale driver
- Fix up the buffer allocation size in the 74x164 driver
- Set the value in direction_output() right in the mvebu driver
- Return proper error codes for invalid GPIOs
- Fix an off-mode bug for the OMAP
- Don't initialized the mask_cach on the mvebu driver
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Merge tag 'gpio-fixes-v3.7-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO fixes from Linus Walleij:
- Fix a potential bit wrap issue in the Timberdale driver
- Fix up the buffer allocation size in the 74x164 driver
- Set the value in direction_output() right in the mvebu driver
- Return proper error codes for invalid GPIOs
- Fix an off-mode bug for the OMAP
- Don't initialize the mask_cach on the mvebu driver
* tag 'gpio-fixes-v3.7-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
GPIO: mvebu-gpio: Don't initialize the mask_cache
gpio/omap: fix off-mode bug: clear debounce settings on free/reset
gpiolib: Don't return -EPROBE_DEFER to sysfs, or for invalid gpios
gpio: mvebu: correctly set the value in direction_output()
gpio-74x164: Fix buffer allocation size
gpio-timberdale: fix a potential wrapping issue
Due to the SMP nature of some of the chips, which have per CPU
registers, the driver does not use the generic irq_gc_mask_set_bit() &
irq_gc_mask_clr_bit() functions, which only support a single register.
The driver has its own implementation of these functions, which can
pick the correct register depending on the CPU being used. The
functions do however use the gc->mask_cache value.
The call to irq_setup_generic_chip() was passing
IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
initialized to the contents of some random register. This resulted in
unexpected interrupts been delivered from random GPIO lines.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jamie Lentin <jm@lentin.co.uk>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ->direction_output() operation of gpio_chip is supposed to set the
direction to output but also to set the GPIO to an initial
value. Unfortunately, this last part was not done until now, causing
for example the LEDs to not be properly set to their default initial
value. This patch fixes this by calling the mvebu_gpio_set() function
from mvebu_gpio_direction_output() before configuring the GPIO as an
output GPIO.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This driver aims at replacing the arch/arm/plat-orion/gpio.c driver,
and is designed to be compatible with all Marvell EBU SoCs: Orion,
Kirkwood, Dove, Armada 370/XP and Discovery.
It has been successfully tested on Dove and Armada XP at the moment.
Compared to the plat-orion driver, this new driver has the following
added benefits:
*) Support for Armada 370 and Armada XP
*) It is integrated with the mvebu pinctrl driver so that GPIO pins
are properly muxed, and the GPIO driver knows which GPIO pins are
output-only or input-only.
*) Properly placed in drivers/gpio
*) More extensible mechanism to support platform differences. The
plat-orion driver uses a simple mask-offset DT property, which
works fine for Discovery MV78200 but not for Armada XP. The new
driver uses different compatible strings to identify the different
variants of the GPIO controllers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Jamie Lentin