Commit Graph

96 Commits

Author SHA1 Message Date
Steve Longerbeam cd98e85a6b gpu: ipu-v3: Add queued image conversion support
This patch implements image conversion support using the IC tasks, with
tiling to support scaling to and from images up to 4096x4096. Image
rotation is also supported. Image conversion requests are added to
a run queue under the IC tasks.

The internal API is subsystem agnostic (no V4L2 dependency except
for the use of V4L2 fourcc pixel formats).

Callers prepare for image conversion by calling
ipu_image_convert_prepare(), which initializes the parameters of
the conversion. The caller passes in the ipu and IC task to use for
the conversion, the input and output image formats, a rotation mode,
and a completion callback and completion context pointer:

struct ipu_image_converter_ctx *
ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
                          struct ipu_image *in, struct ipu_image *out,
                          enum ipu_rotate_mode rot_mode,
                          ipu_image_converter_cb_t complete,
                          void *complete_context);

A new conversion context is created that is added to an IC task
context queue. The caller is given the new conversion context,
which can then be passed to the further APIs:

int ipu_image_convert_queue(struct ipu_image_converter_run *run);

This queues the given image conversion request run to a run queue,
and starts the conversion immediately if the run queue is empty. Only
the physaddr's of the input and output image buffers are needed,
since the conversion context was created previously with
ipu_image_convert_prepare(). When the conversion completes, the run
pointer is returned to the completion callback.

void ipu_image_convert_abort(struct ipu_image_converter_ctx *ctx);

This will abort any active or pending conversions for this context.
Any currently active or pending runs belonging to this context are
returned via the completion callback with an error status.

void ipu_image_convert_unprepare(struct ipu_image_converter_ctx *ctx);

Unprepares the conversion context. Any active or pending runs will
be aborted by calling ipu_image_convert_abort().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-09-19 08:30:27 +02:00
Steve Longerbeam 8b9c3d5099 gpu: ipu-v3: Add ipu_rot_mode_is_irt()
Add a macro that returns boolean true if the given ipu_rotate_mode
requires the use of the Image Rotator.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-09-19 08:30:14 +02:00
LABBE Corentin e92e447877 gpu: ipu-v3: fix a possible NULL dereference
of_match_device could return NULL, and so cause a NULL pointer
dereference later.

For fixing this problem, we use of_device_get_match_data(), this will
simplify the code a little by using a standard function for
getting the match data.

Testing the return value of of_device_get_match_data is also necessary
for avoiding a second NULL deref later on devtype.

Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-09-19 08:30:10 +02:00
Steve Longerbeam ac4708fab1 gpu: ipu-v3: Add FSU channel linking support
Adds functions to link and unlink source channels to sink
channels in the FSU:

int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);

The channels numbers are usually IDMAC channels, but they can also be
channels that do not transfer data to or from memory. The following
convenience functions can be used in place of ipu_fsu_link/unlink()
when both source and sink channels are IDMAC channels:

int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);

So far the following links are supported:

IPUV3_CHANNEL_IC_PRP_ENC_MEM -> IPUV3_CHANNEL_MEM_ROT_ENC
PUV3_CHANNEL_IC_PRP_VF_MEM   -> IPUV3_CHANNEL_MEM_ROT_VF
IPUV3_CHANNEL_IC_PP_MEM      -> IPUV3_CHANNEL_MEM_ROT_PP
IPUV3_CHANNEL_CSI_DIRECT     -> IPUV3_CHANNEL_CSI_VDI_PREV

More links can be added to the fsu_link_info[] array.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-29 16:30:23 +02:00
Steve Longerbeam 2d2ead4530 gpu: ipu-v3: Add Video Deinterlacer unit
Adds the Video Deinterlacer (VDIC) unit.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-29 16:30:11 +02:00
Liu Ying 448ae8ea39 gpu: ipu-v3: Do not wait for DMFC FIFO to clear when disabling DMFC channel
According to basic tests, it looks there is no issue if we don't wait for
DMFC FIFO to clear when disabling DMFC channel.  NXP BSP doesn't do that,
either.  This patch is needed to avoid the annoying warning caused by a
timeout on waiting for the FIFO to clear after we add the new
DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET flag to the imx-drm driver
which changes the procedure to disable display channel slightly.

Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: David Airlie <airlied@linux.ie>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Peter Senna Tschudin <peter.senna@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-29 12:45:05 +02:00
Steve Longerbeam 88287ec3f8 gpu: ipu-v3: rename CSI client device
Rename the CSI client device in the client_reg[] table to
"imx-ipuv3-csi".

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08 11:44:20 +02:00
Steve Longerbeam 58e366eb86 gpu: ipu-v3: Fix IRT usage
There can be multiple IC tasks using the IRT, so the IRT needs
a separate use counter. Create a private ipu_irt_enable() to
enable the IRT module when any IC task requires rotation, and
ipu_irt_disable() when a task no longer needs the IRT.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08 11:44:20 +02:00
Steve Longerbeam ea6bead7eb gpu: ipu-v3: Fix CSI data format for 16-bit media bus formats
The CSI data format was being programmed incorrectly for the
1x16 media bus formats. The CSI data format for 16-bit must
be bayer/generic (CSI_SENS_CONF_DATA_FMT_BAYER).

Suggested-by: Carsten Resch <Carsten.Resch@de.bosch.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08 11:44:20 +02:00
Steve Longerbeam aede45b2f6 gpu: ipu-v3: set correct full sensor frame for PAL/NTSC
Set the sensor full frame based on whether the passed in mbus_fmt
is 720x480 (NTSC) or 720x576 (PAL).

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08 11:44:20 +02:00
Steve Longerbeam 572a7615ae gpu: ipu-v3: Add ipu_get_num()
Adds of-alias id to ipu_soc and retrieve with ipu_get_num().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08 11:44:20 +02:00
Steve Longerbeam 03085911d7 gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
Adds ipu_cpmem_get_burstsize().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08 11:44:20 +02:00
Steve Longerbeam e5e8690ff0 gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08 11:44:20 +02:00
Philipp Zabel b575b31387 gpu: ipu-v3: ipu-dc: don't bug out on invalid bus_format
If imx-drm is combined with a bridge or panel that requests an
unsupported format, warn and use a default mapping instead of
hanging the machine. The worst that can happen here are wrong
colors.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-12 18:26:05 +02:00
Liu Ying 33f1423530 drm/imx: atomic phase 1: Use transitional atomic CRTC and plane helpers
Use the drm_plane_helper_update/disable() and drm_helper_crtc_mode_set()
transitional atomic helpers.  The crtc->mode_set_nofb callback is added
so that the primary plane is no longer tied to the CRTC.  Check/update
logics are separated to make sure crtc->mode_set_nofb and plane->atomic_update
are always successful.  Also, some necessary logics are tweaked for a smooth
transition.

Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-12 18:23:47 +02:00
Liu Ying d7868cb7ac gpu: ipu-v3: ipu-dmfc: Use static DMFC FIFO allocation mechanism
For all video modes we support currently, we always get 2 slots for
a plane by using the current existing dynamic DMFC FIFO allocation
mechanism.  So, let's change to use the static one to simplify the
code.  This also makes it easier to implement the atomic mode setting
as we don't need to handle allocation failure cases then.

Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-12 18:23:43 +02:00
Philipp Zabel 310944d148 drm/imx: Match imx-ipuv3-crtc components using device node in platform data
The component master driver imx-drm-core matches component devices using
their of_node. Since commit 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc
module autoloading"), the imx-ipuv3-crtc dev->of_node is not set during
probing. Before that, of_node was set and caused an of: modalias to be
used instead of the platform: modalias, which broke module autoloading.

On the other hand, if dev->of_node is not set yet when the imx-ipuv3-crtc
probe function calls component_add, component matching in imx-drm-core
fails. While dev->of_node will be set once the next component tries to
bring up the component master, imx-drm-core component binding will never
succeed if one of the crtc devices is probed last.

Add of_node to the component platform data and match against the
pdata->of_node instead of dev->of_node in imx-drm-core to work around
this problem.

Cc: <stable@vger.kernel.org> # 4.4.x
Fixes: 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
2016-05-23 12:35:11 +02:00
Philipp Zabel 503fe87bd0 gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading
If of_node is set before calling platform_device_add, the driver core
will try to use of: modalias matching, which fails because the device
tree nodes don't have a compatible property set. This patch fixes
imx-ipuv3-crtc module autoloading by setting the of_node property only
after the platform modalias is set.

Fixes: 304e6be652 ("gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports")
Reported-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-By: Dennis Gilmore <dennis@ausil.us>
Cc: stable@vger.kernel.org # 4.4+
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-05-05 10:34:52 +10:00
Liu Ying 27630c206b gpu: ipu-v3: ipu-dmfc: Rename ipu_dmfc_init_channel to ipu_dmfc_config_wait4eot
The function name 'ipu_dmfc_config_wait4eot' matches the implementation of
the function better than 'ipu_dmfc_init_channel', since it only touches the
wait4eot bits.

Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-31 11:24:33 +02:00
Liu Ying 2bbe32f739 gpu: ipu-v3: ipu-dmfc: Make function ipu_dmfc_init_channel() return void
Since the function ipu_dmfc_init_channel() always returns zero, we may
change the return type to void to simplify the code.

Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-31 11:24:31 +02:00
Liu Ying 32c26a56af gpu: ipu-v3: ipu-dmfc: Protect function ipu_dmfc_init_channel() with mutex
To avoid race condition issue, we should protect the function
ipu_dmfc_init_channel() with the mutex dmfc->priv->mutex, since it
configures the register DMFC_GENERAL1 at runtime which contains
several control bits for various display channels.  This matches
better with fine grained locking logic in upper layer.

Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-31 11:24:30 +02:00
Philipp Zabel 90195c3651 gpu: ipu-cpmem: modify ipu_cpmem_set_yuv_planar_full for better control
Let ipu_cpmem_set_yuv_planar_full take a DRM_FORMAT instead of a
V4L2_PIXFMT and allow better control over U/V stride, U offset and
V offset settings in the CPMEM.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-31 11:23:29 +02:00
Dave Airlie 9b61c0fcdf Merge drm-fixes into drm-next.
Nouveau wanted this to avoid some worse conflicts when I merge that.
2016-03-14 09:46:02 +10:00
Philipp Zabel 86bdb09f04 gpu: ipu-v3: ipu-dc: Simplify display controller microcode setup
This cleans up the display controller microcode setup in ipu_dc_init_sync
a little bit. The microcode template words for DI0 and DI1 are properly
separated to avoid a clash when DI1 is active in interlaced mode at the
same time as DI0 in non-interlaced mode.
A comment is added to explain the meaning of the sync counter.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01 08:33:38 +01:00
David Jander 596a65d152 gpu: ipu-v3: Reset IPU before activating IRQ
If we don't come out of a clean reset, make sure no IRQ is fired before
everything is setup by resetting the IPU before activating the interrupt
handlers.

Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-02-10 14:26:51 +01:00
Philipp Zabel 17e0521750 gpu: ipu-v3: Do not bail out on missing optional port nodes
The port nodes are documented as optional, treat them accordingly.

Reported-by: Martin Fuzzey <mfuzzey@parkeon.com>
Reported-by: Chris Healy <Chris.Healy@zii.aero>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Fixes: 304e6be652 ("gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports")
2016-02-10 14:26:50 +01:00
Mauro Carvalho Chehab c3152592e7 Merge branch 'patchwork' into v4l_for_linus
* patchwork: (204 commits)
  [media] rc: sunxi-cir: Initialize the spinlock properly
  [media] rtl2832: do not filter out slave TS null packets
  [media] rtl2832: print reg number on error case
  [media] rtl28xxu: return demod reg page from driver cache
  [media] coda: enable MPEG-2 ES decoding
  [media] coda: don't start streaming without queued buffers
  [media] coda: hook up vidioc_prepare_buf
  [media] coda: relax coda_jpeg_check_buffer for trailing bytes
  [media] coda: make to_coda_video_device static
  [media] s5p-mfc: remove volatile attribute from MFC register addresses
  [media] s5p-mfc: merge together s5p_mfc_hw_call and s5p_mfc_hw_call_void
  [media] s5p-mfc: use spinlock to protect MFC context
  [media] s5p-mfc: remove unnecessary callbacks
  [media] s5p-mfc: make queue cleanup code common
  [media] s5p-mfc: use one implementation of s5p_mfc_get_new_ctx
  [media] s5p-mfc: constify s5p_mfc_codec_ops structures
  [media] au8522: Avoid memory leak for device config data
  [media] ir-lirc-codec.c: don't leak lirc->drv-rbuf
  [media] uvcvideo: small cleanup in uvc_video_clock_update()
  [media] uvcvideo: Fix reading the current exposure value of UVC
  ...
2016-01-11 11:13:27 -02:00
Mauro Carvalho Chehab 4a3d0cb06b drm, ipu-v3: use https://linuxtv.org for LinuxTV URL
While https was always supported on linuxtv.org, only in
Dec 3 2015 the website is using valid certificates.

As we're planning to drop pure http support on some
future, change the references at DRM include and at
the ipu-v3 driver to point to the https://linuxtv.org
URL instead.

Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
2015-12-04 10:37:57 -02:00
Philipp Zabel 304e6be652 gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports
The crtc child device driver shouldn't have to modify the of_node of its
platform device in the probe function. Instead, let the IPU core driver
set the of_node when the platform device is created.

Also reorder the client_reg array so the elements are in port id order
(CSIs first, then DIs).

Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-11-24 11:30:17 +01:00
Philipp Zabel 99ae78c373 gpu: ipu-v3: Remove reg_offset field
This is not used, so remove it.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-11-24 11:30:16 +01:00
Dave Airlie cb0fb27121 imx-drm fixes and color format updates
- Some correctness fixes found by coccinelle
 - Add drivers/gpu/ipu-v3 directory to MAINTAINERS
 - Add support for more color formats
 - Fix a regression, making displays larger than FullHD work again
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Merge tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux into drm-next

imx-drm fixes and color format updates

- Some correctness fixes found by coccinelle
- Add drivers/gpu/ipu-v3 directory to MAINTAINERS
- Add support for more color formats
- Fix a regression, making displays larger than FullHD work again

* tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux:
  drm/imx: hdmi: fix HDMI setup to allow modes larger than FullHD
  gpu: ipu-v3: fix div_ratio type
  gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors.
  drm/imx: enable ARGB4444 16-bit color format
  gpu: ipu-v3: add support for ARGB4444 16-bit color format
  drm/imx: ipuv3-plane: enable support for RGBX8888 and RGBA8888 pixel formats
  gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formats
  drm/imx: enable 15-bit RGB with 1-bit alpha formats
  gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formats
  MAINTAINERS: Add IPUv3 core driver to the i.MX DRM driver section
  gpu: ipu-v3: ipu-csi: bool test doesn't need a comparison to false
2015-11-05 11:06:56 +10:00
Andrzej Hajda 9b6d0d33c8 gpu: ipu-v3: fix div_ratio type
The variable can be negative.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Philippe De Muyter 3e8b2246c3 gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors.
Enable the MEDIA_BUS_FMT_Y8_1X8 format.

Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Lucas Stach 7d2e8a204a gpu: ipu-v3: add support for ARGB4444 16-bit color format
This patch adds support for the ARGB4444 color format.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Philipp Zabel 067f4aa402 gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formats
This patch adds support for the RGBA8888, RGBX8888, BGRA8888, and
BGRX8888 in-memory formats.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Philipp Zabel 0cb8b75792 gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formats
This patch adds support for ARGB1555, ABGR1555, RGBA5551, and BGRA5551
in-memory formats.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Fabio Estevam 6dd0d0e1ae gpu: ipu-v3: ipu-csi: bool test doesn't need a comparison to false
Bool initializations should use true and false. Bool tests don't need
comparisons. Based on contributions from Joe Perches, Rusty Russell
and Bruce W Allan.

The semantic patch that makes this change is available
in scripts/coccinelle/misc/boolinit.cocci.

More information about semantic patching is available at
http://coccinelle.lip6.fr/

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30 17:13:47 +01:00
Russell King aefa627fa3 gpu: imx: fix support for interlaced modes
The support for interlaced video modes seems to be broken; we don't use
anything other than the vtotal/htotal from the timing information to
define the various sync counters.

Freescale patches for interlaced video support contain an alternative
sync counter setup, which we include here.  This setup produces the
hsync and vsync via the normal counter 2 and 3, but moves the display
enable signal from counter 5 to counter 6.  Therefore, we need to
change the display controller setup as well.

The corresponding Freescale patches for this change are:
  iMX6-HDMI-support-interlaced-display-mode.patch
  IPU-fine-tuning-the-interlace-display-timing-for-CEA.patch

This produces a working interlace format output from the IPU.

Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-10-06 19:58:30 +01:00
Russell King f94ab604db gpu: imx: simplify sync polarity setting
Use a function to convert the sync pin to a bit mask for the DI_GENERAL
register, and move this out of the interlace/non-interlace path to the
common path.

Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-10-06 19:58:21 +01:00
Rob Herring ca0141de74 gpu/drm: Kill off set_irq_flags usage
set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-09-16 16:53:38 +02:00
Thomas Gleixner bd0b9ac405 genirq: Remove irq argument from irq flow handlers
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.

Remove the argument.

Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
2015-09-16 15:47:51 +02:00
Linus Torvalds 3527122745 dmaengine updates for 4.3-rc1
This time we have aded a new capability for  scatter-gathered memset using
 dmaengine APIs. This is supported in xdmac & hdmac drivers
 
 We have added support for reusing descriptors for examples like video
 buffers etc. Driver will follow
 
 The behaviour of descriptor ack has been clarified and documented
 
 New devices added are:
 - dma controller in sun[457]i SoCs
 - lpc18xx dmamux
 - ZTE ZX296702 dma controller
 - Analog Devices AXI-DMAC DMA controller
 - eDMA support for dma-crossbar
 - imx6sx support in imx-sdma driver
 - imx-sdma device to device support
 
 Others
 - jz4780 fixes
 - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is
   deprecated and fixes
 - ACPI support in X-Gene DMA engine driver
 - ipu irq fixes
 - mvxor fixes
 - minor fixes spread thru drivers
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Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "This time we have aded a new capability for scatter-gathered memset
  using dmaengine APIs.  This is supported in xdmac & hdmac drivers

  We have added support for reusing descriptors for examples like video
  buffers etc.  Driver will follow

  The behaviour of descriptor ack has been clarified and documented

  New devices added are:
   - dma controller in sun[457]i SoCs
   - lpc18xx dmamux
   - ZTE ZX296702 dma controller
   - Analog Devices AXI-DMAC DMA controller
   - eDMA support for dma-crossbar
   - imx6sx support in imx-sdma driver
   - imx-sdma device to device support

  Other:
   - jz4780 fixes
   - ioatdma large refactor and cleanup for removal of ioat v1 and v2
     which is deprecated and fixes
   - ACPI support in X-Gene DMA engine driver
   - ipu irq fixes
   - mvxor fixes
   - minor fixes spread thru drivers"

[ The Kconfig and Makefile entries got re-sorted alphabetically, and I
  handled the conflict with the new Intel integrated IDMA driver by
  slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in
  order to keep the Intel entries together.  I think it might be a good
  idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make
  the sorting be a true sort, not this mismash.

  Also, this merge disables the COMPILE_TEST for the sun4i DMA
  controller, because it does not compile cleanly at all.     - Linus ]

* tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits)
  dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs
  dmaengine :ipu: change ipu_irq_handler() to remove compile warning
  dmaengine: ioatdma: Fix variable array length
  dmaengine: ioatdma: fix sparse "error" with prep lock
  dmaengine: hdmac: Add memset capabilities
  dmaengine: sort the sh Makefile
  dmaengine: sort the sh Kconfig
  dmaengine: sort the dw Kconfig
  dmaengine: sort the Kconfig
  dmaengine: sort the makefile
  drivers/dma: make mv_xor.c driver explicitly non-modular
  dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller
  devicetree: Add bindings documentation for Analog Devices AXI-DMAC
  dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests
  dmaengine: ioatdma: fix coccinelle warning
  dmaengine: ioatdma: fix zero day warning on incompatible pointer type
  dmaengine: tegra-apb: Simplify locking for device using global pause
  dmaengine: tegra-apb: Remove unnecessary return statements and variables
  dmaengine: tegra-apb: Avoid unnecessary channel base address calculation
  dmaengine: tegra-apb: Remove unused variables
  ...
2015-09-04 11:10:18 -07:00
Jiang Liu 4d9efdfce7 dmaengine: ipu: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.

This is also a preparation for the removal of the 'irq' argument from
interrupt flow handlers.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: dmaengine@vger.kernel.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-07-16 18:41:18 +05:30
Russell King 510e6426d3 GPU: ipu: fix lockup caused by pending chained interrupts
Even with the oops fixed by a previous patch, the system still fails to
kexec, due to a stuck chained interrupt locking the system.  We must
disable the child interrupts prior to setting up the irq chip to ensure
we don't get stuck here.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-07-10 11:02:46 +02:00
Russell King 86f5e73304 GPU: ipu: Fix race in installing IPU chained IRQ handler
The IPU code was installing its chained interrupt handler (which enables
the interrupt) before it was setting its data, which provokes an oops on
kexec.  Fix this by converting to irq_set_chained_handler_and_data().

[drm] Initialized drm 1.1.0 20060810
imx-drm display-subsystem: parent device of /soc/aips-bus@02000000/ldb@020e0008/lvds-channel@1 is not available
imx-drm display-subsystem: parent device of /soc/aips-bus@02000000/ldb@020e0008/lvds-channel@1 is not available
Unable to handle kernel NULL pointer dereference at virtual address 00000070
pgd = c0004000
[00000070] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.1.0-rc6+ #1693
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
task: d74c0000 ti: d74aa000 task.ti: d74aa000
PC is at ipu_irq_handle+0x28/0xd8
LR is at ipu_irq_handler+0x6c/0xc0
pc : [<c03c56d8>]    lr : [<c03c58a4>]    psr: 200001d3
sp : d74abbd0  ip : d74abc00  fp : d74abbfc
r10: 000001e0  r9 : c0085154  r8 : 00000009
r7 : 00000000  r6 : 00000000  r5 : d74abc04  r4 : c0a6b6a8
r3 : 00000000  r2 : 00000009  r1 : d74abc04  r0 : 00000000
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 10004059  DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xd74aa210)
Stack: (0xd74abbd0 to 0xd74ac000)
Backtrace:
[<c03c56b0>] (ipu_irq_handle) from [<c03c58a4>] (ipu_irq_handler+0x6c/0xc0)
[<c03c5838>] (ipu_irq_handler) from [<c0080154>] (generic_handle_irq+0x28/0x38)
[<c008012c>] (generic_handle_irq) from [<c0080288>] (__handle_domain_irq+0x5c/0xb8)
[<c008022c>] (__handle_domain_irq) from [<c0009428>] (gic_handle_irq+0x28/0x68)
[<c0009400>] (gic_handle_irq) from [<c0013dc4>] (__irq_svc+0x44/0x5c)
[<c07638fc>] (_raw_spin_unlock_irqrestore) from [<c00803bc>] (__irq_put_desc_unlock+0x1c/0x40)
[<c00803a0>] (__irq_put_desc_unlock) from [<c00841f4>] (__irq_set_handler+0x54/0x5c)
[<c00841a0>] (__irq_set_handler) from [<c03c5f48>] (ipu_probe+0x29c/0x708)
[<c03c5cac>] (ipu_probe) from [<c03d3848>] (platform_drv_probe+0x50/0xac)
[<c03d37f8>] (platform_drv_probe) from [<c03d1f3c>] (driver_probe_device+0x1d4/0x278)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/E1Z4z02-0002SI-Br@rmk-PC.arm.linux.org.uk
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-18 14:03:08 +02:00
Dave Airlie 1d2add28ed imx-drm changes to use media bus formats and LDB drm_panel support
- Add media bus formats needed by imx-drm
 - Switch to use media bus formats to describe the pixel format
   on the internal parallel bus between display interface and
   encoders
 - Some preparations for TV Output via TVEv2 on i.MX5
 - Add drm_panel support to the i.MX LVDS driver, allow to
   determine the bus pixel format from the panel descriptor.
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Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next

imx-drm changes to use media bus formats and LDB drm_panel support

- Add media bus formats needed by imx-drm
- Switch to use media bus formats to describe the pixel format
  on the internal parallel bus between display interface and
  encoders
- Some preparations for TV Output via TVEv2 on i.MX5
- Add drm_panel support to the i.MX LVDS driver, allow to
  determine the bus pixel format from the panel descriptor.

* tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux:
  drm/imx: imx-ldb: allow to determine bus format from the connected panel
  drm/imx: imx-ldb: reset display clock input when disabling LVDS
  drm/imx: imx-ldb: add drm_panel support
  drm/imx: consolidate bus format variable names
  drm/imx: switch to use media bus formats
  Add RGB666_1X24_CPADHI media bus format
  Add YUV8_1X24 media bus format
  Add BGR888_1X24 and GBR888_1X24 media bus formats
  Add LVDS RGB media bus formats
  Add RGB444_1X12 and RGB565_1X16 media bus formats
  drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2
  drm/imx: Add support for interlaced scanout
2015-04-13 17:28:57 +10:00
Philipp Zabel 8f361b279f gpu: ipu-v3: turns out the IPU can only downsize 4:1
The value for downsizing 8:1 is marked as reserved in the technical reference
manual and the documentation states downsizing capability up to 4:1 only.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-03-31 12:03:55 +02:00
Philipp Zabel f7089d923e gpu: ipu-v3: limit pixel clock divider to 8-bits
The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.

Reported-by: Felix Mellmann <felix.mellmann@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-03-31 12:03:54 +02:00
Philipp Zabel 2872c8072a drm/imx: consolidate bus format variable names
This patch consolidates the different interface_pix_fmt, pixel_fmt, pix_fmt,
and pixfmt variables to a common name "bus_format" wherever they describe the
pixel format on the bus between display controller and encoder hardware.
At the same time, it renames imx_drm_panel_format to imx_drm_set_bus_format.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Emil Renner Berthing <kernel@esmil.dk>
2015-03-31 11:59:34 +02:00
Philipp Zabel a7c6e76fee drm/imx: switch to use media bus formats
imx-drm internally misused the V4L2_PIX_FMT constants, which are supposed to
describe the pixel format of frame buffers in memory, to describe the pixel
format on the bus between the display controller and the encoder hardware.
Now that MEDIA_BUS_FMT constants are available to drm drivers, use those
instead.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Emil Renner Berthing <kernel@esmil.dk>
2015-03-31 11:59:34 +02:00