Commit Graph

155 Commits

Author SHA1 Message Date
Helmut Schaa 41842dc1f0 ath9k: Fix symbol overlap window for half/quarter channels
Since commit cd6cfd7311
"ath9k: do not set half/quarter channel flags in AR_PHY_MODE" the
condition "rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF)" would
never evaluate to true.

Fix this by using the available IS_CHAN_HALF_RATE and IS_CHAN_QUARTER_RATE
marcros instead.

Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
Cc: Felix Fietkau <nbd@openwrt.org>
Acked-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-05-09 21:12:01 +03:00
Helmut Schaa b0291715d3 ath9k: Simplify ar9003_hw_tx99_set_txpower
There's no need to keep the same for loop twice in the code.
Move the txpower cap before the loop to reduce code complexity.

Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-05-09 20:46:51 +03:00
Helmut Schaa 8569f59154 ath9k: reuse ar9003_hw_tx_power_regwrite for tx99 setup
The same functionality as ar9003_hw_tx_power_regwrite is hardcoded in
ar9003_hw_tx99_set_txpower. Just reuse the existing ar9003_hw_tx_power_regwrite
for TX99 setup too.

Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-05-09 20:46:31 +03:00
Bob Copeland 1451a3634f ath9k: fix a misleading indentation
These lines belong inside the if-statement above, not in the
main body of the switch.

Found by smatch.

Signed-off-by: Bob Copeland <me@bobcopeland.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-03-11 14:00:01 +02:00
Miaoqing Pan 25c0f30142 ath9k: clear bb filter calibration power threshold
JP WiFi certification for bandwidth of channel 14 failed, the OBW
is lower than the requirement. Clear the bb filter calibration power
threshold to increase OBW(+2). The fix only for qca9531 chip now.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-03-03 19:27:17 +02:00
Miaoqing Pan 3f6cc4e57d ath9k: do not reset while BB panic(0x4000409) on ar9561
BB panic(0x4000409) observed while AP enabling/disabling
bursting.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-01-26 16:47:38 +02:00
Miaoqing Pan cfa2b42b4d ath9k: fix QCA9561 XLNA rxgain initial
A small bugfix for commit ede6a5e7b8 ("ath9k: Add QCA956x HW support").
I guess I would have skipped renaming (that initial QCA956x commit has
been there already for almost a year with the "5g" in the name) and move
the call outside AR_SREV_9462_20_OR_LATER() to make it reachable.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-10-14 14:15:57 +03:00
Miaoqing Pan 871d0051f0 ath9k: rename ini_modes_rxgain_5g_xlna to ini_modes_rxgain_xlna
rename the variable as preparation for using the array with 2.4 GHz
band, etc.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-10-14 14:15:55 +03:00
Miaoqing Pan ede6a5e7b8 ath9k: Add QCA956x HW support
Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-15 14:25:03 +02:00
Lorenzo Bianconi 23f53dd306 ath9k: add TX power per-rate tables
Add TX power per-rate tables for different MIMO modes (e.g STBC) in order to
cap the maximum TX power value per-rate in the TX descriptor path.
Cap TX power for self generated frames (ACK, RTS/CTS).
Currently TPC is supported just by AR9003 based chips

Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-11-25 14:09:56 -05:00
John W. Linville ab1f5a532c Merge commit '4e6ce4dc7ce71d0886908d55129d5d6482a27ff9' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless 2014-11-19 15:38:48 -05:00
Miaoqing Pan 4e6ce4dc7c ath9k: Fix RTC_DERIVED_CLK usage
Based on the reference clock, which could be 25MHz or 40MHz,
AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
But, when a chip reset is done, processing the initvals
sets the register back to the default value.

Fix this by moving the code in ath9k_hw_init_pll() to
ar9003_hw_override_ini(). Also, do this override for AR9531.

Cc: stable@vger.kernel.org
Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-11-11 16:24:18 -05:00
Lorenzo Bianconi edad187380 ath9k: set pulse_rssi threshold to 15
Reduce pulse_rssi threshold to 15 in order to improve radar pattern detection
probability on ext channel

Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-10-30 15:24:49 -04:00
Lorenzo Bianconi 992a36a641 ath9k: do not overwrite AR_PHY_RADAR_1 MSB
Do not overwrite AR_PHY_RADAR_1 most significant byte default value

Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-10-27 14:16:14 -04:00
Felix Fietkau 5fb9b1b949 ath9k_hw: fix PLL clock initialization for newer SoC
On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL
register changed. This currently breaks at least 5/10 MHz operation.
AR933x uses the old layout.

It might also have been causing other stability issues because of the
different location of the PLL_BYPASS bit which needs to be set during
PLL clock initialization.

This patch also removes more instances of hardcoded register values in
favor of properly computed ones with the PLL_BYPASS bit added.

Reported-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-30 13:17:47 -04:00
Rajkumar Manoharan af2db44485 ath9k_hw: fix tx gain table index for AR953x
Fix tx gain table index on fast channel change for AR953x.

Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-06-25 15:40:38 -04:00
Felix Fietkau cd6cfd7311 ath9k: do not set half/quarter channel flags in AR_PHY_MODE
5/10 MHz channel bandwidth is configured via the PLL clock, instead of
the AR_PHY_MODE register. Using that register is AR93xx specific, and
makes the mode incompatible with earlier chipsets.

In some early versions, these flags were apparently applied at the wrong
point in time and thus did not cause connectivity issues, however now
they are causing problems, as pointed out in this OpenWrt ticket:

https://dev.openwrt.org/ticket/14916

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-02-24 15:38:38 -05:00
Sujith Manoharan 2c323058bc ath9k: Add hardware support for QCA9531
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-01-03 15:37:01 -05:00
Sujith Manoharan d88527d3d3 ath9k: Identify baseband watchdog signatures
A full HW reset is not required for all baseband watchdog
signatures. Some BB watchdog updates are benign and can
be discarded, some require re-programming of certain registers
and others require a chip reset.

This patch adds a routine to identify such signatures.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-01-03 15:36:57 -05:00
Sujith Manoharan a7abaf7da9 ath9k: Fix PHY restart workaround
The PHY restart workaround that handles baseband hangs
for packets with unsupported rates is required only
for a HW bug in AR9300 v2.2. All the subsequent chips in
the AR9003 family do not require this driver fix since
it has been addressed in the HW.

Since the value of the AR_PHY_RESTART register is written
with the default initvals, make sure that PHY restart is
always disabled once this particular BB hang signaure has
been encountered.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-01-03 15:36:57 -05:00
Sujith Manoharan 4a878b9f89 ath9k: Initialize baseband for DFS channels
Certain baseband registers require different values
to be programmed when operating in a DFS channel to
ensure that radar detection works correctly. This
is required for AR9300, AR9340 and AR9580.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-12-09 15:37:56 -05:00
Sujith Manoharan 34d9b68934 ath9k: Fix Carrier Leak calibration for SoC chips
CL calibration is applicable for all chips and the
enable/disable knob comes via the INI file. For PCOEM
chips, the calibration data is reused when Fast Channel Change
is used. Caldata reuse is not enabled for SoC chips, so remove
the CL post processing code.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-12-02 14:24:58 -05:00
Sujith Manoharan 6fcbe538be ath9k: Fix issue with MCS15
On some boards which are based on AR9300, AR9580 or
AR9550, MCS15 usage is problematic.

This is because these boards use a "frequency doubler",
which doubles the refclk to get better EVM, but causes
spurs. Handle this properly in the driver to recover
throughput.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-11-15 14:27:26 -05:00
Luis R. Rodriguez 89f927af7f ath9k: add TX99 support
TX99 support enables Specific Absorption Rate (SAR) testing.
SAR is the unit of measurement for the amount of radio frequency(RF)
absorbed by the body when using a wireless device. The RF
exposure limits used are expressed in the terms of SAR, which is a
measure of the electric and magnetic field strength and power density
for transmitters operating at frequencies from 300 kHz to 100 GHz.

Regulatory bodies around the world require that wireless device
be evaluated to meet the RF exposure limits set forth in the
governmental SAR regulations.

In the examples below, for more bit rate options see the iw TX bitrate
setting documentation:

http://wireless.kernel.org/en/users/Documentation/iw#Modifying_transmit_bitrates

Example usage:

iw phy phy0 interface add moni0 type monitor
ip link set dev moni0 up

iw dev moni0 set channel 36 HT40+
iw set bitrates mcs-5 4

echo 10 > /sys/kernel/debug/ieee80211/phy0/ath9k/tx99_power
echo 1  > /sys/kernel/debug/ieee80211/phy0/ath9k/tx99

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@do-not-panic.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-10-18 14:06:56 -04:00
Felix Fietkau e4744ec786 ath9k_hw: remove references to hw->conf
Accessing it to get the current operating channel is racy and in the way
of further channel handling related changes

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-10-14 13:39:59 -04:00
Felix Fietkau 1a5e63265f ath9k_hw: remove IS_CHAN_B()
Hardware 802.11b-only mode isn't supported by the driver (the device is
configured for 802.11n/g instead). Simplify the code by removing checks
for it.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-10-14 13:39:58 -04:00
Felix Fietkau 8896934c16 ath9k_hw: remove direct accesses to channel mode flags
Use wrappers where available. Simplifies code and helps with further
improvements to the channel data structure

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-10-14 13:39:58 -04:00
Sujith Manoharan 551ed40969 ath9k: Remove incorrect diversity initialization
Fast antenna diversity is required only for single chain
chips and the diversity initialization is done in the
per-family board setup routines. Enabling of diversity
should be done based on the calibrated EEPROM/OTP data,
doing it for all chips is incorrect.

Remove the code that sets the fast_div bit for all cards, since
the documentation for the AR_PHY_CCK_DETECT register says:

reg 642: sig_detect_cck
enable_ant_fast_div : Only used for single chain chips.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-09-26 15:13:50 -04:00
Sujith Manoharan 9ef4893234 ath9k: Fix issue with parsing malformed CFP IE
All QCA chips have the ability to parse the CF Parameter Set
IE in beacons. If the IE is malformed in the beacons from some
APs [1], the HW locks up. In AP mode, a beacon stuck would happen
and in client mode, a disconnection usually is the result.

To fix this issue, set the AR_PCU_MISC_MODE2_CFP_IGNORE to ignore
the CFP IE in beacons - this is applicable for all chips. For
AP mode, if this issue happens, the NAV is also corrupted and has
to be reset - this will be done in a subsequent patch.

[1] : http://msujith.org/ath9k/cfp/Malformed-CF-Param.png

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-09-26 15:13:46 -04:00
Sujith Manoharan f96bd2ad22 ath9k: Add support for AR9565 v1.0.1 LNA diversity
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-09-26 15:13:28 -04:00
Sujith Manoharan c946868228 ath9k: Fix antenna diversity init for AR9565
Program the HW registers (AR_PHY_CCK_DETECT, AR_PHY_MC_GAIN_CTRL)
with the correct values for AR9565 to allow LNA combining.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-09-26 15:13:28 -04:00
Sujith Manoharan 65c1a4de59 ath9k: Remove unused ANI commands
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-08-28 13:58:27 -04:00
Sujith Manoharan fb5a2dcbbc ath9k: Add support for AR9485 1.2
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-08-22 14:30:29 -04:00
Felix Fietkau a1c781bb20 ath9k: avoid accessing MRC registers on single-chain devices
They are not implemented, and accessing them might trigger errors

Cc: stable@vger.kernel.org
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-08-15 16:07:58 -04:00
Sujith Manoharan 36e8825e65 ath9k: Fix build failure
Make sure that CONFIG_ATH9K_BTCOEX_SUPPORT is used for
the WLAN/BT RX diversity hooks.

Reported by the kernel build testing backend.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-08-09 15:57:53 -04:00
Sujith Manoharan 84893817aa ath9k: Support ANT diversity for WB225
WB225 based cards like CUS198 and CUS230 support
both fast antenna diversity and LNA combining. Add support
for this and also program the SWCOM register with the
correct "ant_ctrl_comm2g_switch_enable" value.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-08-05 14:52:45 -04:00
Sujith Manoharan 7bdea96a1b ath9k: Remove "shared_chain_lnadiv"
This variable is redundant since we can use
common->bt_ant_diversity to determine if diversity
has to be enabled/disabled.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-08-05 14:52:44 -04:00
Sujith Manoharan d8d7744b72 ath9k: Rename ath9k_hw_antctrl_shared_chain_lnadiv
Use "ath9k_hw_set_bt_ant_diversity" instead.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-08-05 14:52:42 -04:00
Sujith Manoharan c2b8359d78 ath9k: Fix diversity combining for AR9285
When antenna diversity combining is enabled in the EEPROM,
the initial values for the MAIN/ALT config have to be
programmed correctly. This patch adds it for AR9285.

Since the diversity combining macros are common to all chip
families, remove the redundant AR9285 macros and move the
definitions to phy.h.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-07-24 11:02:39 -04:00
Sujith Manoharan 07a9bd2055 ath9k: Program correct initvals for FCC
* CUS217 specific initvals have to be programmed.
* iniAdditional is not used for AR9462/AR9565, remove it.
* Handle channel 2484 for regulatory compliance.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-07-22 16:54:43 -04:00
Sujith Manoharan 4b03f16eb5 ath9k: Move INI overrides to ar9003_hw_override_ini
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-07-22 16:54:41 -04:00
Sujith Manoharan 2b5e54e22f ath9k: Add support for AR9462 2.1
Various parts of the HW code are applicable for
both v2.0 and v2.1.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-06-24 14:44:28 -04:00
Sujith Manoharan c177fabe20 ath9k: Program initvals for CUS217
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-06-18 14:46:48 -04:00
Sujith Manoharan 51dbd0a897 ath9k: Add support for 5G-XLNA/AR9462
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-06-18 14:46:45 -04:00
Sujith Manoharan ff23e0845b ath9k: Fix ofdm weak signal configuration
The commit, "ath9k_hw: improve ANI processing and rx desensitizing parameters"
removed code setting various phy registers holding threshold values.

This is likely required for OFDM weak signal detection to function
correctly, so add them, but skip AR9462 and AR9565.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-06-12 14:59:11 -04:00
John W. Linville 861bca265e Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
Conflicts:
	drivers/net/wireless/ath/ath9k/Kconfig
	net/mac80211/iface.c
2013-06-12 14:35:23 -04:00
Sujith Manoharan c24bd3620c ath9k: Do not maintain ANI state per-channel
ANI state can be maintained globally instead of per-channel.
This reduces memory usage and since default values are used
during a scan run, per-channel state is not required.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-06-03 15:55:48 -04:00
Sujith Manoharan 4f4395c692 ath9k: Set ofdmWeakSigDetect directly
The macros ATH9K_ANI_USE_OFDM_WEAK_SIG can be removed.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-06-03 15:55:47 -04:00
Felix Fietkau 23dd9b2a43 ath9k_hw: fix spur mitigation issues on AR934x
Do not subtract spur power from noise floor on this chip, as it can lead
to packet loss and other connectivity issues.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2013-05-24 12:50:21 -04:00
John W. Linville 9ebea3829f Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
Conflicts:
	drivers/net/wireless/ath/ath9k/main.c
	drivers/net/wireless/iwlwifi/dvm/tx.c
2013-01-28 13:54:03 -05:00