Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.
This change also renames "clock"/"clk" to "modules"/"mod" in symbols
related to entries in configlink_clocks[], since:
- We don't care about clock handles any more, but rather reset handles,
so the old name isn't applicable.
- It really is a list of modules on the bus, about which we currently
only care about reset handles.
If we start caring about any other aspect of the modules in the future,
we won't have to rename all these symbols again.
Note: The addition of "depends COMMON_CLOCK" is something that was missing
before, not a new requirement.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Brown <broonie@linaro.org>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tegra124 introduces some small changes to the layout of some registers.
Modify the affected drivers to program those registers appropriately
based on which SoC they're running on.
Tegra124 also introduced some new modules on the AHUB configlink register
bus. These will require new entries in configlink_clocks[] in the AHUB
driver. However, supporting that change likely relies on switching Tegra
to the common reset framework, so I'll defer that change for now.
Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Use the common DAI DMA data struct for tegra, this allows us to use the common
helper function to configure the DMA slave config based on the DAI DMA data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tegra114's AHUB shares a design with Tegra30, with the followin changes:
* Supports more (10 vs. 4) bi-directional FIFO channels into RAM.
* Requires a separate block of registers to support the above.
* Supports more attached clients, i.e. new audio multiplexing and
de-multiplexing modules.
* Is affected by more clocks due to the above.
This change fully defines the device tree binding changes required to
represent these changes, and minimally extends the driver to support
the new hardware, without exposing any of the new FIFO channels.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The AHUB (Audio Hub) is a mux/crossbar which links all audio-related
devices except the HDA controller on Tegra30. The devices include the
DMA FIFOs, DAM (Digital Audio Mixers), I2S controllers, and SPDIF
controller. Audio data may be routed between these devices in various
combinations as required by board design/application.
Includes a squashed bugfix from Nikesh Oswal <noswal@nvidia.com>
Includes squashed bugfixes from Sumit Bhattacharya <sumitb@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Stephen Warren