Commit Graph

292 Commits

Author SHA1 Message Date
Nava kishore Manne 01c54e6289 fpga: versal-fpga: Add versal fpga manager driver
Add support for Xilinx Versal FPGA manager.

PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.

Reviewed-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Link: https://lore.kernel.org/r/20210626155248.5004-6-nava.manne@xilinx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-07-21 13:14:09 +02:00
Moritz Fischer 1e2658aef5 fpga: machxo2-spi: Address warning about unused variable
Address warning about unused variable in case CONFIG_OF is not set.

warning: unused variable 'of_match' [-Wunused-const-variable]
    static const struct of_device_id of_match[] = {

Fixes: 88fb3a0023 ("fpga: lattice machxo2: Add Lattice MachXO2 support")
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Tom Rix <trix@redhat.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210618224618.1487323-1-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-24 15:45:11 +02:00
Russ Weight 5e77886d0a fpga: region: Rename dev to parent for parent device
Rename variable "dev" to "parent" in cases where it represents the parent
device.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210614170909.232415-6-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-15 09:29:55 +02:00
Russ Weight ceb8ab3c07 fpga: bridge: Rename dev to parent for parent device
Rename variable "dev" to "parent" in cases where it represents the parent
device.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210614170909.232415-5-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-15 09:29:45 +02:00
Russ Weight 59ef362234 fpga: mgr: Rename dev to parent for parent device
Rename variable "dev" to "parent" in cases where it represents the parent
device.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210614170909.232415-4-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-15 09:29:35 +02:00
Russ Weight d9ec9daa20 fpga: stratix10-soc: Add missing fpga_mgr_free() call
The stratix10-soc driver uses fpga_mgr_create() function and is therefore
responsible to call fpga_mgr_free() to release the class driver resources.
Add a missing call to fpga_mgr_free in the s10_remove() function.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Fixes: e7eef1d763 ("fpga: add intel stratix10 soc fpga manager driver")
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20210614170909.232415-3-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-15 09:28:15 +02:00
Russ Weight 341466b64f fpga: altera-pr-ip: Remove function alt_pr_unregister
Remove the alt_pr_unregister() function; it is no longer used.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210614170909.232415-2-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-15 09:27:35 +02:00
Tom Rix 8923557bd5 fpga: stratix10-soc: change FPGA indirect article to an
Change use of 'a fpga' to 'an fpga'

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20210608212350.3029742-12-trix@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09 14:51:25 +02:00
Tom Rix 25feb31d26 fpga: of-fpga-region: change FPGA indirect article to an
Change use of 'a fpga' to 'an fpga'

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20210608212350.3029742-11-trix@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09 14:51:25 +02:00
Tom Rix 011c49e370 fpga: region: change FPGA indirect article to an
Change use of 'a fpga' to 'an fpga'

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20210608212350.3029742-10-trix@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09 14:51:25 +02:00
Tom Rix 895ec9c09a fpga-mgr: change FPGA indirect article to an
Change use of 'a fpga' to 'an fpga'

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20210608212350.3029742-9-trix@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09 14:51:25 +02:00
Tom Rix e7555cf6c2 fpga: bridge: change FPGA indirect article to an
Change use of 'a fpga' to 'an fpga'

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20210608212350.3029742-8-trix@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09 14:51:25 +02:00
Tom Rix df82d2ecd9 fpga: change FPGA indirect article to an
Change use of 'a fpga' to 'an fpga'

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20210608212350.3029742-7-trix@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09 14:51:25 +02:00
Linus Torvalds 37f00ab4a0 ARM: SoC drivers for v5.13
Updates for SoC specific drivers include a few subsystems that
 have their own maintainers but send them through the soc tree:
 
 TEE/OP-TEE:
  -  Add tracepoints around calls to secure world
 
 Memory controller drivers:
  - Minor fixes for Renesas, Exynos, Mediatek and Tegra platforms
  - Add debug statistics to Tegra20 memory controller
  - Update Tegra bindings and convert to dtschema
 
 ARM SCMI Firmware:
  - Support for modular SCMI protocols and vendor specific extensions
  - New SCMI IIO driver
  - Per-cpu DVFS
 
 The other driver changes are all from the platform maintainers
 directly and reflect the drivers that don't fit into any other
 subsystem as well as treewide changes for a particular platform.
 
 SoCFPGA:
  - Various cleanups contributed by Krzysztof Kozlowski
 
 Mediatek:
  - add MT8183 support to mutex driver
  - MMSYS: use per SoC array to describe the possible routing
  - add MMSYS support for MT8183 and MT8167
  - add support for PMIC wrapper with integrated arbiter
  - add support for MT8192/MT6873
 
 Tegra:
  - Bug fixes to PMC and clock drivers
 
 NXP/i.MX:
  - Update SCU power domain driver to keep console domain power on.
  - Add missing ADC1 power domain to SCU power domain driver.
  - Update comments for single global power domain in SCU power domain
    driver.
  - Add i.MX51/i.MX53 unique id support to i.MX SoC driver.
 
 NXP/FSL SoC driver updates for v5.13
  - Add ACPI support for RCPM driver
  - Use generic io{read,write} for QE drivers after performance optimized
    for PowerPC
  - Fix QBMAN probe to cleanup HW states correctly for kexec
  - Various cleanup and style fix for QBMAN/QE/GUTS drivers
 
 OMAP:
  - Preparation to use devicetree for genpd
  - ti-sysc needs iorange check improved when the interconnect target module
    has no control registers listed
  - ti-sysc needs to probe l4_wkup and l4_cfg interconnects first to avoid
    issues with missing resources and unnecessary deferred probe
  - ti-sysc debug option can now detect more devices
  - ti-sysc now warns if an old incomplete devicetree data is found as we
    now rely on it being complete for am3 and 4
  - soc init code needs to check for prcm and prm nodes for omap4/5 and dra7
  - omap-prm driver needs to enable autoidle retention support for omap4
  - omap5 clocks are missing gpmc and ocmc clock registers
  - pci-dra7xx now needs to use builtin_platform_driver instead of using
    builtin_platform_driver_probe for deferred probe to work
 
 Raspberry Pi:
  - Fix-up all RPi firmware drivers so as for unbind to happen in an
    orderly fashion
  - Support for RPi's PoE hat PWM bus
 
 Qualcomm
  - Improved detection for SCM calling conventions
  - Support for OEM specific wifi firmware path
  - Added drivers for SC7280/SM8350: RPMH, LLCC< AOSS QMP
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmCC2JwACgkQmmx57+YA
 GNkgRg//cBtq2NyDbjiNABxFSkmGCfcc0w0C2wjVzr4cfg6BLTbuvvlpZxI912pu
 P1G2sbsdfQJ8sSeIyZos+PilWK0zHrqlaGZfKI19US45dMjpteDBgsPd7wNZwBjQ
 jbops3YLjztZK1HpY4dIdvMnfxt7yRqhBWaTbPuCwQ35c5KsOM8NHB3cP3BUINWK
 x1uuBCv9svppzwdDiPxneV93WKEzabOUo+WBMPyh5vnyvmW17Iif4BA/VKQxzymm
 mWUi8HHpKBpvntJOKwAD2hnLAdpR3SwX20SLOpyLhnJMotbzNUEqq3LdRxDNPdHk
 ry+rarJ78JGlYfpcfegf2bLf5ITNMfOyRGkjtzeYpcZIXPjufOg9DA9YtAy37k0u
 L0T/9gQ+tQ01WGMca77OyUtIqJKdblZrQMfuH/yGlR99bqFQMV7rNc7GNlX1MXp/
 zw4aOYrRWGtGEeAjx5JJWcYydvMSJpCrqxTz3YhgeJECHB2iA6YkV3NROR4TLW//
 tfxaKqxR/KmSqE6hoVOAuuQ0BLXNlql/+4EE6MKsAOBiKPJclvmJg4CyuY8G21ev
 9Su0zJnXMzai7gNu32v1pizGj26+AOhxCEgAG0mGgk2jlQSn24CKgm5e7kCUewcF
 j/1XksNPT95v/K8MsLpXe5xGvF3jhA1BlFfvjJNZOrcZywBXRxg=
 =iidq
 -----END PGP SIGNATURE-----

Merge tag 'arm-drivers-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "Updates for SoC specific drivers include a few subsystems that have
  their own maintainers but send them through the soc tree:

  TEE/OP-TEE:
   - Add tracepoints around calls to secure world

  Memory controller drivers:
   - Minor fixes for Renesas, Exynos, Mediatek and Tegra platforms
   - Add debug statistics to Tegra20 memory controller
   - Update Tegra bindings and convert to dtschema

  ARM SCMI Firmware:
   - Support for modular SCMI protocols and vendor specific extensions
   - New SCMI IIO driver
   - Per-cpu DVFS

  The other driver changes are all from the platform maintainers
  directly and reflect the drivers that don't fit into any other
  subsystem as well as treewide changes for a particular platform.

  SoCFPGA:
   - Various cleanups contributed by Krzysztof Kozlowski

  Mediatek:
   - add MT8183 support to mutex driver
   - MMSYS: use per SoC array to describe the possible routing
   - add MMSYS support for MT8183 and MT8167
   - add support for PMIC wrapper with integrated arbiter
   - add support for MT8192/MT6873

  Tegra:
   - Bug fixes to PMC and clock drivers

  NXP/i.MX:
   - Update SCU power domain driver to keep console domain power on.
   - Add missing ADC1 power domain to SCU power domain driver.
   - Update comments for single global power domain in SCU power domain
     driver.
   - Add i.MX51/i.MX53 unique id support to i.MX SoC driver.

  NXP/FSL SoC driver updates for v5.13
   - Add ACPI support for RCPM driver
   - Use generic io{read,write} for QE drivers after performance
     optimized for PowerPC
   - Fix QBMAN probe to cleanup HW states correctly for kexec
   - Various cleanup and style fix for QBMAN/QE/GUTS drivers

  OMAP:
   - Preparation to use devicetree for genpd
   - ti-sysc needs iorange check improved when the interconnect target
     module has no control registers listed
   - ti-sysc needs to probe l4_wkup and l4_cfg interconnects first to
     avoid issues with missing resources and unnecessary deferred probe
   - ti-sysc debug option can now detect more devices
   - ti-sysc now warns if an old incomplete devicetree data is found as
     we now rely on it being complete for am3 and 4
   - soc init code needs to check for prcm and prm nodes for omap4/5 and
     dra7
   - omap-prm driver needs to enable autoidle retention support for
     omap4
   - omap5 clocks are missing gpmc and ocmc clock registers
   - pci-dra7xx now needs to use builtin_platform_driver instead of
     using builtin_platform_driver_probe for deferred probe to work

  Raspberry Pi:
   - Fix-up all RPi firmware drivers so as for unbind to happen in an
     orderly fashion
   - Support for RPi's PoE hat PWM bus

  Qualcomm
   - Improved detection for SCM calling conventions
   - Support for OEM specific wifi firmware path
   - Added drivers for SC7280/SM8350: RPMH, LLCC< AOSS QMP"

* tag 'arm-drivers-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits)
  soc: aspeed: fix a ternary sign expansion bug
  memory: mtk-smi: Add device-link between smi-larb and smi-common
  memory: samsung: exynos5422-dmc: handle clk_set_parent() failure
  memory: renesas-rpc-if: fix possible NULL pointer dereference of resource
  clk: socfpga: fix iomem pointer cast on 64-bit
  soc: aspeed: Adapt to new LPC device tree layout
  pinctrl: aspeed-g5: Adapt to new LPC device tree layout
  ipmi: kcs: aspeed: Adapt to new LPC DTS layout
  ARM: dts: Remove LPC BMC and Host partitions
  dt-bindings: aspeed-lpc: Remove LPC partitioning
  soc: fsl: enable acpi support in RCPM driver
  soc: qcom: mdt_loader: Detect truncated read of segments
  soc: qcom: mdt_loader: Validate that p_filesz < p_memsz
  soc: qcom: pdr: Fix error return code in pdr_register_listener
  firmware: qcom_scm: Fix kernel-doc function names to match
  firmware: qcom_scm: Suppress sysfs bind attributes
  firmware: qcom_scm: Workaround lack of "is available" call on SC7180
  firmware: qcom_scm: Reduce locking section for __get_convention()
  firmware: qcom_scm: Make __qcom_scm_is_call_available() return bool
  Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers"
  ...
2021-04-26 12:11:52 -07:00
Russ Weight a78a51a851 fpga: dfl: pci: add DID for D5005 PAC cards
This patch adds the approved PCI Express Device IDs for the
PF and VF for the card for D5005 PAC cards.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-04-05 17:46:56 -07:00
Russ Weight 9a8d3cda8d fpga: dfl: afu: harden port enable logic
Port enable is not complete until ACK = 0. Change
__afu_port_enable() to guarantee that the enable process
is complete by polling for ACK == 0.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-03-24 11:15:04 -07:00
Krzysztof Kozlowski 3a1fef70ff fpga: altera: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs
ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the
32-bit ARM drivers to rely on new symbol.

Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-23 11:03:36 -05:00
Krzysztof Kozlowski 4a9a1a5602 arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGA
Agilex, N5X and Stratix 10 share all quite similar arm64 hard cores and
SoC-part.  Up to a point that N5X uses the same DTSI as Agilex.  From
the Linux kernel point of view these are flavors of the same
architecture so there is no need for three top-level arm64
architectures.  Simplify this by merging all three architectures into
ARCH_INTEL_SOCFPGA and dropping the other ARCH* arm64 Kconfig entries.

The side effect is that the INTEL_STRATIX10_SERVICE will now be
available for both 32-bit and 64-bit Intel SoCFPGA, even though it is
used only for 64-bit.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-23 11:03:36 -05:00
Nava kishore Manne 6f1e376cfc fpga: Add support for Xilinx DFX AXI Shutdown manager
This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI
shutdown manager IP. It can be used to safely handling the AXI traffic
on a Reconfigurable Partition when it is undergoing dynamic reconfiguration
and there by preventing system deadlock that may occur if AXI transactions
are interrupted during reconfiguration.

PR-Decoupler and AXI shutdown manager are completely different IPs.
But both the IP registers are compatible and also both belong to the
same sub-system (fpga-bridge).So using same driver for both IP's.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-03-06 07:54:40 -08:00
Michal Simek 2d6e820c4e fpga: xilinx-pr-decoupler: Simplify code by using dev_err_probe()
Use already prepared dev_err_probe() introduced by commit a787e5400a
("driver core: add device probe log helper").
It simplifies EPROBE_DEFER handling.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-03-06 07:39:17 -08:00
Luca Ceresoli 484a58607a fpga: fpga-mgr: xilinx-spi: fix error messages on -EPROBE_DEFER
The current code produces an error message on devm_gpiod_get() errors even
when the error is -EPROBE_DEFER, which should be silent.

This has been observed producing a significant amount of messages like:

    xlnx-slave-spi spi1.1: Failed to get PROGRAM_B gpio: -517

Fix and simplify code by using the dev_err_probe() helper function.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Fixes: dd2784c01d ("fpga manager: xilinx-spi: check INIT_B pin during write_init")
Fixes: 061c97d13f ("fpga manager: Add Xilinx slave serial SPI driver")
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-03-06 07:39:17 -08:00
Greg Kroah-Hartman 09381eb16a First set of FPGA Manager changes for 5.12-rc1
This is the first set of changes for the FPGA Manager 5.12-rc1
 mergewindow.
 
 DFL:
 - Minor cleanup, constifying a static attribute group
 
 Core:
 - Minor cleanup, using DEFINE_SPINLOCK over open coding it
 
 All patches have been reviewed on the mailing list, and have been in the
 last linux-next releases (as part of my for-next branch) without issues.
 
 Signed-off-by: Moritz Fischer <mdf@kernel.org>
 -----BEGIN PGP SIGNATURE-----
 
 iIUEABYIAC0WIQRORt0E5Sb/c/mZMgkXxQAtim5VSwUCX/1KeQ8cbWRmQGtlcm5l
 bC5vcmcACgkQF8UALYpuVUuYpQEAya7GC+ILtLWm0IATwbIbn7grNP3THNnD0XBG
 jeoTY5sBAPzr4DQdQibqHQOsK6rpXsg8XOxZVkQPUHeVwAG0Me0B
 =a63k
 -----END PGP SIGNATURE-----

Merge tag 'fpga-cleanup-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next

Moritz writes:

First set of FPGA Manager changes for 5.12-rc1

This is the first set of changes for the FPGA Manager 5.12-rc1
mergewindow.

DFL:
- Minor cleanup, constifying a static attribute group

Core:
- Minor cleanup, using DEFINE_SPINLOCK over open coding it

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of my for-next branch) without issues.

Signed-off-by: Moritz Fischer <mdf@kernel.org>

* tag 'fpga-cleanup-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
  fpga: dfl: fme: Constify static attribute_group structs
  fpga: Use DEFINE_SPINLOCK() for spinlock
2021-01-12 10:19:14 +01:00
Rikard Falkeborn e41d4c0117 fpga: dfl: fme: Constify static attribute_group structs
The only usage of these is to put their addresses in arrays of pointers
to const attribute_groups. Make them const to allow the compiler to put
them in read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-01-10 10:57:14 -08:00
Zheng Yongjun f5187329d0 fpga: Use DEFINE_SPINLOCK() for spinlock
spinlock can be initialized automatically with DEFINE_SPINLOCK()
rather than explicitly calling spin_lock_init().

Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-01-10 10:57:13 -08:00
Xu Yilun 56172ab353 fpga: dfl: add support for N3000 Nios private feature
This patch adds support for the Nios handshake private feature on Intel
PAC (Programmable Acceleration Card) N3000.

The Nios is the embedded processor on the FPGA card. This private feature
provides a handshake interface to FPGA Nios firmware, which receives
retimer configuration command from host and executes via an internal SPI
master (spi-altera). When Nios finishes the configuration, host takes over
the ownership of the SPI master to control an Intel MAX10 BMC (Board
Management Controller) Chip on the SPI bus.

For Nios firmware handshake part, this driver requests the retimer
configuration for Nios firmware on probe, and adds some sysfs nodes for
user to query the onboard retimer's working mode and Nios firmware
version.

For SPI part, this driver adds a spi-altera platform device as well as
the MAX10 BMC spi slave info. A spi-altera driver will be matched to
handle the following SPI work.

[mdf@kernel.org: Fixed up ABI doc kernel release]

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20210107043714.991646-8-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-07 15:21:27 +01:00
Xu Yilun ecc1641aca fpga: dfl: move dfl bus related APIs to include/linux/dfl.h
Now the dfl drivers could be made as independent modules and put in
different folders according to their functionalities. In order for
scattered dfl device drivers to include dfl bus APIs, move the
dfl bus APIs to a new header file in the public folder.

[mdf@kernel.org: Fixed up header guards to match filename]

Reviewed-by: Tom Rix <trix@redhat.com>
Acked-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210107043714.991646-7-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-07 15:21:27 +01:00
Xu Yilun 9326eecd93 fpga: dfl: move dfl_device_id to mod_devicetable.h
In order to support MODULE_DEVICE_TABLE() for dfl device driver, this
patch moves struct dfl_device_id to mod_devicetable.h

Some brief description for DFL (Device Feature List) is added to make
the DFL known to the whole kernel.

Reviewed-by: Tom Rix <trix@redhat.com>
Acked-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210107043714.991646-5-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-07 15:21:27 +01:00
Xu Yilun e08b9e6d87 fpga: dfl: fix the definitions of type & feature_id for dfl devices
The value of the field dfl_device.type comes from the 12 bits register
field DFH_ID according to DFL spec. So this patch changes the definition
of the type field to u16.

Also it is not necessary to illustrate the valid bits of the type field
in comments. Instead we should explicitly define the possible values in
the enumeration type for it, because they are shared by hardware spec.
We should not let the compiler decide these values.

Similar changes are also applied to dfl_device.feature_id.

This patch also fixed the MODALIAS format according to the changes
above.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210107043714.991646-4-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-07 15:21:27 +01:00
Matthew Gerlach fa41d10589 fpga: dfl-pci: locate DFLs by PCIe vendor specific capability
A PCIe vendor specific extended capability is introduced by Intel to
specify the start of a number of DFLs.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210107043714.991646-3-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-07 15:21:27 +01:00
Matthew Gerlach 3e265f836e fpga: dfl: refactor cci_enumerate_feature_devs()
In preparation of looking for dfls based on a vendor specific pci
capability, move the code for the default method of finding the first
dfl at offset 0 of Bar 0 to its own function.

Acked-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210107043714.991646-2-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-07 15:21:27 +01:00
Greg Kroah-Hartman a3ab07c642 Merge 5.10-rc7 into char-misc-next
We want the fixes in here, and this resolves a merge issue with
drivers/misc/habanalabs/common/memory.c.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-07 10:08:14 +01:00
Moritz Fischer 907d4ad599 fpga: fpga-mgr: altera-pr-ip: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-11-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer 2630fa8d00 fpga: fpga-mgr: zynqmp: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-10-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer f4ce435b73 fpga: fpga-mgr: xilinx-spi: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-9-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer d6530c0a48 fpga: fpga-mgr: ts73xx: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-8-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer 20e8963f4f fpga: fpga-mgr: socfpga: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-7-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer a3b79b2a58 fpga: fpga-mgr: machxo2-spi: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-6-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer 7027b7305d fpga: fpga-mgr: ice40-spi: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-5-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer 83eb4fbdcf fpga: fpga-mgr: dfl-fme-mgr: Simplify registration
Simplify registration using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-4-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer c9d754d6f7 fpga: fpga-mgr: altera-ps-spi: Simplify registration
Simplify registration by using new devm_fpga_mgr_register() API.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-3-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
Moritz Fischer 57d9352b6c fpga: fpga-mgr: Add devm_fpga_mgr_register() API
Add a devm_fpga_mgr_register() API that can be used to register a FPGA
Manager that was created using devm_fpga_mgr_create().

Introduce a struct fpga_mgr_devres that makes the devres
allocation a little bit more readable and gets reused for
devm_fpga_mgr_create() devm_fpga_mgr_register().

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201115195127.284487-2-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:49:32 +01:00
David Gow 1a16af33ba fpga: Specify HAS_IOMEM dependency for FPGA_DFL
Because dfl.c uses the 'devm_ioremap', 'devm_iounmap',
'devm_ioremap_resource', and 'devm_platform_ioremap_resource'
functions, it should depend on HAS_IOMEM.

This fixes make allyesconfig under UML (ARCH=um), which doesn't provide
HAS_IOMEM.

[mdf@kernel.org: Removed "drivers: " in commit message]
Fixes: 89eb35e810 ("fpga: dfl: map feature mmio resources in their own feature drivers")
Signed-off-by: David Gow <davidgow@google.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20201122001549.107023-2-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-12-01 18:46:24 +01:00
Xu Yilun 9ba3a0aa09 fpga: dfl: create a dfl bus type to support DFL devices
A new bus type "dfl" is introduced for private features which are not
initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
private features could be handled by separate driver modules.

DFL feature drivers (dfl-fme, dfl-port) will create DFL devices on
enumeration. DFL drivers could be registered on this bus to match these
DFL devices. They are matched by dfl type & feature_id.

[mdf@kernel.org: Add missing Documentation part to MAINTAINERS file]

Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Acked-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-09-09 20:28:16 -07:00
Moritz Fischer c71e805083 fpga: fpga-region: Cleanup an outdated comment
Clean up an outdated comment claiming FPGA regions implement devicetree
support for reprogramming FPGAs.

Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-09-04 20:27:45 -07:00
Xu Yilun 89eb35e810 fpga: dfl: map feature mmio resources in their own feature drivers
This patch makes preparation for modularization of DFL sub feature
drivers.

DFL based FPGA devices may contain some IP blocks which are already
supported by kernel, most of them are supported by platform device
drivers. We could create platform devices for these IP blocks and get them
supported by these drivers.

An important issue is that platform device drivers usually requests mmio
resources on probe. But now DFL mmio is mapped in DFL bus driver (e.g.
dfl-pci) as a whole region. Then platform device drivers for sub features
can't request their own mmio resources again. This is what the patch
trying to resolve.

This patch changes the DFL enumeration. DFL bus driver will unmap mmio
resources after first step enumeration and pass enumeration info to DFL
framework. Then DFL framework will map the mmio resources again, do 2nd
step enumeration, and also unmap the mmio resources. In this way, sub
feature drivers could then request their own mmio resources as needed.

An exception is that mmio resource of FIU headers are still mapped in DFL
bus driver. The FIU headers have some fundamental functions (sriov set,
port enable/disable) needed for DFL bus devices and other sub features.
They should not be unmapped as long as DFL bus device is alive.

Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Acked-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-08-30 17:15:58 -07:00
Luca Ceresoli 4e772ab86b fpga manager: xilinx-spi: provide better diagnostics on programming failure
When the DONE pin does not go high after programming to confirm programming
success, the INIT_B pin provides some info on the reason. Use it if
available to provide a more explanatory error message.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-08-30 17:09:05 -07:00
Luca Ceresoli eefe64fba9 fpga manager: xilinx-spi: add error checking after gpiod_get_value()
Current code calls gpiod_get_value() without error checking. Should the
GPIO controller fail, execution would continue without any error message.

Fix by checking for negative error values.

Reported-by: Tom Rix <trix@redhat.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-08-30 17:08:57 -07:00
Luca Ceresoli 16b7856d94 fpga manager: xilinx-spi: fix write_complete timeout handling
If this routine sleeps because it was scheduled out, it might miss DONE
going asserted and consider it a timeout. This would potentially make the
code return an error even when programming succeeded. Rewrite the loop to
always check DONE after checking if timeout expired so this cannot happen
anymore.

While there, also add error checking for gpiod_get_value(). Also avoid
checking the DONE GPIO in two places, which would make the error-checking
code duplicated and more annoying.

The new loop it written to still guarantee that we apply 8 extra CCLK
cycles after DONE has gone asserted, which is required by the hardware.

Reported-by: Tom Rix <trix@redhat.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-08-30 17:06:50 -07:00
Luca Ceresoli a44ecdc9c9 fpga manager: xilinx-spi: remove final dot from dev_err() strings
Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.

Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-08-30 17:04:18 -07:00
Luca Ceresoli 5e36aff2e1 fpga manager: xilinx-spi: remove stray comment
Remove comment committed by mistake.

Fixes: dd2784c01d ("fpga manager: xilinx-spi: check INIT_B pin during write_init")
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2020-08-19 21:10:47 -07:00