The DSI host and PHY driver currently expects the DT bindings to provide
custom properties "qcom,dsi-host-index" and "qcom,dsi-phy-index" so that
the driver can identify which DSI instance it is.
The binding isn't acceptable, but the driver still needs to figure out
what its instance id. This is now done by storing the mmio starting
addresses for each DSI instance in every SoC version in the driver. The
driver then identifies the index number by trying to match the stored
address with comparing the resource start address we get from DT.
We don't have compatible strings for DSI PHY on each SoC, but only the
DSI PHY type. We only support one SoC version for each PHY type, so we
get away doing the same thing above for the PHY driver. We can revisit
this when we support two SoCs with the same DSI PHY.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Introduce new compatible strings for the top level MDSS wrapper device,
and the MDP5 device.
Previously, the "qcom,mdp5" and "qcom,mdss_mdp" compatible strings
were used to match the top level platform_device (which was also tied
to the top level drm_device struct). Now, these strings are used
to match the MDP5 platform device.
Use "qcom,mdss" as the compatible string for top level MDSS device.
This is now used to match the top level platform_device (which is
tied to the drm_device struct).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The driver currently identifies the GPU components it needs by parsing
a phandle list from the 'gpus' DT property.
This isn't the right binding to go with. So, for now, just search all
device nodes and find the gpu node we need by parsing a list of
compatible strings.
Once we know how to link the kms and gpu drivers, we'll drop this method
and use the correct binding.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
For MDP5 based platforms, the master device isn't the MDP5 platform
device, but the top level MDSS device, which is a parent to MDP5 and
interface (DSI, HDMI, eDP etc) devices.
In order to add components on MDP5 platforms, we first need to populate
the MDSS children, locate the MDP5 child, and then parse its ports to
get the display interfaces.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The kms driver currently identifies all the mdss components it needs by
parsing a phandle list from the 'connectors' DT property.
Instead of this, describe a list of ports that the MDP hardware provides
to the external world. These ports are linked to external encoder
interfaces such as DSI, HDMI. These are also the subcomponent devices
that we need add. This description of ports complies with the generic
graph bindings.
The LVDS port is a special case since it is a part of MDP4 itself, and
its output connects directly to the LVDS panel. In this case, we don't
try to add it as a component.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Since runtime PM isn't implemented yet, we need to call
mdp5_enable/disable in a few more places. These would later be
replaced by runtime PM get/put calls.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
With the new device hierarchy for MDP5, we need to enable runtime PM
for both the toplevel MDSS device and the MDP5 device itself. Enable
runtime PM for the new devices.
Since MDP4 and MDP5 now have different places where runtime PM is
enabled, remove the previous pm_runtime_enable/disable calls, and
squash them in the respective kms drivers.
The new device hierarchy (as expressed in the DT bindings) has the GDSC
tied only to the MDSS wrapper device. This GDSC needs to be enabled for
accessing any register in the MDSS sub-blocks. Once every driver is
runtime adapted, the GDSC will be enabled when any sub-block device
calls runtime_get because of the parent-child relationship with MDSS.
Until then, we call pm_runtime_get_sync() once for the MDSS device to
ensure the GDSC is never disabled. This will be removed once all the
drivers are runtime PM adapted.
The error handling paths become a bit tricky when we call these runtime
PM funcs. There doesn't seem to be any helper that checks if runtime PM
is enabled already. Add bool variables in mdp4_kms/mdp5_kms structs to
check if the driver had managed to call pm_runtime_enable before bailing
out.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The MDP5 sub-block register offsets are relative to the top level
MDSS register address.
Now that we have the start of MDP5 register address space, provide
the offsets relative to that. This involves subtracting the offsets
with 0x1000 or 0x100 depending on the MDP5 version.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Since MDSS registers were stuffed within the the MDP5 register
space, we had an __offset_MDP() macro to identify the offset
between the start of MDSS and MDP5 address spaces. This offset
macro expected a MDP index argument, which didn't make much
sense since we don't have multiple MDPs.
The offset is no longer needed now that we have devices for the 2
different register address spaces. Also, remove the "REG_MDP5_MDP_"
prefix to "REG_MDP5_".
Update the generated headers in mdp5.xml.h
We generally update headers as a separate patch, but we need to
do these together to prevent breaking build.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
With the new kms_init/destroy funcs in place for MDP5, we can get rid of
the old kms funcs. Some members of the mdp5_kms struct also become
redundant, so we remove those too.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Call msm_mdss_init in msm_drv to set up top level registers/irq line.
Start using the new kms_init2/destroy2 funcs to inititalize MDP5 KMS.
With the MDSS interrupt and irqdomain set up, the old MDP5 irq code
can be dropped.
The mdp5_hw_init kms func now uses the platform device tied to MDP5
instead of the one tied to the drm_device/MDSS.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
With MDP5 as a new device, we need to do less for MDP when initializing
modeset after all the components are bound.
Create mdp5_kms_init2/destroy2 funcs that inits modeset. These will
eventually replace the older kms_init/destroy funcs.
In the new kms_init2, the platform_device used is the one corresponding
to the new MDP5 platform_device. The new change here is that the irq is
now retrieved using irq_of_parse_and_map(), since MDP5 is a child interrupt
of the MDSS interrupt controller.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
In order to have a tree-like device hierarchy between MDSS and its
sub-blocks (MDP5, DSI, HDMI, eDP etc), we need to create a separate
device/driver for MDP5. Currently, MDP5 and MDSS are squashed
together are are tied to the top level platform_device, which is
also the one used to create drm_device.
The mdp5_kms_init code is split into two parts. The part where device
resources are allocated are associated with the MDP5 driver's probe,
the rest is executed later when we initialize modeset.
With this change, unlike MDP4, the MDP5 platform_device isn't tied to
the top level drm_device anymore. The top level drm_device is now
associated with a platform device that corresponds to MDSS wrapper
hardware.
Create mdp5_init/destroy funcs that will be used by the MDP5 driver
probe/remove. Use the HW_VERSION register in the MDP5 register address
space. Both the MDSS and MDP VERSION registers give out identical
version info.
The older mdp5_kms_init code is left as is for now, this would be removed
later when we have all the pieces to support the new device hierarchy.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
SoCs that contain MDP5 have a top level wrapper called MDSS that manages
clocks, power and irq for the sub-blocks within it.
Currently, the MDSS portions are stuffed into the MDP5 driver. This makes
it hard to represent the DT bindings in the correct way. We create a top
level MDSS helper that handles these parts. This is essentially moving out
some of the mdp5_kms irq code and MDSS register space and keeping it as a
separate entity. We haven't given any clocks to the top level MDSS yet,
but a AHB clock would be added in the future to access registers.
One thing to note is that the resources allocated by this helper are
tied to the top level platform_device (the one that allocates the
drm_device struct too). This device would be the parent to MDSS
sub-blocks like MDP5, DSI, eDP etc.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The driver gets the irq number using platform_get_irq on the main kms
platform device. This works fine since both MDP4 and MDP5 currently
have a flat device hierarchy. The platform device tied with the
drm_device points to the MDP DT node in both cases.
This won't work when MDP5 supports a tree-like hierarchy. In this
case, the platform device tied to the top level drm_device is the
MDSS DT node, and the irq we need for KMS is the one generated by
MDP5, not MDSS.
Get the irq number from the MDP4/5 kms driver itself. Each driver
can later provide the irq number based on what device hierarchy it
uses.
While we're at it, call drm_irq_install only when we have a valid KMS
driver.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
These aren't used. Probably left overs when driver was refactored to
support both MDP4 and MDP5.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
A more standard DT binding describing data lanes already exists here:
Documentation/devicetree/bindings/media/video-interfaces.txt
Use this binding instead of "qcom,data-lane-map". One difference
in the standard binding w.r.t to the existing binding is that it
provides a logical to physical mapping instead of the other way
round. Tweak the code to translate the data the way we want it.
The MSM DSI DT bindings aren't used anywhere at the moment, so
it's okay to update this property.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The DSI host links to the DSI PHY device using a custom binding. Switch to
the generic PHY bindings. The DSI PHY driver itself doesn't use the common
PHY framework for now.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The DSI interface is going to have two ports defined in its device node.
The first port is always going to be the link between the MDP output
and the input to DSI, the second port is going to be the link between
the DSI output and the connected panel/bridge:
----- ----- -------
| MDP | ------> | DSI | ------> | Panel |
----- ----- -------
(Port 0) (Port 1)
Until now, there was only one Port representing the output. Update the
DSI host driver such that it parses Port #1 for a connected device.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Fix some issues with MDP4 clocks:
- mdp4_dtv_encoder tries to get "src_clk", which is a RCG(TV_SRC) in
MSM8960 and APQ8064. This isn't something the driver should access or
configure. Instead of this, configure the "mdp_clk" (MDP_TV_CLK), a
branch clock in MMCC that has the TV_SRC as its parent. Setting
rate/enabling the "mdp_clk" will eventually configure "src_clk", which
is what we want.
- Rename "mdp_clk" to "tv_clk" because that's slightly less confusing.
- Rename "mdp_axi_clk" to "bus_clk" because that's what we do elsewhere
too.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The driver expects DT to provide the parent to MDP core clock. The only
operation done to the parent clock is to set a rate. This can be
achieved by setting the rate on the core clock itsef. Don't try to
get the parent clock anymore.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The msm_iommu_map/unmap funcs have debug prints to show the list of
VA:PA mappings. Use the correct variable to print the VAs.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The u32 type used to pass the physical addresses to iommu_map can't
accommodate 64 bit addresses. Move to dma_addr_t to ensure wrong
addresses aren't provided to the IOMMU driver.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
allowing GLSL shaders with non-unrolled loops.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCgAGBQJXiWHaAAoJELXWKTbR/J7olkkP/3buVvzBdxQmT7yMeBL2Up+F
MZ+W/pr7+gWXT/rvyY8zbEZV1txQtZDnvu8cC3h9E66TVYpTx3dYypECwiRKFt5f
HXhrkiniu65zBPhtYxloswcr686SpFOhr9rwy6cJbCCvuZQZVpQ41Fu7BinaYJc2
uGllnNmRkB7tPG/6BYQ/MAWvR7AjTaaAmcdhNZDyEHqXHiUu8NPprL0BQIwS1GMn
65pQjni/WEek6/WxncxszaDWfsLMRJPKiuPV4kAsoQDluB3ortk3k1VVNJ+n3aXw
GjlMNbU2ganEGWJS16e7HXXz3I19SQHn5mnL74X3GGL8r2x9AIZ64Zk7Ru659NBq
CW/NsSWM/TfU6T4iflbZjSVlmtbvdX5T0rDFb+lMFNXG8EvmRIc3fkbSeh6gF9sF
hc3UDS3ScQBAm8QOpDiVAsXNBGJUTsvxdDYgVUj1mjPtbD1ZDmEWYdb2fzs/n7ja
qU/CW9Ap3tModkTjaD58RoenTkbTXymhxmRd1JHoxVztkAM00fNxtGP6fTxuGLOW
snOoE9Ahdq/IzV/yZrqvWRCLTDenQ/ZxcP+fYleJ6M3qLxfHkgZX/chy/n21Q80G
Qe40uqBWreTCz6SzCEOXeaJ9RDbZfSomVfWuLzm5IGMhOmh1rqkpdgAUKQW7OvxB
e/LnruAmY/K7Yin87gK6
=Qh0U
-----END PGP SIGNATURE-----
Merge tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux into drm-next
This pull request brings in vc4 shader validation for branching,
allowing GLSL shaders with non-unrolled loops.
* tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux:
drm/vc4: Fix a "the the" typo in a comment.
drm/vc4: Fix definition of QPU_R_MS_REV_FLAGS
drm/vc4: Add a getparam to signal support for branches.
drm/vc4: Add support for branching in shader validation.
drm/vc4: Add a bitmap of branch targets during shader validation.
drm/vc4: Move validation's current/max ip into the validation struct.
drm/vc4: Add a getparam ioctl for getting the V3D identity regs.
This set of changes contains a few cleanups for existing panels as well
as improved handling of certain backlights. In addition there's support
for a few new simple panels.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJXh5uyAAoJEN0jrNd/PrOhtysQAJ1raFyTpNYltaMsiDnA117k
0rs2ILE9L6hI2p/3ibewwi1S2mVs9i9vnCBYkBNxheuspKs0SBoVVKuMUr00WvDE
fmI/rOs1Ygqh9jX8j1XIkvjtD+MHtjxmaMWymaV2F2/vpjQ3ReTLPv4cuf1odjDf
qsmRNjH+2UhxPrkp+aeVwlafcA3ZbsCJ3sqxLQVY4TMTBCZFemaKoIkQQrNahWH9
dyRwnYuQm7t2YUytIf4EoZcX14O1D4hF8NM5teFMzolSL5lACOAY+Kg0Goai9rXU
RmnGAMlCXuAWJxJm2YlJMr21TDNqsGPZHu6LpX2dNbc+K8yfNXCkiivBdS9yIx0q
qoL7BTGJupPTW2g9rXKY4fovF9gcyND2yNqyNFHAa5aq9Cw68yCV2u5Yz0oYYS8T
BlSkAuY4bpmjuL2kgpP5hNU1CZqDvjI7KKPtklGBOa3/8J4b++m/FxVZPmvquB6m
rv42bk1y5NWK3VFhLbYGmRo5mjm0BLk0/bIP3T4Uk/mbpd2aJNfJWcyMhd8waTVd
ene3iV6WYtuvZMuvaM4y94QRiH1hX+rGAaf/4tvUIBxSlKK9EBi1x6xPpVZlkJ4F
ZgYRc8E8IiWsqXAO4p9qW8ZlHGL2wCAOzZL+uu17GbURWxChC9u6vr2TEooflrgs
9OxI3YHinSbv9+Vz8yMg
=XLd7
-----END PGP SIGNATURE-----
Merge tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/panel: Changes for v4.8-rc1
This set of changes contains a few cleanups for existing panels as well
as improved handling of certain backlights. In addition there's support
for a few new simple panels.
* tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/panel: simple: Add support for Starry KR122EA0SRA panel
dt-bindings: Add Starry KR122EA0SRA panel binding
dt-bindings: Add vendor prefix for Starry
dt-bindings: display: Add Sharp LQ101K1LY04 panel binding
drm/panel: simple: Add support for Sharp LQ101K1LY04
drm/panel: simple: Add support for LG LP079QX1-SP0V panel
dt-bindings: Add support for LG LP079QX1-SP0V panel
drm/panel: simple: Add support for Sharp LQ123P1JX31 panel
dt-bindings: Add Sharp LQ123P1JX31 panel binding
drm/panel: simple: Add support for Samsung LSN122DL01-C01 panel
dt-bindings: Add Samsung LSN122DL01-C01 panel binding
drm/panel: simple: Add support for LG LP097QX1-SPA1 panel
dt-bindings: Add LG LP097QX1-SPA1 panel binding
drm/panel: simple: Update backlight state property
drm/panel: simple: Remove gratuitous blank line
drm/panel: simple: Fix a couple of physical sizes
This set of changes contains a bunch of cleanups to the host1x driver as
well as the addition of a pin controller for DPAUX, which is required by
boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C
mode (for HDMI and DDC).
Included is also a bit of rework of the SOR driver in preparation to add
DisplayPort support as well as some refactoring and cleanup.
Finally, all output drivers are converted to runtime PM, which greatly
simplifies the handling of clocks and resets.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJXh5n1AAoJEN0jrNd/PrOh+KcP/0SLO9UKvGBsfD0EFvkxx/NV
VZvqCWP0ARCGDAZn890O4sqwgHdRDF+hp0HcUt8wDt4o3VTYJIdifr/5tunOZ6+w
1IatWrjJjpyvZs9bveEvtJ8Hbkq5h0esA1StcqheRUiE0o+uQppdWO1NLO+HxssQ
f4qV4GQ7trJQdjr9OGfGJigsvOjwGVbPL7CRrKKLmbfTiqy9zhi5bOyUfojtMEL6
BvH9RMqC0ke70sGtcPgigbL7wgnbkH0uR3sV5TwU5dErrvh0tnhYU1a1ednPotJW
z56+W8hWfC3XLIiU9mju1l+3sQA0BuS9ZQ+6VhdRTKxv85CUI5dUKT0/h5BtRrK9
0XgPwrn4YpAr17oFEGdqFPhefkDkbb/1WrWmgUEi8/YaimdCXNkf8rILZvWUVQdt
q9GbbmEiGNR2FvBEN7s/nT96E5XEzfLTjOzTOP0c5RF9cOK+Ul9t0t44eBn4Wqbk
x6rTv37eieK5RVYd24xKKnzf5uSMpU+RTea4Vpr0xdH6glGcrTJ5ogub0iIsY0Jn
A9M1pKadQvu//95ZzGWEyrqAr66cDG8vGjZn9z24PRaNZEbzvY3ohj2/qOSQoRFY
HPmswshI0DnyFPWmdhhlPy3di0zNDP6kfPo6NhotoAl2Uwd+RrY/VyWjDG0dwV0R
nSkcnGES5hnf3gguXEmO
=7xlG
-----END PGP SIGNATURE-----
Merge tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.8-rc1
This set of changes contains a bunch of cleanups to the host1x driver as
well as the addition of a pin controller for DPAUX, which is required by
boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C
mode (for HDMI and DDC).
Included is also a bit of rework of the SOR driver in preparation to add
DisplayPort support as well as some refactoring and cleanup.
Finally, all output drivers are converted to runtime PM, which greatly
simplifies the handling of clocks and resets.
* tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits)
drm/tegra: sor: Reject HDMI 2.0 modes
drm/tegra: sor: Prepare for generic PM domain support
drm/tegra: dsi: Prepare for generic PM domain support
drm/tegra: sor: Make XBAR configurable per SoC
drm/tegra: sor: Use sor1_src clock to set parent for HDMI
dt-bindings: display: tegra: Add source clock for SOR
drm/tegra: sor: Implement sor1_brick clock
drm/tegra: sor: Implement runtime PM
drm/tegra: hdmi: Implement runtime PM
drm/tegra: dsi: Implement runtime PM
drm/tegra: dc: Implement runtime PM
drm/tegra: hdmi: Enable audio over HDMI
drm/tegra: sor: Do not support deep color modes
drm/tegra: sor: Extract tegra_sor_mode_set()
drm/tegra: sor: Split out tegra_sor_apply_config()
drm/tegra: sor: Rename tegra_sor_calc_config()
drm/tegra: sor: Factor out tegra_sor_set_parent_clock()
drm/tegra: dpaux: Add pinctrl support
dt-bindings: Add bindings for Tegra DPAUX pinctrl driver
drm/tegra: Prepare DPAUX for supporting generic PM domains
...
Please consider merging this tag, which contains the v4 misc fixes and add RK3399 eDP support patches[0] I sent on 2016-06-29, rebased onto v4.7-rc5.
* 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux:
dt-bindings: analogix_dp: rockchip: correct the wrong compatible name
drm/rockchip: analogix_dp: introduce the pclk for grf
drm/bridge: analogix_dp: fix no drm hpd event when panel plug in
drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode
drm/rockchip: analogix_dp: correct the connector display color format and bpc
drm/bridge: analogix_dp: passing the connector as an argument in .get_modes()
drm/rockchip: analogix_dp: make panel detect to an optional action
drm/rockchip: analogix_dp: add rk3399 eDP support
drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
drm/rockchip: analogix_dp: split the lcdc select setting into device data
- atomic mode setting conversion
- replace DMFC FIFO allocation mechanism with a fixed allocation
that is good enough for all cases
- support for external bridges connected to parallel-display
- improved error handling in imx-ldb, imx-tve, and parallel-display
- some code cleanup in imx-tve
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJXh1raAAoJEFDCiBxwnmDrWDIQALgkGU+38W6zspoNI1n317wy
QiPk/B7j56Um2w/qw8IgAm+pXcps3g1cGVc0zXlXsF2Kft7FmbNPll5qTFrgXc+c
odP2aOx4znFOPmMYuODKHL4GEG7F7qk1f/cVs4APZf0dupLEcxYsUHnTN/Z90hd7
JmPdbXMsC0ay/ZAvbtPTpf7BDkeUUF6vCM1JriJ0ngBlIq4LOocQOZGdA66zAnJM
fxVxQ/HRGEIIn8YMwk+Rbbj6iVTl0quOcXchILtBB6JK0OR3J0HUKDOS1hzLI29E
Y0kgZSDzQcE1U2BcHTtIlpa9hWqySVhv6tRFx2FVivy+H3wa2sQZ+rvpQKV6jNlx
0gme4b1GkX76oxhtg5nwj+Vhxazo1ANj+ezXJclr2FT2P3flGnzlBK9xQN68jOGy
cJEGKcFrO7BbgF22UP3MKCHl6A74NuutFQ/SR9ZetspFtEmzmUeae8shhJw0FVUr
ent5IeWeeZBC4KmtgIBtBwKM3PB/O7vmFVJGP47Y3uMR5qhzxUBQKTnoBIuFkgjz
3K1kDqR0AimDq+M9n8nnHXihYffFNtb4gBzbTaZTZUxYfsz8Uoe/kBpe2Gc8dcxq
KYTCbJFZ49H7on5/wDD3P98m7rEnvWAcP3k/ZzS2tBhNTAaQprkq+tQL7+JFpXcV
qTgSznrXDVlpgVXm4PnI
=lWas
-----END PGP SIGNATURE-----
Merge tag 'imx-drm-next-2016-07-14' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm updates
- atomic mode setting conversion
- replace DMFC FIFO allocation mechanism with a fixed allocation
that is good enough for all cases
- support for external bridges connected to parallel-display
- improved error handling in imx-ldb, imx-tve, and parallel-display
- some code cleanup in imx-tve
* tag 'imx-drm-next-2016-07-14' of git://git.pengutronix.de/git/pza/linux:
drm/imx: parallel-display: add bridge support
drm/imx: parallel-display: check return code from of_get_drm_display_mode()
gpu: ipu-v3: ipu-dc: don't bug out on invalid bus_format
drm/imx: imx-tve: fix the error message
drm/imx: imx-tve: remove unneeded 'or' operation
drm/imx: imx-tve: check the value returned by regulator_set_voltage()
drm/imx: imx-ldb: check return code on panel attach
drm/imx: turn remaining container_of macros into inline functions
drm/imx: store internal bus configuration in crtc state
drm/imx: remove empty mode_set encoder callbacks
drm/imx: atomic phase 3 step 3: Advertise DRIVER_ATOMIC
drm/imx: atomic phase 3 step 2: Legacy callback fixups
drm/bridge: dw-hdmi: Remove the legacy drm_connector_funcs structure
drm/imx: atomic phase 3 step 1: Use atomic configuration
drm/imx: Remove encoders' ->prepare callbacks
drm/imx: atomic phase 2 step 2: Track plane_state->fb correctly in ->page_flip
drm/imx: atomic phase 2 step 1: Wire up state ->reset, ->duplicate and ->destroy
drm/imx: atomic phase 1: Use transitional atomic CRTC and plane helpers
gpu: ipu-v3: ipu-dmfc: Use static DMFC FIFO allocation mechanism
drm/imx: ipuv3 plane: Check different types of plane separately
The current output code only supports connection to drm panels.
Add code to support drm bridge, to support connections to
external connectors.
Signed-off-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
This patch rework the output code to add of_graph dt binding support
for panel device and also keeps the backward compatibility
Signed-off-by: Meng Yi <meng.yi@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
of_node_put needs to be called when the device node which is got
from of_parse_phandle has finished using, but current code only
calls it at error path, fix it by adding it at correct code path.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
We don't use it in shader validation currently, so it had no effect,
but best to fix it anyway in case we do some day.
Signed-off-by: Eric Anholt <eric@anholt.net>
Userspace needs to know if it can create shaders that do branching.
Otherwise, for backwards compatibility with old kernels it needs to
lower if statements to conditional assignments.
Signed-off-by: Eric Anholt <eric@anholt.net>
We're already checking that branch instructions are between the start
of the shader and the proper PROG_END sequence. The other thing we
need to make branching safe is to verify that the shader doesn't read
past the end of the uniforms stream.
To do that, we require that at any basic block reading uniforms have
the following instructions:
load_imm temp, <next offset within uniform stream>
add unif_addr, temp, unif
The instructions are generated by userspace, and the kernel verifies
that the load_imm is of the expected offset, and that the add adds it
to a uniform. We track which uniform in the stream that is, and at
draw call time fix up the uniform stream to have the address of the
start of the shader's uniforms at that location.
Signed-off-by: Eric Anholt <eric@anholt.net>
This isn't used yet, it's just a first step toward loop validation.
During the main parsing of instructions, we need to know when we hit a
new basic block so that we can reset validated state.
v2: Fix a stray semicolon after an if block. (caught by kbuild test).
Signed-off-by: Eric Anholt <eric@anholt.net>
fix the build
Signed-off-by: Slava Grigorev <slava.grigorev@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sometimes, driver can not return from fence waiting when doing VCE ring
ib test. The issue is a asic special and random issue. so adjust VCE suspend
and resume sequence.
Signed-off-by: JimQu <Jim.Qu@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The pp_tables_get_response_times function will be used on iceland HW
mananger.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The return value 0 (false) means fail to find GPIO in
atomctrl_get_pp_assign_pin. "-1" returns true as bool actually.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The atomctrl_get_voltage_evv function will be used on iceland HW
manager.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The ucode_start_address would be used on powerplay of iceland.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
SDMA firmware will be loaded by SMU manager if powerplay is enabled.
So it needn't load at SDMA.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rename smumgr.h to smum.h, because smum.h is to align with the dpm of
other chips and we will use "iceland_smumgr" at powerplay in following
patches.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Still some stability issues under certain workloads.
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Currently enabling Nouveau DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Currently enabling ATMEL HLCDC DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Currently enabling R-Car DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Currently enabling Rockchip DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Some Kabylake SKUs are going to use Kabypoint PCH.
It is mainly for Halo and DT ones.
>From our specs it doesn't seem that KBP brings
any change on the display south engine. So let's consider
this as a continuation of SunrisePoint, i.e., SPT+.
Since it is easy to get confused by a letter change:
KBL = Kabylake - CPU/GPU codename.
KBP = Kabypoint - PCH codename.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96826
Link: http://patchwork.freedesktop.org/patch/msgid/1467418032-15167-1-git-send-email-rodrigo.vivi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 22dea0be50)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
This patch enables a workaround for a mid thread preemption
issue where a hardware timing problem can prevent the
context restore from happening, leading to a hang.
v2: move to gen9_init_workarounds (Arun)
v3: move to start of gen9_init_workarounds (Arun)
Signed-off-by: Tim Gore <tim.gore@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465816501-25557-1-git-send-email-tim.gore@intel.com
(cherry picked from commit a8ab5ed5e1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.
v2: proper workaround name
References: HSD#2227109, HSDES#1404569388
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-27-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 031cd8c85a)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.
v2: use correct workaround name
v3: split out overlapping wa for corruption avoidance (Ville)
References: HSD#2137218, HSD#2227171, HSD#2136579, BSID#883
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-26-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 303d4ea522)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
According to bspec this prevents screen corruption when fbc is
used.
v2: This workaround has a name, use it (Ville)
v3: remove bogus gen check on ilk/vlv wm path (Ville)
References: HSD#2135555, HSD#2137270, BSID#562
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-25-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 0f78dee6f0)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.
v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-22-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 590e8ff04b)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
v4: Split out the skl part in separate commit for easier backport
References: HSD#2227156, HSD#2227050
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-20-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 4de5d7ccbc)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Bspec states that we need to turn off dynamic credit
sharing on kbl revid a0 and b0. This happens by writing bit 28
on 0x4ab8.
References: HSD#2225601, HSD#2226938, HSD#2225763
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-15-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit c0b730d572)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Extend the scope of this workaround, already used in skl,
to also take effect in kbl.
v2: Fix KBL_REVID_E0 (Matthew)
References: HSD#2132677
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-12-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit fe90581987)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Add this workaround for kbl revid A0 only.
v2: rebase
v3: carve out a non related workaround (Chris)
References: HSD#1911714
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-9-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 8401d42fd5)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.
v2: Don't add revid checks to gen9 init workarounds (Arun)
References: HSD#2126660
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-8-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit e587f6cb0a)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Past evidence with system hangs and hsds tie
WaForceEnableNonCoherent and WaDisableHDCInvalidation to
WaForceContextSaveRestoreNonCoherent. Documentation
states that WaForceContextSaveRestoreNonCoherent would
not be needed on skl past E0 but evidence proved otherwise. See
commit <510650e8b2ab> ("drm/i915/skl: Fix spurious gpu hang with gt3/gt4
revs"). In this scope consider kbl to be skl with a bigger revision than
E0 so play it safe and bind these two workarounds to the
WaForceContextSaveRestoreNonCoherent, and apply to all gen9.
v2: fix comment (Matthew)
References: HSD#2134449, HSD#2131413
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-7-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit bbaefe72a0)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
We need this for kbl a0 boards. Note that this should be also
for bxt A0 but we omit that on purpose as bxt A0's are
out of fashion already.
References: HSD#1912158, HSD#4393097
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-5-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 6e4f10c33a)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
References: HSD#2227156, HSD#2227050
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-2-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit eee8efb02a)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Kernel only need to add a register to HW whitelist, required for a
preemption related issue.
Reference: HSD#2131039
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465203169-16591-1-git-send-email-arun.siluvery@linux.intel.com
(cherry picked from commit 6bb6285582)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Found this while browsing Bspec. Looks like it applies to both skl and
kbl.
v2: Also for bxt (Art).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Cc: "Runyan, Arthur J" <arthur.j.runyan@intel.com>
Reviewed-by: Sonika Jindal<sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463642060-30728-1-git-send-email-daniel.vetter@ffwll.ch
(cherry picked from commit dc00b6a07c)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
of_node_put needs to be called when the device node which is got
from of_parse_phandle has finished using.
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
of_node_put needs to be called when the device node which is got
from of_parse_phandle has finished using.
Cc: Joonyoung Shim <jy0922.shim@samsung.com>
Cc: Seung-Woo Kim <sw0312.kim@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
of_node_put needs to be called when the device node which is got
from of_parse_phandle has finished using.
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
of_node_put needs to be called when the device node which is got
from of_parse_phandle has finished using.
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
This pull request adds to the rework patch series for IOMMU
integration to support ARM64bit architecture with DMA-IOMMU
glue code.
With this patch series, Exynos DRM works well on Exynos5433 SoC
with IOMMU enabled.
* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos:
drm/exynos: iommu: add support for ARM64 specific code for IOMMU glue
drm/exynos: iommu: move ARM specific code to exynos_drm_iommu.h
drm/exynos: iommu: remove unused entries from exynos_drm_private strcuture
drm/exynos: iommu: add a check if all sub-devices have iommu controller
drm/exynos: iommu: move dma_params configuration code to separate functions
vblank timestamping, and a couple of small cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCgAGBQJXhUULAAoJELXWKTbR/J7oZ1oQAKnTTJlnCbaSNrWbRBUuaMtO
S2RQKyMI2LOpf4XE13cNHm0IaYNOw6hJIXlnxeuzHbQSGvOrHnabluZuvAfLa3OQ
4bb8K0elWsPRbtmx2L8DjncLCmmmOsbczrTwo3efq70XZs4PyaCp2vHpCU8kI7HJ
xO/fk6E8sYDPFCxZxb82C7LTSjQBlPn58dD+cEFg1kGILOhyR1eZwRj8e4netjKU
gN/059R6VPPor+I8oIMrqoHAxAlZUGnVPsK/1rgR5cfxlC1NPKU71eI7xiBLNclt
86BcvU/LuwAYt81UirnGTQU/m47dCMK4mmpzD/9EgVW/KTUPLPubML+u9fL67+B4
BJ7T7N4t7APblqkO/iI9DcTAkZNmydq4sdsfDdXcVZ3umDTNpmb/PQuq+rFEc1CZ
qsBw13kJ4bHBYUpZvrxuCesSRLpXhUiSOg/uVnRHTdiALZqQQyzQlnw6Q4GCMKiz
R99/k4/7/cAgQkGElwLeHR8Aw0r26m+X4pnLN9lrafjQjlH04CcuvFwlak28jnit
Oi0eZ0VD9RTHwPzUIoe4M32Q/7oAe7y5b7gCNPbM/0s56WQv+cIHi7CdgdIYtUWs
BIyeBTzpLvzkEvrEMYoipgpv3scbudMssTd3bo8gsdOu0tllBzi59Poo5hl6pQbs
lseJ7LavmK5sPDPsIZb3
=aF3C
-----END PGP SIGNATURE-----
Merge tag 'drm-vc4-next-2016-07-12' of https://github.com/anholt/linux into drm-next
This pull request brings in new vc4 plane formats for Android, precise
vblank timestamping, and a couple of small cleanups.
* tag 'drm-vc4-next-2016-07-12' of https://github.com/anholt/linux:
drm/vc4: remove redundant ret status check
drm/vc4: Implement precise vblank timestamping.
drm/vc4: Bind the HVS before we bind the individual CRTCs.
gpu: drm: vc4_hdmi: add missing of_node_put after calling of_parse_phandle
drm: vc4: enable XBGR8888 and ABGR8888 pixel formats
drm/vc4: clean up error exit path on failed dpi_connector allocation
A bunch of vmwgfx fixes that fix a black screen issue on latest distros/hw combos.
* 'drm-vmwgfx-fixes' of git://people.freedesktop.org/~syeh/repos_linux:
drm/vmwgfx: Fix error paths when mapping framebuffer
drm/vmwgfx: Fix corner case screen target management
drm/vmwgfx: Delay pinning fbdev framebuffer until after mode set
drm/vmwgfx: Check pin count before attempting to move a buffer
drm/ttm: Make ttm_bo_mem_compat available
drm/vmwgfx: Add an option to change assumed FB bpp
drm/vmwgfx: Work around mode set failure in 2D VMs
drm/vmwgfx: Add a check to handle host message failure
- select igt testing depencies for CONFIG_DRM_I915_DEBUG (Chris)
- track outputs in crtc state and clean up all our ad-hoc connector/encoder
walking in modest code (Ville)
- demidlayer drm_device/drm_i915_private (Chris Wilson)
- thundering herd fix from Chris Wilson, with lots of help from Tvrtko Ursulin
- piles of assorted clean and fallout from the thundering herd fix
- documentation and more tuning for waitboosting (Chris)
- pooled EU support on bxt (Arun Siluvery)
- bxt support is no longer considered prelimary!
- ring/engine vfunc cleanup from Tvrtko
- introduce intel_wait_for_register helper (Chris)
- opregion updates (Jani Nukla)
- tuning and fixes for wait_for macros (Tvrkto&Imre)
- more kabylake pci ids (Rodrigo)
- pps cleanup and fixes for bxt (Imre)
- move sink crc support over to atomic state (Maarten)
- fix up async fbdev init ordering (Chris)
- fbc fixes from Paulo and Chris
* tag 'drm-intel-next-2016-07-11' of git://anongit.freedesktop.org/drm-intel: (223 commits)
drm/i915: Update DRIVER_DATE to 20160711
drm/i915: Select DRM_VGEM for igt
drm/i915: Select X86_MSR for igt
drm/i915: Fill unused GGTT with scratch pages for VT-d
drm/i915: Introduce Kabypoint PCH for Kabylake H/DT.
drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
drm/i915: Check for invalid cloning earlier during modeset
drm/i915: Simplify hdmi_12bpc_possible()
drm/i915: Kill has_dsi_encoder
drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/
drm/i915: Replace some open coded intel_crtc_has_dp_encoder()s
drm/i915: Kill has_dp_encoder from pipe_config
drm/i915: Replace manual lvds and sdvo/hdmi counting with intel_crtc_has_type()
drm/i915: Unify intel_pipe_has_type() and intel_pipe_will_have_type()
drm/i915: Add output_types bitmask into the crtc state
drm/i915: Remove encoder type checks from MST suspend/resume
drm/i915: Don't mark eDP encoders as MST capable
drm/i915: avoid wait_for_atomic() in non-atomic host2guc_action()
drm/i915: Group the irq breadcrumb variables into the same cacheline
drm/i915: Wake up the bottom-half if we steal their interrupt
...
I recovered dri-devel backlog from my vacation, more misc stuff:
- of_put_node fixes from Peter Chen (not all yet)
- more patches from Gustavo to use kms-native drm_crtc_vblank_* funcs
- docs sphinxification from Lukas Wunner
- bunch of fixes all over from Dan Carpenter
- more follow up work from Chris register/unregister rework in various
places
- vgem dma-buf export (for writing testcases)
- small things all over from tons of different people
* tag 'topic/drm-misc-2016-07-14' of git://anongit.freedesktop.org/drm-intel: (52 commits)
drm: Don't overwrite user ioctl arg unless requested
dma-buf/sync_file: improve Kconfig description for Sync Files
MAINTAINERS: add entry for the Sync File Framework
drm: Resurrect atomic rmfb code
drm/vgem: Use PAGE_KERNEL in place of x86-specific PAGE_KERNEL_IO
qxl: silence uninitialized variable warning
qxl: check for kmap failures
vga_switcheroo: Sphinxify docs
drm: Restore double clflush on the last partial cacheline
gpu: drm: rockchip_drm_drv: add missing of_node_put after calling of_parse_phandle
gpu: drm: sti_vtg: add missing of_node_put after calling of_parse_phandle
gpu: drm: sti_hqvdp: add missing of_node_put after calling of_parse_phandle
gpu: drm: sti_vdo: add missing of_node_put after calling of_parse_phandle
gpu: drm: sti_compositor: add missing of_node_put after calling of_parse_phandle
drm/tilcdc: use drm_crtc_handle_vblank()
drm/rcar-du: use drm_crtc_handle_vblank()
drm/nouveau: use drm_crtc_handle_vblank()
drm/atmel: use drm_crtc_handle_vblank()
drm/armada: use drm_crtc_handle_vblank()
drm: make drm_vblank_count_and_time() static
...
I've also realized that a pile of hang fixes for kbl landed in next, and
no one thought of backporting it to 4.7 - kbl has lost prelim_hw_support
tagging in 4.7-rc1 already. Mika is prepping a topic branch for those,
will send you a separate pull request since it's quite a bit (but should
be all well restricted to kbl code, so similar to polaris in amdgpu).
* tag 'drm-intel-fixes-2016-07-14' of git://anongit.freedesktop.org/drm-intel:
drm/i915: Ignore panel type from OpRegion on SKL
drm/i915: Update ifdeffery for mutex->owner
This is a minor interface change, but clearly won't break anything.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
A little fallout from "drm/amdgpu: sanitize fence numbers", we
sometimes need to signal all fences in the ring.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Otherwise we can run into the following situation:
1. Process A grabs ID 1 for ring 0.
2. Process B grabs ID 1 for ring 0.
3. Process A grabs ID 1 for ring 1.
4. Process A tries to reuse ID1 for ring 0 but things he doesn't need to flush.
v2: check the context of the flush fence instead of messing with the owner field.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We already waited for the fence, so waiting for the registers
is completely pointless and just copy & pasted from the ring test.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reference should be taken when we make the assignment, not anywhere else.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cleanup 80 chars limit.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We always used updated firmware for amdgpu, so this actually should work fine.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fix 80 chars issues and remove some dead code as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Looks like the VCE block sometimes still sends nonsense
fence numbers on startup.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reduces the argument count for some of the functions, and will be used
more with the upcoming looping support.
Signed-off-by: Eric Anholt <eric@anholt.net>
As I extend the driver to support different V3D revisions, userspace
needs to know what version it's targeting. This is most easily
detected using the V3D identity registers.
v2: Make sure V3D is runtime PM on when reading the registers.
v3: Switch to a 64-bit param value (suggested by Rob Clark in review)
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
Reviewed-by: Rob Clark <robdclark@gmail.com> (v3, over irc)
Dell XPS 13 9350 apparently doesn't like it when we use the panel type
from OpRegion. The OpRegion panel type (0) tells us to use use low
vswing for eDP, whereas the VBT panel type (2) tells us to use normal
vswing. The problem is that low vswing results in some display flickers.
Since no one seems to know how this stuff is supposed to be handled,
let's just ignore the OpRegion panel type on SKL for now.
v2: Print the panel type correctly in the debug output
Reported-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Cc: James Bottomley <James.Bottomley@HansenPartnership.com>
Cc: drm-intel-fixes@lists.freedesktop.org
References: https://lists.freedesktop.org/archives/intel-gfx/2016-June/098826.html
Fixes: a05628195a ("drm/i915: Get panel_type from OpRegion panel details")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1468324837-29237-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
(cherry picked from commit bb10d4ec3b)
[danvet: Fix up cherry-pick conflict with an s/dev_priv/dev/.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Prior to gen6 we didn't have per-ring IMR registers, which means that
since commit 61ff75ac20 ("drm/i915: Simplify enabling
user-interrupts with L3-remapping") we're now masking off all interrupts
when init_render_ring() gets called. That's rather rude. Let's limit
the ring IMR frobbing to machines that actually have the per-ring IMR
registers.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 61ff75ac20 ("drm/i915: Simplify enabling user-interrupts with L3-remapping")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1468340687-3596-1-git-send-email-ville.syrjala@linux.intel.com
Reviewd-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 035ea405c9)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Never go to sleep waiting on the GPU without first ensuring that we will
get woken up.
We have a choice of queuing the hangcheck before every schedule() or the
first time we wakeup. In order to simply accommodate both the signaler
and the ordinary waiter, move the queuing to the common point of
enabling the irq. We lose the paranoid safety of ensuring that the
hangcheck is active before the sleep, but avoid code duplication (and
redundant hangcheck queuing).
Testcase: igt/prime_busy
Fixes: c81d46138d ("drm/i915: Convert trace-irq to the breadcrumb waiter")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1468055535-19740-2-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
(cherry picked from commit 232af392fd)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
In commit 7608a43d8f ("locking/mutexes: Use MUTEX_SPIN_ON_OWNER when
appropriate") the owner field in the mutex was updated from being
dependent upon CONFIG_SMP to using optimistic spin. Update our peek
function to suite.
Fixes:7608a43d8f2e ("locking/mutexes: Use MUTEX_SPIN_ON_OWNER...")
Reported-by: Hong Liu <hong.liu@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1468244777-4888-1-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
(cherry picked from commit 4f074a5393)
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Enabling HDMI 2.0 modes requires extra programming and will not work
with the current driver, so reject all those modes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SOR driver for Tegra requires the SOR power partition to be enabled.
Now that Tegra supports the generic PM domain framework we manage the
SOR power partition via this framework. However, the sequence for
gating/ungating the SOR power partition requires that the SOR reset is
asserted/de-asserted at the time the SOR power partition is
gated/ungated, respectively. Now that the reset control core assumes
that resets are exclusive, the Tegra generic PM domain code and the SOR
driver cannot request the same reset unless we mark the reset as shared.
Sharing resets will not work in this case because we cannot guarantee
that the reset will be asserted/de-asserted at the appropriate time.
Therefore, given that the Tegra generic PM domain code will handle the
resets, do not request the reset in the SOR driver if the SOR device has
a PM domain associated.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DSI driver for Tegra requires the SOR power partition to be enabled.
Now that Tegra supports the generic PM domain framework we manage the
SOR power partition via this framework. However, the sequence for
gating/ungating the SOR power partition requires that the DSI reset is
asserted/de-asserted at the time the SOR power partition is
gated/ungated, respectively. Now that the reset control core assumes
that resets are exclusive, the Tegra generic PM domain code and the DSI
driver cannot request the same reset unless we mark the reset as shared.
Sharing resets will not work in this case because we cannot guarantee
that the reset will be asserted/de-asserted at the appropriate time.
Therefore, given that the Tegra generic PM domain code will handle the
resets, do not request the reset in the DSI driver if the DSI device has
a PM domain associated.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When running in HDMI mode, the sor1 IP block needs to use the sor1_src
as parent clock, and in turn configure the sor1_src to use pll_d2_out0
as its parent.
Signed-off-by: Thierry Reding <treding@nvidia.com>
sor1_brick is a clock that can be used as a source for the sor1 clock.
The registers to control the clock output are part of the sor1 IP block
and hence the sor driver is the best place to implement it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Currently, we completely ignore the user when it comes to the in/out
direction of the ioctl argument, as we simply cannot trust userspace.
(For example, they might request a copy of the modified ioctl argument
when the driver is not expecting such and so leak kernel stack.)
However, blindly copying over the target address may also lead to a
spurious EFAULT, and a failure after the ioctl was completed
successfully. This is important in order to avoid an ABI break when
extending an ioctl from IOR to IORW. Similar to how we only copy the
intersection of the kernel arg size and the user arg size, we only want
to copy back the kernel arg data iff both the kernel and userspace
request the copy.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1468335590-21023-1-git-send-email-chris@chris-wilson.co.uk
Here's an initial drm-next pull for nouveau 4.8, highlights:
- GK20A/GM20B volt and clock improvements.
- Initial support for GP100/GP104 GPUs, GP104 will not yet support
acceleration due to NVIDIA having not released firmware for them as of yet.
* 'linux-4.8' of git://github.com/skeggsb/linux: (97 commits)
drm/nouveau/bus: remove cpu_coherent flag
drm/nouveau/ttm: remove special handling of coherent objects
drm/nouveau: check for supported chipset before booting fbdev off the hw
drm/nouveau/ce/gp104: initial support
drm/nouveau/fifo/gp104: initial support
drm/nouveau/disp/gp104: initial support
drm/nouveau/dma/gp104: initial support
drm/nouveau/ltc/gp104: initial support
drm/nouveau/ibus/gp104: initial support
drm/nouveau/i2c/gp104: initial support
drm/nouveau/gpio/gp104: initial support
drm/nouveau/fuse/gp104: initial support
drm/nouveau/bus/gp104: initial support
drm/nouveau/bar/gp104: initial support
drm/nouveau/mmu/gp104: initial support
drm/nouveau/fb/gp104: initial support
drm/nouveau/imem/gp104: initial support
drm/nouveau/devinit/gp104: initial support
drm/nouveau/bios/gp104: initial support
drm/nouveau/tmr/gp104: initial support
...
This flag's only remaining function is to ignore the uncached flag for
BOs on coherent architectures.
However the reason for allocating an object uncache on a non-coherent
architecture (namely because the cost of doing explicit flushes/
invalidations is higher than the benefit of caching the data because
accesses are few and far between) should also apply on architectures for
which coherency is maintained implicitly. Thus allocate coherent objects
as uncached on all architectures.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
TTM-allocated coherent objects were populated using the DMA API and
accessed using the mapping it returned to workaround coherency
issues. These issues seem to have been solved, thus remove this extra
case to handle and use the regular kernel mapping functions.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Due to the GPU preventing us from touching NV_PLTCG_LTCS_LTSS_CBC_BASE,
we cannot provide CBC/ZBC support without signed PMU firmware to handle
the task for us...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
GP100 still supports the previous generations' page table layout, which
we will temporarily make use of here.
Proper support for the new MMU layout requires some rework to the common
MMU code, which is in progress.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
GFxxx/GM1xx support the selection of 64/128KiB big pages globally.
GM2xx supports the same, as well as another mode where the page size
can be selected per-instance.
We default to 128KiB pages (With per-instance for GM200, but the current
code selects 128KiB there already) as the MMU code isn't currently able
to handle otherwise.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Fixes the second DVI output on Quadro FX380.
Thanks to NVIDIA for providing the details on the full workaround.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Makes common the code that was previously used by the PMU table parsing,
as it appears other tables need this too.
Not much of an idea what this is all about...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Some VBIOS have separate tables for each link of a given output path,
which means we have to specify the specific link we're using instead
of all possible links.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Corresponds with GT215. Don't rely on the lock test logic being
unconditionally enabled, and disable test logic when done (presumably
to save power).
v2: Remove warning, nvkm_msec already warns on time-out
Signed-off-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Defer the loading of firmware files to the chip-specific part of secure
boot. This allows implementations to retry loading firmware if the first
attempt failed ; for the GM200 implementation, this happens when trying
to reset a falcon, typically in reaction to GR init.
Firmware loading may fail for a variety of reasons, such as the
filesystem where they reside not being ready at init time. This new
behavior allows GR to be initialized the next time we try to use it if
the firmware has become available.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Make it possible to call gm20x_secboot_prepare_blobs() several times
after either success or failure without re-building already existing
blobs. The function will now try to load firmware files that have
previously failed before returning success.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Handle and propagate secure boot errors. Failure to do so results in
Nouveau incorrectly believing init has succeeded and a completely
black display during boot. If we propagate the error, GR init will fail
and the user will at least have a working display.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Some members were documented in the wrong structure.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
We shouldn't set voltages below the min or above the max voltage the gpu is
able to set, so save the range for future lookups.
Signed-off-by: Karol Herbst <karolherbst@gmail.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This patch adds support for advanced features supported by the
Noise-Aware PLL of Maxwell. Glitchless switch allows the PL field to be
updated without disabling the PLL first if the SYNC_MODE bit of the CFG
register is set.
More significantly, DFS allows the PLL to monitor the actual input
voltage and to dynamically lower the output frequency accordingly. This
allows the clock to be more tolerant of lower voltages.
These improvements are only supported for Tegra speedos >= 1.
Also add the voltage table that is suitable for GM20B's NAPLL. This
change needs to be done atomically for the right voltages to be used by
the clock driver.
v2. Fix build on non-Tegra platforms
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Strip the _ prefix off the gk20a clock constructor.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Split the MNP programming function into two functions for the cases
where we allow sliding or not, instead of making it take a parameter for
this. This results in less conditionals in the code and makes it easier
to read.
Also make the MNP programming functions take the PLL parameters as
arguments, and move bits of code to more relevant places (previous
programming tended to be just-in-time, which added more conditionnals in
the code).
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Use a dedicated function instead of always calculating n_lo on the fly.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Make functions manipulating PLL settings take them as an argument,
instead of assuming we want to work on the copy in the gk20a_clk
structure. This makes these functions more flexible, which we will need
in GM20B.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add relevant functions to work with the gk20a_pll structure and use them
where they ought to be instead of directly manipulating registers.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Move variables declarations to their actual scope of use, and simplify
code a bit.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Slide setup needs to be performed only once, during init. Also
use the proper parameters for different clock speeds.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Chips may be characterized for a minimum voltage. Support this extra
parameter and select the appropriate minimum voltage for the detected
GPU speedo.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Strip the _ prefix off the gk20a volt constructor.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Give a name to this constant so we at least get an idea of what it is
for.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Nobody else is using these, so make them private.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
The GPU speedo ID is required to select the right clk/volt parameters on
GM20B.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
There are cases where subdevs need to perform additonal actions around
the master reset, so we want to expost the operations separately.
This commit also adds a flag to the NV_PMC_ENABLE bitfield definitions
which allow skipping the automatic reset() called from core/subdev.c.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* topic/vsp1: (36 commits)
[media] v4l: vsp1: wpf: Add flipping support
[media] v4l: vsp1: rwpf: Support runtime modification of controls
[media] v4l: vsp1: Simplify alpha propagation
[media] v4l: vsp1: clu: Support runtime modification of controls
[media] v4l: vsp1: lut: Support runtime modification of controls
[media] v4l: vsp1: Support runtime modification of controls
[media] v4l: vsp1: Add Cubic Look Up Table (CLU) support
[media] v4l: vsp1: lut: Expose configuration through a control
[media] v4l: vsp1: lut: Initialize the mutex
[media] v4l: vsp1: dl: Don't free fragments with interrupts disabled
[media] v4l: vsp1: Set entities functions
[media] v4l: vsp1: Don't create LIF entity when the userspace API is enabled
[media] v4l: vsp1: Don't register media device when userspace API is disabled
[media] v4l: vsp1: Base link creation on availability of entities
[media] media: Add video statistics computation functions
[media] media: Add video processing entity functions
[media] v4l: vsp1: sru: Fix intensity control ID
[media] v4l: vsp1: Stop the pipeline upon the first STREAMOFF
[media] v4l: vsp1: Constify operation structures
[media] v4l: vsp1: pipe: Fix typo in comment
...
This patch adds support for ARM 64bit architecture with IOMMU-DMA glue
code, so Exynos DRM can be now used on Exynos 5433 with IOMMU enabled.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
This patch moves all ARM 32bit DMA-mapping/IOMMU dependant code from
exynos_drm_iommu.c to .h, to let it compile conditionally and prepare
for adding support for other architectures/IOMMU glue code (like ARM
64bit with IOMMU-DMA glue). Later, when ARM 32bit and 64bit will be
unified, this code can be removed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
This patch removes unused entries from exynos_drm_private strcuture.
da_start/da_space_size were only used in drm_create_iommu_mapping()
function and never set to other value than the defaults. Instead use
default values directly in arm_iommu_create_mapping() call.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
This patch adds a check if all devices belonging to Exynos DRM have the
same dma_map_ops set. This is required to enable operation with IOMMU
enabled.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Move code for managing DMA max segment size parameter to separate
functions. This patch also replaces devm_kzalloc() with kzalloc() and
adds proper kfree call. devm_kzalloc() cannot be used for dma_params
structure, because it will be freed on driver remove not on device
release. This means in case of Exynos DRM being compiled as module and
loaded 2 times, a user-after-free issue will happen.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
This was somehow lost between v3 and the merged version in Maarten's
patch merged as:
commit f2d580b9a8
Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Date: Wed May 4 14:38:26 2016 +0200
drm/core: Do not preserve framebuffer on rmfb, v4.
Actual code copied from Maarten's patch, but with the slight change to
just use dev->mode_config.funcs->atomic_commit to decide whether to
use the atomic path or not.
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1465388359-8070-24-git-send-email-daniel.vetter@ffwll.ch
Lower modes on ADV7533 require lower number of DSI lanes for correct
operation. If ADV7533 is being used with 4 DSI lanes, then switch the
lanes to 3 when the target mode's pixel clock is less than 80 Mhz.
Based on patch by Andy Green <andy.green@linaro.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
ADV7533 provides an internal timing generator for certain modes that it
can't use the DSI clock directly.
We've observed that HDMI is more stable with the internal timing
generator, especially if there are instabilities in the DSI clock source.
The data spec also seems to recommend the usage of the timing generator
for all modes.
However, on some platforms, it's reported that enabling the timing
generator causes instabilities with the HDMI output.
Create a DT parameter that lets a platform explicitly disable the timing
generator. The timing generator is enabled by default.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
In order to pass DSI specific parameters to the DSI host, we need the
driver to create a mipi_dsi_device DSI device that attaches to the
host.
Use of_graph helpers to get the DSI host DT node. Create a MIPI DSI
device using this host. Finally, attach this device to the DSI host.
Populate DT parameters (number of data lanes for now) that are required
for DSI RX to work correctly. Hardcode few other parameters (rgb,
embedded_sync) for now.
Select DRM_MIPI_DSI config option only when ADV7533 support is enabled.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
ADV7533 is a DSI to HDMI encoder chip. It is a derivative of ADV7511,
with additional blocks to translate input DSI data to parallel RGB
data. Besides the ADV7511 I2C register map, it has additional registers
that require to be configured to activate the DSI Rx block.
Create a new config that enables ADV7533 support. Use DT compatible
strings to populate the ADV7533 type enum. Add minimal register
configurations belonging to the DSI/CEC register map. Keep the ADV7533
code in a separate file.
Originally worked on by Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
When the adv7511 i2c client doesn't have an interrupt line, we observe a
deadlock on caused by trying to lock drm device's mode_config.mutex twice
in the same context.
Here is the sequence that causes it:
ioctl DRM_IOCTL_MODE_GETCONNECTOR from userspace
drm_mode_getconnector (acquires mode_config mutex)
connector->fill_modes()
drm_helper_probe_single_connector_modes
connector_funcs->get_modes
adv7511_encoder_get_modes
adv7511_get_edid_block
adv7511_irq_process
drm_helper_hpd_irq_event (acquires mode_config mutex again)
In adv7511_irq_process, don't call drm_helper_hpd_irq_event when not
called from the interrupt handler. It doesn't serve any purpose there
anyway.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
The driver has been converted to use drm_bridge instead of
drm_i2c_slave_encoder. We can now move it to the bridge folder.
Create a separate folder since we already have a couple of files and
expect more when we support audio and ADV7533.
Rename the driver to adv7511_drv.c. This will come in handy later
when the driver module will need to be built from multiple object
files.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
We don't want to use the old i2c slave encoder interface anymore.
Remove that and make the i2c driver create a drm_bridge entity instead.
Converting to bridges helps because the kms drivers don't need to
exract encoder slave ops from this driver and use it within their
own encoder/connector ops.
The driver now creates its own connector when a kms driver attaches
itself to the bridge. Therefore, kms drivers don't need to create
their own connectors anymore.
The old encoder slave ops are now used by the new bridge and connector
entities.
The of_node member in drm_bridge is accessible only when CONFIG_OF is
enabled. The driver anyway only works only when OF is available. Make
the driver depend on OF in its Kconfig.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
of_get_drm_display_mode() may fail. Check its return code and bail out
on error.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
If imx-drm is combined with a bridge or panel that requests an
unsupported format, warn and use a default mapping instead of
hanging the machine. The worst that can happen here are wrong
colors.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
The error message should say "hsync" instead of "vsync" as
we have just checked the "fsl,hsync-pin" property.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
There is no need for doing an extra 'or' operation when reading
the return value from of_property_read_u32().
Just do a simple read instead.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
regulator_set_voltage() may fail, so we better check its return value
and propagate it in the case of error.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Check the return code on panel attach. Avoids a kernel crash later
on if the attach failed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
The internal bus configuration is imx-drm specific crtc state. Store it
in imx_crtc_state and let the encoder atomic_check callbacks determine
bus_flags, bus_format and the sync pins, possibly taking into account
the mode and the connector display info.
The custom imx_drm_encoder structure can be replaced again with
drm_encoder.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
With all the beforehand phases and steps done, we can adverstise DRIVER_ATOMIC.
Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Now that we can use atomic configurations, all the legacy callbacks
of CRTCs, encoders and connectors can be switched to the atomic version.
For the imx-ldb driver, there is a clock parent setting mismatch bewteen
->enable and ->disable after the switch, so a fixup is added. For the
imx-tve driver, since the encoder's callback ->dpms is replaced by
->disable, we need to move the setting for the IPU_CLK_EN bit(in register
TVE_COM_CONF_REG) from ->enable/->disable to ->mode_set, otherwise, the
relevant CRTC cannot be disabled correctly with a warning on DC stop timeout.
Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
There is no one using the legacy drm_connector_funcs structure since
the imx-drm has been converted to atomic, so we may remove it.
Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Replacing drm_crtc_helper_set_config() by drm_atomic_helper_set_config()
and converting the suspend/resume operations to atomic make us be able
to use atomic configurations. All of these allow us to remove the
crtc_funcs->mode_set callback as it is no longer used. Also, change
the plane_funcs->update/disable_plane callbacks from the transitional
version to the atomic version. Furthermore, switching to the pure atomic
version of set_config callback means that we may implement CRTC/plane
atomic checks by using the new CRTC/plane states instead of the legacy
ones and we may remove the private ipu_crtc->enabled state which was left
there for the transitional atomic helpers in phase 1. Page flip is also
switched to the atomic version. Last, the legacy function
drm_helper_disable_unused_functions() is removed from ->load in order
not to confuse the atomic driver.
Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
The main task of imx encoders' ->prepare callbacks is to set bus_format,
bus_flags, di_vsync_pin and di_hsync_pin. We may create a structure named
imx_encoder to cache them. The atomic encoder callback ->disable may
replace ->prepare later, so let's remove ->prepare.
Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Use drm_atomic_set_fb_for_plane() in the legacy ->page_flip path to track
the pointer plane_state->fb correctly.
Signed-off-by: Liu Ying <gnuiyl@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Rob Clark