2 Commits

Author	SHA1	Message	Date
Andrew Bresticker	88b4bd7071	clk: tegra: cclk_lp has a pllx/2 divider ... When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>	2014-02-17 16:18:28 +02:00
Peter De Schrijver	a7c8485a0e	clk: tegra: introduce common gen4 super clock ... Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>	2013-11-26 18:46:50 +02:00