This set does not include those for issues introduced during the merge
window. Fixes of those will follow in a future series.
* ad5064
- Make sure the local i2c_write returns 0 on success rather than the
number of bytes transfered. Otherwise we report an error on all writes.
- Fix a shift for ad5629 and ad5669 which gives incorrect DAC output on
these parts.
* ad7793
- The product ID on the datasheet is wrong. Fix it in the driver.
* IIO_DUMMY_EVGEN
- select IRQ_WORK as a dependency.
* lpc32xx
- make sure clock is prepared before enabling.
* si7020
- data byte order was reversed. Fix it.
* vf610
- Internal temperature calculation was wrong if a different
reference voltage was used. Now use a linear interpolation
function to make it work over the full range.
- Fix a division by zero in the case of a device tree property
not being present (same issue two fixes).
* xilinx XADC
- VREFN scale was wrong - fix it.
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Merge tag 'iio-fixes-for-4.4a' of ssh://ra.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus
Jonathan writes:
First set of IIO fixes for the 4.4 cycle.
This set does not include those for issues introduced during the merge
window. Fixes of those will follow in a future series.
* ad5064
- Make sure the local i2c_write returns 0 on success rather than the
number of bytes transfered. Otherwise we report an error on all writes.
- Fix a shift for ad5629 and ad5669 which gives incorrect DAC output on
these parts.
* ad7793
- The product ID on the datasheet is wrong. Fix it in the driver.
* IIO_DUMMY_EVGEN
- select IRQ_WORK as a dependency.
* lpc32xx
- make sure clock is prepared before enabling.
* si7020
- data byte order was reversed. Fix it.
* vf610
- Internal temperature calculation was wrong if a different
reference voltage was used. Now use a linear interpolation
function to make it work over the full range.
- Fix a division by zero in the case of a device tree property
not being present (same issue two fixes).
* xilinx XADC
- VREFN scale was wrong - fix it.
The scaling factor for VREFN is 3.0/4096 (not 1.0/4096), just as for
VREFP. This is not immediately obvious from the specification (Xilinx
UG480), but has been confirmed by Xilinx support.
Suggested-by: Hartmut Knaack <knaack.h@gmx.de>
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The driver currently registers a pair of irq handlers using
request_threaded_irq(), however the synchronization mechanism between the
hardirq and the threadedirq handler is a regular spinlock.
Unfortunately, this breaks PREEMPT_RT builds, where a spinlock can sleep,
and is thus not able to be acquired from a hardirq handler. This patch gets
rid of the threaded handler and pushes all interrupt handling into the
hardirq context, and uses request_irq().
To validate that this change has no impact on RT performance, here are
cyclictest values with no processes running:
$ sudo cyclictest -S -m -p 98
policy: fifo: loadavg: 0.00 0.01 0.05 1/174 2539
T: 0 ( 1405) P:98 I:1000 C:167010520 Min: 9 Act: 12 Avg: 12 Max: 75
T: 1 ( 1862) P:98 I:1500 C:111340339 Min: 9 Act: 12 Avg: 12 Max: 73
Then, all xadc raw handles were accessed in a continuous loop via
/sys/bus/iio/devices/iio:device0:
$ sudo cyclictest -S -m -p 98
policy: fifo: loadavg: 7.84 7.70 7.63 3/182 4260
T: 0 ( 2559) P:98 I:1000 C:241557018 Min: 11 Act: 18 Avg: 21 Max: 74
T: 1 ( 2560) P:98 I:1500 C:161038006 Min: 10 Act: 21 Avg: 20 Max: 73
Signed-off-by: Xander Huff <xander.huff@ni.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The VREFN channel is bipolar, not unipolar. Small negative values do
occur (e.g., -1mV), and unsigned conversion maps them incorrectly to
large positive values (about +1V), so fix this.
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The scaling factor for VREFP is 3.0/4096, not 1.0/4096; fix this to get
correct readings.
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
For the "vccaux" channel, read the VCCAUX register, not VCCINT.
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
We want the fixes in there, and it resolves a merge issue with
drivers/iio/accel/bma180.c
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
There is no need to init .owner field.
Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"
This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Convert a zero return value on error to a negative one, as returned
elsewhere in the function.
A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
(
if@p1 (\(ret < 0\|ret != 0\))
{ ... return ret; }
|
ret@p1 = 0
)
... when != ret = e1
when != &ret
*if(...)
{
... when != ret = e2
when forall
return ret;
}
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
argument has been ignored; adjust drivers accordingly
Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This driver
supports both interfaces and internally has a small abstraction layer that hides
the specifics of these interfaces from the main driver logic.
The ADC has a couple of internal channels which are used for voltage and
temperature monitoring of the FPGA as well as one primary and up to 16 channels
auxiliary channels for measuring external voltages. The external auxiliary
channels can either be directly connected each to one physical pin on the FPGA
or they can make use of an external multiplexer which is responsible for
multiplexing the external signals onto one pair of physical pins.
The voltage and temperature monitoring channels also have an event capability
which allows to generate a interrupt when their value falls below or raises
above a set threshold.
Buffered sampling mode is supported by the driver, but only for AXI-XADC since
the ZYNQ XADC interface does not have capabilities for supporting buffer mode
(no end-of-conversion interrupt). If buffered mode is supported the driver will
register two triggers. One "xadc-samplerate" trigger which will generate samples
with the configured samplerate. And one "xadc-convst" trigger which will
generate one sample each time the CONVST (conversion start) signal is asserted.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Greg Kroah-Hartman