There is nothing to prevent multiple commands being executed
simultaneously. Add a mutex to prevent this.
Fixes: 606397d67f ("fsi: Add ast2600 master driver")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Milton Miller <miltonm@us.ibm.com>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20201120004929.185239-1-joel@jms.id.au
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Systems have a line for restting the remote CFAM. This is not part of
the FSI master, but is associated with it, so it makes sense to include
it in the master driver.
This exposes a sysfs interface to reset the cfam, abstracting away the
direction and polarity of the GPIO, as well as the timing of the reset
pulse. Userspace will be blocked until the reset pulse is finished.
The reset is hard coded to be in the range of (900, 1000) us. It was
observed with a scope to regularly be just over 1ms.
If the device tree property is not preset the driver will silently
continue.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20200728025527.174503-6-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
For testing and hardware debugging a user may wish to override the
divisor at runtime. By setting fsi_master_aspeed.bus_div=N, the divisor
will be set to N, if 0 < N <= 0x3ff.
This is a module parameter and not a device tree option as it will only
need to be set when testing or debugging.
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20200728025527.174503-5-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
Testing of Tacoma has shown that the ASPEED master can be run at maximum
speed.
The exception is when wired externally with a cable, in which case we
use a divisor of two to ensure reliable operation.
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20200728025527.174503-4-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
Some FSI capable systems have internal FSI signals, and some have
external cabled FSI. Software can detect which machine this is by
reading a jumper GPIO, and also control which pins the signals are
routed to through a mux GPIO.
This attempts to find the GPIOs at probe time. If they are not present
in the device tree the driver will not error and continue as before.
The mux GPIO is owned by the FSI driver to ensure it is not modified at
runtime. The routing jumper obtained as non-exclusive to allow other
software to inspect it's state.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20200728025527.174503-3-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
Both the Aspeed and hub masters read back the link enable register
after enabling the link, but this is unnecessary, so remove it.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add the ability to disable a link with a boolean parameter to the
link_enable function. This is necessary so that the master can disable
links that it isn't using; for example, links to slaves that fail
initialization.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
In order to access more than the second hub link, 23-bit addressing is
required. The core provides the highest two bits of address as the slave
ID to the master.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Acked-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The data byte order selection registers in the APB2OPB primarily expose some
internal plumbing necessary to get correct write accesses onto the OPB.
OPB write cycles require "data mirroring" across the 32-bit data bus to
support variable data width slaves that don't implement "byte enables".
For slaves that do implement byte enables the master can signal which
bytes on the data bus the slave should consider valid.
The data mirroring behaviour is specified by the following table:
+-----------------+----------+-----------------------------------+
| | | 32-bit Data Bus |
+---------+-------+----------+---------+---------+-------+-------+
| | | | | | | |
| ABus | Mn_BE | Request | Dbus | Dbus | Dbus | Dbus |
| (30:31) | (0:3) | Transfer | 0:7 | 8:15 | 16:23 | 24:31 |
| | | Size | byte0 | byte1 | byte2 | byte3 |
+---------+-------+----------+---------+---------+-------+-------+
| 00 | 1111 | fullword | byte0 | byte1 | byte2 | byte3 |
+---------+-------+----------+---------+---------+-------+-------+
| 00 | 1110 | halfword | byte0 | byte1 | byte2 | |
+---------+-------+----------+---------+---------+-------+-------+
| 01 | 0111 | byte | _byte1_ | byte1 | byte2 | byte3 |
+---------+-------+----------+---------+---------+-------+-------+
| 00 | 1100 | halfword | byte0 | byte1 | | |
+---------+-------+----------+---------+---------+-------+-------+
| 01 | 0110 | byte | _byte1_ | byte1 | byte2 | |
+---------+-------+----------+---------+---------+-------+-------+
| 10 | 0011 | halfword | _byte2_ | _byte3_ | byte2 | byte3 |
+---------+-------+----------+---------+---------+-------+-------+
| 00 | 1000 | byte | byte0 | | | |
+---------+-------+----------+---------+---------+-------+-------+
| 01 | 0100 | byte | _byte1_ | byte1 | | |
+---------+-------+----------+---------+---------+-------+-------+
| 10 | 0010 | byte | _byte2_ | | byte2 | |
+---------+-------+----------+---------+---------+-------+-------+
| 11 | 0001 | byte | _byte3_ | _byte3_ | | byte3 |
+---------+-------+----------+---------+---------+-------+-------+
Mirrored data values are highlighted by underscores in the Dbus columns.
The values in the ABus and Request Transfer Size columns correspond to
values in the field names listed in the write data order select register
descriptions.
Similar configuration registers are exposed for reads which enables the
secondary purpose of configuring hardware endian conversions. It appears the
data bus byte order is switched around in hardware so set the registers such
that we can access the correct values for all widths. The values were
determined by experimentation on hardware against fixed CFAM register
values to configure the read data order, then in combination with the
table above and the register layout documentation in the AST2600
datasheet performing write/read cycles to configure the write data order
registers.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Alistair Popple <alistair@popple.id.au>
Link: https://lore.kernel.org/r/20191108051945.7109-12-joel@jms.id.au
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
These trace points help with debugging the FSI master. They show the low
level reads, writes and error states of the master.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20191108051945.7109-11-joel@jms.id.au
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The ast2600 BMC has a pair of FSI masters in it, behind an AHB to OPB
bridge.
The master driver supports reads and writes of full words, half word and
byte accesses to remote CFAMs. It can perform very basic error recovery
through resetting of the FSI port when an error is detected, and the
issuing of breaks and terms.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Alistair Popple <alistair@popple.id.au>
--
v2:
- remove debugging
- squash in fixes
Link: https://lore.kernel.org/r/20191108051945.7109-10-joel@jms.id.au
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Eddie James