Commit Graph

407 Commits

Author SHA1 Message Date
Arvind Yadav 023a8280b8 clk: rockchip: handle of_iomap failures in legacy clock driver
Check return value of of_iomap and handle errors correctly.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-23 18:00:25 +02:00
Xing Zheng 4608d96fb4 clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399
Sorry to refer incorrect clock diagram, we double check it that the bits
configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin board.

1. the hclk_host0 and hclk_host1 are endpoint clocks:
cpll --> G5[1] --> aclk_perihp_cpll_src --\              |--> hclk_host0
                                          | --> ... ---> |
gpll --> G5[0] --> aclk_perihp_gpll_src --/              |--> hclk_host1

2. there is no clock below the cpll_aclk_perihp_src,
   and the hclk_hostX are below the gpll_aclk_perihp_src:
    pll_cpll                              1            1   800000000          0 0
       cpll                               7           19   800000000          0 0
          cpll_aclk_perihp_src            0            0   800000000          0 0
...
    pll_gpll                              1            1   594000000          0 0
       gpll                              10           10   594000000          0 0
          gpll_aclk_perihp_src            2            2   594000000          0 0
                hclk_perihp               5            5    74250000          0 0
                   hclk_host1_arb         2            2    74250000          0 0
                   hclk_host1             2            2    74250000          0 0
                   hclk_host0_arb         2            2    74250000          0 0
                   hclk_host0             2            2    74250000          0 0

3. by default, G5[0] and G5[1] are enabled:
localhost ~ # mem r 0xff760314
0x000003e0

4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable,
   the DUT still works well:
localhost ~ # mem w 0xff760314 0xffff03e2
localhost ~ # mem r 0xff760314
0x000003e2
plug/unplug, the work statue is ok

5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable,
   the DUT will be crashed:
localhost ~ # mem w 0xff760314 0xffff03e1
localhost ~ # mem r 0xff760314
0x000003e1
plug/unplug, the DUT is crashed

Summary:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

Fixes: 3bd14ae9da ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

[here the clock-documentation in the manual was actually stating the wrong
bits and thus only Xing's testing above revealed the issue]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-12 18:09:19 +02:00
Xing Zheng 20c389e656 clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-12 10:04:52 +02:00
Chris Zhong 54479449c8 clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical
The aclk_vio_noc should be put into critical list, as the interconnect
is not handled right now, but is required by VOP.
And the Type-C DP need these clocks: aclk_hdcp_noc, hclk_hdcp_noc,
pclk_hdcp_noc. Mark them as critical to avoid someone close them.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-12 00:12:55 +02:00
Chris Zhong a3f457d963 clk: rockchip: fix rk3399 aclk_vio gate bit
Fix incorrect rk3399 aclk_vio gating bit, it should be 0, not 10.

Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-11 23:05:06 +02:00
Heiko Stübner e6cebc7273 clk: rockchip: use general clock flag when registering pll
Add the general flags the pll list already contains to the clock init,
so that needed clock flags can be used for plls.

Signed-off-by: Heiko Stübner <heiko@sntech.de>
2016-08-08 10:57:21 +02:00
Elaine Zhang 4f4e049167 clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399
allow aclk_pcie and aclk_perf_pcie disabled when unused.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-08 10:57:21 +02:00
Xing Zheng efc4204cf7 clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
We need to add more clocks for supporting more display resolution
for HDMI.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-08 10:57:21 +02:00
Stephen Boyd 582e2405b2 Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to
 displayport clock on the rk3399.
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Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.

* tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
  clk: rockchip: export rk3228 MAC clocks
  clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
  clk: rockchip: export rk3228 audio clocks
  clk: rockchip: include rk3228 downstream muxes into fractional dividers
  clk: rockchip: fix incorrect rk3228 clock registers
  clk: rockchip: add clock-ids for rk3228 MAC clocks
  clk: rockchip: add clock-ids for rk3228 audio clocks
  clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
2016-07-01 17:30:42 -07:00
Xing Zheng 3770821fa3 clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.

Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-07-01 01:50:17 +02:00
Xing Zheng 6e3732a2be clk: rockchip: export rk3228 MAC clocks
This patch exports related MAC clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-07-01 01:50:11 +02:00
Xing Zheng 09f684226d clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
The sclk_macphy_50m is confusing, the sclk_mac_extclk describes
a external clock  clearly.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-07-01 01:50:06 +02:00
Xing Zheng a45c072bb4 clk: rockchip: export rk3228 audio clocks
This patch exports related i2s/spdif clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-07-01 01:50:02 +02:00
Xing Zheng cb87df58bc clk: rockchip: include rk3228 downstream muxes into fractional dividers
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-07-01 01:49:31 +02:00
Xing Zheng 67de7901c4 clk: rockchip: fix incorrect rk3228 clock registers
Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect,
we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22 00:55:03 +02:00
Shawn Lin 62d0e71df0 clk: rockchip: release io resource when failing to init clk on rk3399
We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.

This was missing on the newly added rk3399 clock tree.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-03 15:36:49 +02:00
Xing Zheng 26e0ee1c62 clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
Like rk3288, the pclk supplying the watchdog is controlled via the
SGRF register area. Additionally the SGRF isn't even writable in
every boot mode.

But still the clock control is available and in the future someone
might want to use it. Therefore define a simple clock for the time
being so that the watchdog driver can read its rate.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:44:26 +02:00
Xing Zheng 3183c0d519 clk: rockchip: fix cpuclk registration error handling
It maybe due to a copy-paste error the error handing should be
cclk not clk when checking if the cpuclk registration succeeded.

Reported-by: Lin Huang <lin.huang@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:40:23 +02:00
Douglas Anderson 4715f81afc clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization"
This reverts commit 7a03fe6f48 ("clk: rockchip: reset init state
before mmc card initialization").

Though not totally obvious from the commit message nor from the source
code, that commit appears to be trying to reset the "_drv" MMC clocks to
90 degrees (note that the "_sample" MMC clocks have a shift of 0 so are
not touched).

The major problem here is that it doesn't properly reset things.  The
phase is a two bit field and the commit only touches one of the two
bits.  Thus the commit had the following affect:
- phase   0  => phase  90
- phase  90  => phase  90
- phase 180  => phase 270
- phase 270  => phase 270

Things get even weirder if you happen to have a bootloader that was
actually using delay elements (should be no reason to, but you never
know), since those are additional bits that weren't touched by the
original patch.

This is unlikely to be what we actually want.  Checking on rk3288-veyron
devices, I can see that the bootloader leaves these clocks as:
- emmc:  phase 180
- sdmmc: phase 90
- sdio0: phase 90

Thus on rk3288-veyron devices the commit we're reverting had the effect
of changing the eMMC clock to phase 270.  This probably explains the
scattered reports I've heard of eMMC devices not working on some veyron
devices when using the upstream kernel.

The original commit was presumably made because previously the kernel
didn't touch the "_drv" phase at all and relied on whatever value was
there when the kernel started.  If someone was using a bootloader that
touched the "_drv" phase then, indeed, we should have code in the kernel
to fix that.  ...and also, to get ideal timings, we should also have the
kernel change the phase depending on the speed mode.  In fact, that's
the subject of a recent patch I posted at
<https://patchwork.kernel.org/patch/9075141/>.

Ideally, we should take both the patch posted to dw_mmc and this
revert.  Since those will likely go through different trees, here I
describe behavior with the combos:

1. Just this revert: likely will fix rk3288-veyron eMMC on some devices
   + other cases; might break someone with a strange bootloader that
   sets the phase to 0 or one that uses delay elements (pretty
   unpredicable what would happen in that case).
2. Just dw_mmc patch: fixes everyone.  Effectly the dw_mmc patch will
   totally override the broken patch and fix everything.
3. Both patches: fixes everyone.  Once dw_mmc is initting properly then
   any defaults from the clock code doesn't mattery.

Fixes: 7a03fe6f48 ("clk: rockchip: reset init state before mmc card initialization")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

[emmc and sdmmc still work on all current boards in mainline after this
revert, so they should take precedence over any out-of-tree board that
will hopefully again get fixed with the better upcoming dw_mmc change.]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:40:23 +02:00
Xing Zheng 3bd14ae9da clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
There was a typo, swapping 'c' <--> 'g'.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:40:23 +02:00
Brian Norris 176df69cb0 clk: rockchip: mark rk3399 GIC clocks as critical
We never want to kill the GIC.

Noticed when making other clock fixups, and seeing the newly-constructed
clock tree try to disable cpll, where we had this parent structure:

  aclk_gic <------\
                  |--- aclk_gic_pre <-- cpll <-- pll_cpll
  aclk_gic_noc <--/

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:40:23 +02:00
Heiko Stuebner 595144c114 clk: rockchip: initialize flags of clk_init_data in mmc-phase clock
The flags element of clk_init_data was never initialized for mmc-
phase-clocks resulting in the element containing a random value
and thus possibly enabling unwanted clock flags.

Fixes: 89bf26cbc1 ("clk: rockchip: Add support for the mmc clock phases using the framework")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:40:23 +02:00
Stephen Boyd 5707291c6c Merge tag 'v4.7-rockchip-clk4' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:

Another small rk3399 fixup as well as simplifications around
our handling of the General-Register-Files syscon.

* tag 'v4.7-rockchip-clk4' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: drop old_rate calculation on pll rate changes
  clk: rockchip: simplify GRF handling in pll clocks
  clk: rockchip: lookup General Register Files in rockchip_clk_init
  clk: rockchip: fix the rk3399 sdmmc sample / drv name
2016-05-12 14:48:22 -07:00
Heiko Stuebner 7e5385dc72 clk: rockchip: drop old_rate calculation on pll rate changes
Previously when everything happened in the set_rate callbacks itself we
needed the old_rate value for the possible rate rollback, so that made
it easy to also use it in the debug output.

Now with the param-handling being done in separate functions, reading and
recalculating the current pll rate only to use it in a debug message that
won't get displayed in regular cases anyway is quite a waste.

Therefore drop that value from the debug output. In the worst case that
previous rate will have been displayed on the rate change before.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-09 16:04:39 +02:00
Heiko Stuebner c9c3c6eecc clk: rockchip: simplify GRF handling in pll clocks
With the previous commit, the clock drivers now know at init time if the
GRF regmap is available. That means if it isn't available then, it also
won't become available later and we can therefore switch PLLs, that need
the GRF for the lock-status, to read-only mode - similar behaviour as the
aborting of rate changes we did before.

This saves some conditionals on every rate change and we can also drop
the rockchip_clk_get_grf function completely.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-09 16:04:15 +02:00
Heiko Stuebner 6f339dc271 clk: rockchip: lookup General Register Files in rockchip_clk_init
In the distant past syscons were initialized pretty late and weren't
available at the time the clock init ran. As the GRF is mainly needed
for PLL lock-status checking, we had this lazy init that tried to grab
the syscon on PLL rate changes and denied these changes if it was not
available.

These days syscons are available very early and recent addition to
rockchip clocks, like the PLL clk_init actually also rely on them
being available at that time, so there is no need to keep that lazy
init around, as it will also result in some more simplifications in
other parts of the clock-code.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-09 16:04:11 +02:00
Douglas Anderson 84752e8d8a clk: rockchip: fix the rk3399 sdmmc sample / drv name
The rk3399 clock table had a simple typo in it, calling the SDMMC sample
and drive clocks by the wrong name.  Fix this minor typo.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Acked-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-08 22:40:32 +02:00
Stephen Boyd 5569aedf1d A spelling fix and a bunch of rk3399 clock fixes.
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Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk updates from Heiko Stuebner:

A spelling fix and a bunch of rk3399 clock fixes.

* tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix the rk3399 cifout clock
  clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
  clk: rockchip: add some frequencies on the rk3399 PLL table
  clk: rockchip: assign more necessary rk3399 clock ids
  clk: rockchip: export some necessary rk3399 clock ids
  clk: rockchip: rename rga clock-id on rk3399
  clk: rockchip: add general gpu soft-reset on rk3399
  clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
  clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
2016-05-02 16:43:03 -07:00
Xing Zheng fd8bc82933 clk: rockchip: fix the rk3399 cifout clock
The cifout clock is incorrect due to the manual error, we need to
fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 22:54:51 +02:00
Xing Zheng 50961e8314 clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
We don't need to many clocks enable after startup, to reduce some
power consumption.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 22:52:26 +02:00
Xing Zheng aa2897ceb7 clk: rockchip: add some frequencies on the rk3399 PLL table
This patch add some necessary frequencies for the RK3399 clock.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 22:51:21 +02:00
Xing Zheng 3f92a05440 clk: rockchip: assign more necessary rk3399 clock ids
Assign newly added clock ids.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 22:49:13 +02:00
Xing Zheng f3d40914d3 clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 21:52:32 +02:00
Colin Ian King b8199ff31f clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
fix spelling mistake, unsucessful -> unsuccessful

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 09:34:03 +02:00
Stephen Boyd 0f05db651d Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.
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Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull some checkpatch silencers from Heiko Stuebner:

Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.

* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix checkpatch warning in core code
  clk: rockchip: drop unnecessary header comment
  clk: rockchip: reign in some overly long lines in the rk3399 controller
  clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
2016-04-20 11:41:37 -07:00
Heiko Stuebner 03ae174786 clk: rockchip: fix checkpatch warning in core code
We seem to have accumulated a bunch of checkpatch warnings, with mainly
overlong lines and two unnecessary allocation error messages.
Most were introduced with the recent multi-controller-support but some
were quite a bit older.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-20 09:53:39 +02:00
Heiko Stuebner 2b4e628648 clk: rockchip: drop unnecessary header comment
The internal clk header did contain a comment indicating that some of the
defined registers were shared over multiple clock controller variants.
In recent times, it was simply extended all the time and stopped providing
any meaningful information, so drop it and it's overlong line.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-19 21:17:55 +02:00
Heiko Stuebner 995d3fdeb2 clk: rockchip: reign in some overly long lines in the rk3399 controller
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.

Fix the newly added rk3399 clock code to respect that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-19 21:07:01 +02:00
Stephen Boyd ab98e20af5 This is first big chunk of Rockchip clock-related changes for 4.7.
Main change is probably the added support for the new rk3399 soc
 and necessary infrastructure changes surrounding it.
 
 The biggest chunk is probably that clock code is now able to
 handle multiple clock providers in one system, as the rk3399
 has two of those. A general one and another smaller one in a
 separate power domain. The rk3399 also uses another new pll type.
 Thankfully it just fits nicely into our current structure.
 It also needs some parts like the cpuclk mux parameters to be
 a bit more flexible and an new fractional divider subtype without
 gate.
 
 Apart from this big change we have some more fixes and removal
 of forgotten variables.
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Merge tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk updates from Heiko Stuebner:

This is first big chunk of Rockchip clock-related changes for 4.7.

Main change is probably the added support for the new rk3399 soc
and necessary infrastructure changes surrounding it.

The biggest chunk is probably that clock code is now able to
handle multiple clock providers in one system, as the rk3399
has two of those. A general one and another smaller one in a
separate power domain. The rk3399 also uses another new pll type.
Thankfully it just fits nicely into our current structure.
It also needs some parts like the cpuclk mux parameters to be
a bit more flexible and an new fractional divider subtype without
gate.

Apart from this big change we have some more fixes and removal
of forgotten variables.

* tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add clock controller for the RK3399
  dt-bindings: add bindings for rk3399 clock controller
  clk: rockchip: add dt-binding header for rk3399
  clk: rockchip: release io resource when failing to init clk
  clk: rockchip: remove redundant checking of device_node
  clk: rockchip: fix warning reported by kernel-doc
  clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data
  clk: rockchip: add new pll-type for rk3399 and similar socs
  clk: rockchip: Add support for multiple clock providers
  clk: rockchip: allow varying mux parameters for cpuclk pll-sources
  clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
2016-04-15 15:47:54 -07:00
Philipp Zabel 3fb950fea6 clk: rockchip: Make reset_control_ops const
The rockchip_softrst_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29 16:29:46 -07:00
Xing Zheng 115510053e clk: rockchip: add clock controller for the RK3399
Add the clock tree definition for the new RK3399 SoC.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28 14:57:07 +02:00
Shawn Lin 1d003eb080 clk: rockchip: release io resource when failing to init clk
We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:35 +02:00
Shawn Lin ff1ae20961 clk: rockchip: remove redundant checking of device_node
rockchip_clk_of_add_provider is used by sub-clk driver which
already call of_iomap before calling it. If device_node does
not exist, of_iomap returns NULL which will fail to init the
sub-clk driver. So really it's redundant.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:35 +02:00
Shawn Lin 2af2544d60 clk: rockchip: fix warning reported by kernel-doc
./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null

drivers/clk/rockchip/clk.h:133: warning: missing initial short
description on line:
 * struct rockchip_clk_provider: information about clock provider
drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:164: warning: missing initial short
description on line:
 * struct rockchip_pll_clock: information about pll clock
drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'parent_names'
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'num_parents'
drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef
member 'parent_name' description in 'rockchip_pll_clock'
drivers/clk/rockchip/clk.h:235: warning: missing initial short
description on line:
 * struct rockchip_cpuclk_reg_data: describes register offsets and
masks of the cpuclock

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:35 +02:00
Shawn Lin cb3abdd628 clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data
mux_core_reg isn't been used anywhere, let's remove it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:34 +02:00
Xing Zheng b40baccd23 clk: rockchip: add new pll-type for rk3399 and similar socs
The rk3399's pll and clock are similar with rk3036's, it different
with base on the rk3066(rk3188, rk3288, rk3368 use it), there are
different adjust foctors and control registers, so these should be
independent and separate from the series of rk3066s.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:34 +02:00
Xing Zheng ef1d9feecc clk: rockchip: Add support for multiple clock providers
There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.

Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:34 +02:00
Xing Zheng 268aebaa24 clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 13:03:33 +02:00
Xing Zheng 9387bfd19b clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
Because there are some frac clock mux nodes don't have a gate node on
the RK3399.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 00:53:20 +01:00
Linus Torvalds 33c1f638a0 The clk changes for this release cycle are mostly dominated by
new device support in terms of LoC, but there has been some cleanup
 in the core as well as the usual minor clk additions to various
 drivers.
 
 Core:
 
  - parent tracking has been simplified
 
  - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started
 
  - of_clk_init() doesn't consider disabled DT nodes anymore
 
  - clk_unregister() had an error path bug squashed
 
  - of_clk_get_parent_count() has been fixed to only return unsigned ints
 
  - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone
 
 New Drivers:
 
  - NXP LPC18xx creg
 
  - QCOM IPQ4019 GCC
 
  - TI dm814x ADPLL
 
  - i.MX6QP
 
 Updates:
 
  - Cyngus audio clks found on Broadcom iProc devices
 
  - Non-critical fixes for BCM2385 PLLs
 
  - Samsung exynos5433 updates for clk id errors, HDMI support,
    suspend/resume simplifications
 
  - USB, CAN, LVDS, and FCP clks on shmobile devices
 
  - sunxi got support for more clks on new SoCs and went through a minor
    refactoring/rewrite to use a simpler factor clk construct
 
  - rockchip added some more clk ids and added suport for fraction dividers
 
  - QCOM GDSCs in msm8996
 
  - A new devm helper to make adding custom actions simpler (acked by Greg)
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The clk changes for this release cycle are mostly dominated by new
  device support in terms of LoC, but there has been some cleanup in the
  core as well as the usual minor clk additions to various drivers.

  Core:
   - parent tracking has been simplified
   - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started
   - of_clk_init() doesn't consider disabled DT nodes anymore
   - clk_unregister() had an error path bug squashed
   - of_clk_get_parent_count() has been fixed to only return unsigned ints
   - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone

  New Drivers:
   - NXP LPC18xx creg
   - QCOM IPQ4019 GCC
   - TI dm814x ADPLL
   - i.MX6QP

  Updates:
   - Cyngus audio clks found on Broadcom iProc devices
   - Non-critical fixes for BCM2385 PLLs
   - Samsung exynos5433 updates for clk id errors, HDMI support,
     suspend/resume simplifications
   - USB, CAN, LVDS, and FCP clks on shmobile devices
   - sunxi got support for more clks on new SoCs and went through a
     minor refactoring/rewrite to use a simpler factor clk construct
   - rockchip added some more clk ids and added suport for fraction
     dividers
   - QCOM GDSCs in msm8996
   - A new devm helper to make adding custom actions simpler (acked by Greg)"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (197 commits)
  clk: bcm2835: fix check of error code returned by devm_ioremap_resource()
  clk: renesas: div6: use RENESAS for #define
  clk: renesas: Rename header file renesas.h
  clk: max77{686,802}: Remove CLK_IS_ROOT
  clk: versatile: Remove CLK_IS_ROOT
  clk: sunxi: Remove use of variable length array
  clk: fixed-rate: Remove CLK_IS_ROOT
  clk: qcom: Remove CLK_IS_ROOT
  doc: dt: add documentation for lpc1850-creg-clk driver
  clk: add lpc18xx creg clk driver
  clk: lpc32xx: fix compilation warning
  clk: xgene: Add missing parenthesis when clearing divider value
  clk: mb86s7x: Remove CLK_IS_ROOT
  clk: x86: Remove clkdev.h and clk.h includes
  clk: x86: Remove CLK_IS_ROOT
  clk: mvebu: Remove CLK_IS_ROOT
  clk: renesas: move drivers to renesas directory
  clk: si5{14,351,70}: Remove CLK_IS_ROOT
  clk: scpi: Remove CLK_IS_ROOT
  clk: s2mps11: Remove CLK_IS_ROOT
  ...
2016-03-23 06:06:45 -07:00
Linus Torvalds 8c6d4082fc ARM: SoC 64-bit changes for v4.6
Here's our branch of ARM64 contents for this merge window, now
 containing all ARM64 changes other than device tree files.
 
 - Various new platforms get added
   - Allwinner A64 SoC
   - Annapurna Labs Alpine SoCs
   - Broadcom Vulcan
   - Marvell Armada 3700 SoCs
   - Amlogic S905
 
 - Various defconfig changes to enable platform specific drivers
 
 This branch includes the clk git tree to resolve a build-time
 dependency.
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Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC 64-bit changes from Arnd Bergmann:
 "Here's our branch of ARM64 contents for this merge window, now
  containing all ARM64 changes other than device tree files.

   - Various new platforms get added:
      * Allwinner A64 SoC
      * Annapurna Labs Alpine SoCs
      * Broadcom Vulcan
      * Marvell Armada 3700 SoCs
      * Amlogic S905

   - Various defconfig changes to enable platform specific drivers

  This branch includes the clk git tree to resolve a build-time
  dependency"

* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  arm64: defconfig: Increase MMC_BLOCK_MINORS to 16
  arm64: defconfig: Add Qualcomm sdhci and restart functionality
  ARM64: Enable Amlogic Meson GXBaby platform
  arm64: defconfig: Enable Samsung MFD and related configs
  arm64: alpine: select the Alpine MSI controller driver
  arm64: defconfig: enable the Alpine family
  arm64: add Alpine SoC family
  arm64: defconfig: Enable exynos thermal config
  arm64: add defconfig options for Allwinner SoCs
  arm64: defconfig: Enable DesignWare APB GPIO controller
  arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
  arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
  clk: samsung: Don't build ARMv8 clock drivers on ARMv7
  MAINTAINERS: Add entry for Broadcom Vulcan SoC
  arm64: cputype info for Broadcom Vulcan
  arm64: Broadcom Vulcan support
  arm64: defconfig: Add Broadcom Vulcan to defconfig
  arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
  Documentation: arm: add Marvell Armada 7K and 8K families
  Documentation: arm: add link to Armada 38x Functional Spec
  ...
2016-03-20 15:08:45 -07:00
Heiko Stuebner 2c6fae2501 clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036
The emac needs constant and very specific rate but the possible PLL-sources
are very limited, so we expect the PLL source to be set manually on per
board and don't want it to get changed in an automatic way later.
So add the necessary clock-id and disable reparenting on set_rate calls.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16 19:28:02 -04:00
Xing Zheng e764b93924 clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
Associate the new clock id the clock.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16 19:28:01 -04:00
Stephen Boyd 37655fae0c Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
 and some more clock-ids.
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Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull second batch of rockchip clk updates from Heiko Stuebner:

Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.

* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: include downstream muxes into fractional dividers on rk3368
  clk: rockchip: set the clock ids for RK3228 HDMI
  clk: rockchip: set the clock ids for RK3228 VOP
  clk: rockchip: add the tsadc clocks found on rk3228 SoCs
  clk: rockchip: add the new clock ids for RK3228 HDMI
  clk: rockchip: add the new clock ids for RK3228 VOP
  clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
  clk: rockchip: fix coding style for clk-cpu.c
  clk: rockchip: don't return NULL when registering mmc branch fails
  clk: rockchip: don't return NULL when registering inverter fails
  clk: rockchip: check grf when waiting pll lock
  clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
2016-03-04 09:36:29 -08:00
Elaine Zhang 7af8a26ce7 clk: rockchip: include downstream muxes into fractional dividers on rk3368
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3368 clocks were left out, so convert them now.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:08:45 +01:00
Yakir Yang bdc7deec2f clk: rockchip: set the clock ids for RK3228 HDMI
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:08:04 +01:00
Yakir Yang 0a9d4ac08e clk: rockchip: set the clock ids for RK3228 VOP
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:07:15 +01:00
Caesar Wang a3cb9aa4ba clk: rockchip: add the tsadc clocks found on rk3228 SoCs
This patch adds the needed clocks for rk3228 tsadc.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:05:12 +01:00
Shawn Lin fc6d875ecb clk: rockchip: fix coding style for clk-cpu.c
Fix the issue reported by checkpatch:
ERROR: space prohibited before that ',' (ctx:WxW)
+               writel(clksel->val , cpuclk->reg_base + clksel->reg);

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 23:38:35 +01:00
Shawn Lin 022dce0bd0 clk: rockchip: don't return NULL when registering mmc branch fails
Avoid return NULL if rockchip_clk_register_mmc fails, otherwise
rockchip_clk_register_branches print "unknown clock type". The acutal
case is that it's a known clock type but we fail to regiser it, which
may makes user confuse the reason of failure.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 23:37:27 +01:00
Shawn Lin ddd02e1456 clk: rockchip: don't return NULL when registering inverter fails
Avoid return NULL if rockchip_clk_register_inverter fails, otherwise
rockchip_clk_register_branches print "unknown clock type". The acutal
case is that it's a known clock type but we fail to regiser it, which
may makes user confuse the reason of failure.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 23:35:20 +01:00
Shawn Lin eb4e10c61d clk: rockchip: check grf when waiting pll lock
rockchip_clk_get_grf pass on return value from
syscon_regmap_lookup_by_phandle, so we check grf to
make sure whether to do the following things or not.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 22:38:27 +01:00
Shawn Lin 282312d1ac clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
Add clk_disable_unprepare to handle cpuclk->alt_parent if
rockchip_clk_register_cpuclk fails.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 22:32:00 +01:00
Michael Turquette 70750ff2c9 Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
 place in the clock tree instead of having to register factor
 clocks in the init callback separately. And as always some more
 clock-ids and non-regression fixes for mistakes introduced in
 past kernel releases.
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Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
2016-02-15 11:59:45 -08:00
Heiko Stuebner 36714529f8 clk: rockchip: convert manually created factor clocks to the new type
Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.

This also unifies the artificial separation of the hclk_vcodec etc clocks
again.

We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 15:54:20 +01:00
Heiko Stuebner 29a30c269a clk: rockchip: add a factor clock type
Add a clock type for fixed factor clocks. This allows us to define fixed
factor clocks where they appear in the clock hierarchy instead of in the
init function.

The additional factor_gate type, finally allows us to model some last
parts of the clock tree correctly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 15:49:09 +01:00
Heiko Stuebner aebe3ad801 clk: rockchip: fix parent of hclk_vcodec on rk3036
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock
hclk_vcodec_pre in between and not a child of hclk_disp_pre.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 13:53:15 +01:00
Shawn Lin 2467b6745e clk: rockchip: free memory in error cases when registering clock branches
Add free memeory if rockchip_clk_register_branch fails.

Fixes: a245fecbb8 ("clk: rockchip: add basic infrastructure...")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-02 22:09:50 +01:00
Stephen Boyd 4fcad2eaaa Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: rockchip: rk3368: fix some clock gates
  clk: rockchip: rk3036: rename emac ext source clock
  clk: rockchip: rk3036: fix the div offset for emac clock
  clk: rockchip: rk3036: fix uarts clock error
  clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-29 17:26:31 -08:00
Heiko Stuebner 5035981979 clk-divider: make sure read-only dividers do not write to their register
Commit e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.

On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.

To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.

The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.

Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:44:37 -08:00
Alexander Kochetkov 89aa027e60 clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0

Tested on radxarock-lite.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-29 10:18:49 +01:00
Shawn Lin bb07698fc8 clk: rockchip: fix wrong mmc phase shift for rk3228
mmc sample shift is 0 for rk3228 refer to user manaul.
So it's broken if we enable mmc tuning for rk3228.

Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-28 18:02:26 +01:00
Alexander Kochetkov e8b63288b3 clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks
hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.

Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Cc: stable@vger.kernel.org # 4.1.x-
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26 21:09:51 +01:00
Paweł Jarosz 2c41b5a775 clk: rockchip: add tsadc clock on rk3066
Set clock id for sclk_tsadc gating clock of tsadc in rk3066

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26 01:08:02 +01:00
Heiko Stuebner 219a5859c8 clk: rockchip: fix usbphy-related clocks
The otgphy clocks really only drive the phy blocks. These in turn
contain plls that then generate the 480m clocks the clock controller
uses to supply some other clocks like uart0, gpu or the video-codec.

So fix this structure to actually respect that hirarchy and removed
that usb480m fixed-rate clock working as a placeholder till now, as
this wouldn't even work if the supplying phy gets turned off while
its pll-output gets used elsewhere.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
2016-01-25 15:00:03 +01:00
zhangqing e8099067de clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch
I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25 11:06:54 +01:00
zhangqing 0bbe62eb92 clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch
SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25 11:04:51 +01:00
zhangqing d566ebc3c0 clk: rockchip: rk3368: fix edp_24m parent
The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25 11:03:45 +01:00
Heiko Stuebner fd0c0740fa clk: rockchip: rk3368: fix hdmi_cec gate-register
Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Heiko Stuebner 0f28d98463 clk: rockchip: rk3368: fix parents of video encoder/decoder
The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Heiko Stuebner c6d5fe2ca8 clk: rockchip: rk3368: fix cpuclk core dividers
Similar to commit 9880d4277f ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Heiko Stuebner 535ebd428a clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster
Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Yakir Yang ee16bbd289 clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for hclk_vio_bus
HCLK_VIO_BUS is the noc bus controller clock for display module,
due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-24 23:29:16 +01:00
Jianqun xu 8931f8e029 clk: rockchip: rk3368: fix some clock gates
Reference to the Rockchip RK3368 TRM v1.1, some clock
gates need to be updated.

Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng 3d667920bc clk: rockchip: rk3036: rename emac ext source clock
There is only support rmii in the RK3036, so we should use the correct
ext clock name as described in the TRM.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
[update dt-binding document as well]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng c40519350e clk: rockchip: rk3036: fix the div offset for emac clock
Due to reference to old version TRM, there are incorrect emac clock node.
The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the
child div.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng b29de2de50 clk: rockchip: rk3036: fix uarts clock error
Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng 99222c9e4d clk: rockchip: rk3036: fix the FLAGs for clock mux
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags
of COMPOSITE_NODIV type should be MFLAGS.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Michael Turquette 49dea76aeb Merge branch 'clk-rockchip' into clk-next 2016-01-02 13:41:09 -08:00
Heiko Stübner 5b73840375 clk: rockchip: fix section mismatches with new child-clocks
To model the muxes downstream of fractional dividers we introduced the
child property, allowing to describe a direct child clock.
The first implementation seems to cause section warnings, as the core
clock-tree is marked as initdata while the data pointed to from the
child element is not.

While there may be some way to also set that missing property in the
inline notation I didn't find it, so to actually fix the issue for now
move the sub-definitions into separate declarations that can have
their own __initdata properties.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-02 13:40:29 -08:00
Michael Turquette a915e30dd2 Merge branch 'clk-rockchip' into clk-next 2015-12-23 13:08:56 -08:00
Xing Zheng b0158bb27c clk: rockchip: rk3036: include downstream muxes into fractional dividers
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3036 SoCs.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:31 -08:00
Sjoerd Simons 84a8c54166 clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288
SoCs only feed those clocks, allow those clocks to change their parents
all the way up the hierarchy.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:30 -08:00
Heiko Stuebner 6674642089 clk: rockchip: include downstream muxes into fractional dividers
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported Rockchip SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:30 -08:00
Heiko Stuebner 8ca1ca8f60 clk: rockchip: handle mux dependency of fractional dividers
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature"
that requires the downstream mux to actually point to the fractional
divider and the fractional divider gate to be enabled, for it to really
accept changes to the divider ratio.

The downstream muxes themselfs are not generic enough to include them
directly into the fractional divider, as they have varying sources of
parent clocks including not only clocks related to the fractional
dividers but other clocks as well.

To solve this, allow our clock branches to specify direct child clock-
branches in the new child property, let the fractional divider register
its downstream mux through this and add a clock notifier that temporarily
switches the mux setting when it notices rate changes to the fractional
divider.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:29 -08:00
Heiko Stuebner dfff24bde7 clk: rockchip: only enter pll slow-mode directly before reboots on rk3288
As commit 1d33929e2a ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.

The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.

Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.

This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.

For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.

With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.

Fixes: 1d33929e2a ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-21 02:01:19 +01:00
Yakir Yang 2abc02fc49 clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio
ACLK_VIO is the noc bus clock for display module, display cann't
read data from ddr without this clock enabled.

Due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-16 22:24:13 +01:00
ZhengShunQian 60ecbd9d94 clk: rockchip: use rk3288-efuse clock ids
Reference the newly added efuse clock-ids in the clock-tree.

Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-12 20:10:48 +01:00
Jeffy Chen 307a2e9ac5 clk: rockchip: add clock controller for rk3228
Add the clock tree definition for the new rk3228 SoC.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-12 20:04:54 +01:00
Jeffy Chen ea03835fb8 clk: rockchip: allow more than 2 parents for cpuclk
RK3228's armclk has 3 parents, so allow cpuclk to have
more than 2 parents.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-09 22:30:42 +01:00
Heiko Stuebner 8ad0df33c6 clk: rockchip: fix rk3368 cpuclk divider offsets
Due to a copy-paste error the the rk3368 cpuclk settings were acessing
rk3288-specific register offsets. This never caused problems till now,
as cpu frequency scaling in't used currently at all.

Reported-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-03 16:20:02 +01:00
Jianqun xu 941c4d3f11 clk: rockchip: protect rk3368 aclk_bus and aclk_peri clocks
Add aclk_bus and aclk_peri to the list of rk3368 critical clocks,
which are the base clocks that supply for all peripherals, never
to be disabled automatically.

Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-02 23:11:44 +01:00
Caesar Wang a7ce405088 clk: rockchip: Force rk3368 PWM clock (and its parents) on
Most rk3368 boards (especially those with Pmic that followed the lead
from rk3368-evb-act8846) have a PWM regulator on them for vdd_logic.
This is the main voltage for all kinds of misc stuff including the
memory controller.

On these boards it is critically important to make sure that the PWM
never ever glitches and never loses its clock. Any glitch could
crash the system.

Right now there are no users of the PWM regulator and also Linux
thinks that the PWM regulator is disabled.  Things happen to work
because firmware configured the PWM and Linux doesn't touch it.
..and the PWM's clock is marked as "ignore unused".

...but things _stop_ working if we turn off serial console.  Why?
Because:
    1. Serial console shares a parent clock with the PWM (pclk_cpu)
    2. If we have no serial console then nobody is holding pclk_cpu on
       at reboot time.  It gets disabled.

We need to fix a lot of the above problems, but until we get
everything right the cleanest "hack" seems like it is to just keep
the "rk_pwm" clock on always.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-02 00:40:17 +01:00
Chris Zhong 1d33929e2a clk: rockchip: switch PLLs to slow mode before reboot for rk3288
We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-01 18:33:43 +01:00
Chris Zhong a2f4c560f1 clk: rockchip: add mipidsi clock on rk3288
sclk_mipidsi_24m is the gating of mipi dsi phy.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-11-26 11:15:23 +01:00
Xing Zheng 5190c08b29 clk: rockchip: add clock controller for rk3036
Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-11-23 21:59:19 +01:00
Xing Zheng 9c4d6e5537 clk: rockchip: add new pll-type for rk3036 and similar socs
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-11-23 21:55:07 +01:00
Zain Wang 751be8f2ee clk: rockchip: set the id for crypto clk
Set the newly added id for the crypto clk, so that it can be called
in other parts.

Signed-off-by: Zain Wang <zain.wang@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-11-23 21:24:27 +01:00
Linus Torvalds f66477a0ae The majority of the changes are driver updates and new device
support. The core framework is mostly unchanged this time
 around, with only a couple patches to expose a clk provider
 API and make getting clk parent names from DT more robust.
 
 Driver updates:
 
 - Support for clock controllers found on Broadcom Northstar
   SoCs and bcm2835 SoC
 
 - Support for Allwinner audio clocks
 
 - A few cleanup patches for Tegra drivers and support for the
   highest DFLL frequencies on Tegra124
 
 - Samsung exynos7 fixes and improvements
 
 - i.Mx SoC updates to add a few missing clocks and keep debug
   uart clocks on during kernel intialization
 
 - Some mediatek cleanups and support for more subsystem clocks
 
 - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain
   controllers
 
 - A new driver for the Silabs si514 clock chip
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Merge tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The majority of the changes are driver updates and new device support.
  The core framework is mostly unchanged this time around, with only a
  couple patches to expose a clk provider API and make getting clk
  parent names from DT more robust.

  Driver updates:

   - Support for clock controllers found on Broadcom Northstar SoCs and
     bcm2835 SoC

   - Support for Allwinner audio clocks

   - A few cleanup patches for Tegra drivers and support for the highest
     DFLL frequencies on Tegra124

   - Samsung exynos7 fixes and improvements

   - i.Mx SoC updates to add a few missing clocks and keep debug uart
     clocks on during kernel intialization

   - Some mediatek cleanups and support for more subsystem clocks

   - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain
     controllers

   - A new driver for the Silabs si514 clock chip"

* tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (143 commits)
  clk: qcom: msm8960: Fix dsi1/2 halt bits
  clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks
  clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks
  clk: Add clk_hw_is_enabled() for use by clk providers
  clk: Add stubs for of_clk_*() APIs when CONFIG_OF=n
  clk: versatile-icst: fix memory leak
  clk: Remove clk_{register,unregister}_multiplier()
  clk: iproc: define Broadcom NS2 iProc clock binding
  clk: iproc: define Broadcom NSP iProc clock binding
  clk: ns2: add clock support for Broadcom Northstar 2 SoC
  clk: iproc: Separate status and control variables
  clk: iproc: Split off dig_filter
  clk: iproc: Add PLL base write function
  clk: nsp: add clock support for Broadcom Northstar Plus SoC
  clk: iproc: Add PWRCTRL support
  clk: cygnus: Convert all macros to all caps
  ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
  clk: imx31: add missing of_node_put
  clk: imx27: add missing of_node_put
  clk: si5351: add missing of_node_put
  ...
2015-11-05 12:59:36 -08:00
Douglas Anderson 4351f19a33 clk: rockchip: Make calculations use rounding
Let's use DIV_ROUND_CLOSEST for rounding, not just truncating
division.  This lets us get closer to the right rate.

Before this:
  set_phase(86) delay_nums=26 reg[0xf000420c]=0x468 actual_degrees=83
  set_phase(89) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86

After this:
  set_phase(86) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86
  set_phase(89) delay_nums=28 reg[0xf000420c]=0x470 actual_degrees=90

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:07 +01:00
Douglas Anderson f0232063fb clk: rockchip: Allow more precision for some mmc clock phases
Because of the inexact nature of the extra MMC delay elements (it's
not possible to keep the phase monotonic and to also make phases (mod
90) > 70), we previously only allowed phases (mod 90) of 22.5, 45,
and 67.5.

But it's not the end of the world if the MMC clock phase goes
non-monotonic.  At most we'll be 25 degrees off.  It's way better to
test more phases to look for bad ones than to be 25 degrees off, because
in the case of MMC really the point is to find bad phases and get as far
asway from the as possible.  If we get to test extra phases by going
slightly non-monotonic then that might be fine.  Worst case we would
end up at a phases that's slight differnt than the one we wanted, but
at least we'd still be quite far away from the a bad phase.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Fold in more precise variance-values of 44-77 instead of 40-80.
Fold in the actual removal of the monotonic requirement and adapt
patch message accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:06 +01:00
Andy Shevchenko 5d49a6e103 clk: rockchip: save width in struct clk_fractional_divider
The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it
will be switched to rational base approximation algorithm.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-02 11:29:47 -07:00
Shawn Lin 7a03fe6f48 clk: rockchip: reset init state before mmc card initialization
mmc host controller's IO input/output timing is unpredictable if
bootloader execute tuning for HS200 mode. It might make kernel failed
to initialize mmc card in identification mode. The root cause is
tuning phase and degree setting for HS200 mode in bootloader aren't
applicable to that of identification mode in kernel stage. Anyway, we
can't force all bootloaders to reset tuning phase and degree setting
before into kernel. Simply reset it in rockchip_clk_register_mmc.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-01 16:36:54 -07:00
Heiko Stübner 8334c0e7b9 clk: rockchip: don't use clk_ APIs in the pll init-callback
Separate the update of pll registers from the actual set_rate function
so that the init callback does not need to access clk-API functions.

As we now have separated the getting and setting of the pll parameters
we can also directly use these new functions in other places too.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-01 14:58:28 -07:00
Linus Torvalds d590b2d4bf A few driver fixes for tegra, rockchip, and st SoCs and a two-liner
in the framework to avoid oops when get_parent ops return out of range
 values on tegra platforms.
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A few driver fixes for tegra, rockchip, and st SoCs and a two-liner in
  the framework to avoid oops when get_parent ops return out of range
  values on tegra platforms"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
  clk: check for invalid parent index of orphans in __clk_init()
  clk: tegra: dfll: Properly protect OPP list
  clk: rockchip: add critical clock for rk3368
2015-09-19 20:17:40 -07:00
Stephen Boyd db544f1b58 Merge branch 'clk-next' into v4.3-rc1 2015-09-16 15:20:03 -07:00
Linus Torvalds d25ed277fb A couple build fixes for drivers introduced in the merge window and a
handful of patches to add more critical clocks on rockchip SoCs that
 are affected by newly introduced gpio clock handling.
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A couple build fixes for drivers introduced in the merge window and a
  handful of patches to add more critical clocks on rockchip SoCs that
  are affected by newly introduced gpio clock handling"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188
  clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks
  clk: rockchip: handle critical clocks after registering all clocks
  clk: Hi6220: separately build stub clock driver
  clk: h8s2678: Fix compile error
2015-09-14 16:58:35 -07:00
Heiko Stübner 380528f742 clk: rockchip: add critical clock for rk3368
Again a result of the gpio-clock-liberation the rk3368 needs the
pclk_pd_pmu marked as critical, to boot successfully.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-14 12:49:39 -07:00
Romain Perier 3bba75a2ec clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188
Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Michael Niewoehner <linux@mniewoehner.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-10 13:55:30 -07:00
Michael Niewoehner 1166160ab5 clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks
pclk_cpu needs to keep running because it is needed for devices like
the act8865 regulator but with the recent gpio clock handling this is
not always the case anymore. So add it to the list of critical clocks.

Signed-off-by: Michael Niewoehner <linux@mniewoehner.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-10 13:55:28 -07:00
Heiko Stuebner bb0f736163 clk: rockchip: handle critical clocks after registering all clocks
Currently the registration of critical clocks is done in the function
shared between rk3066 and rk3188 clock trees. That results in them
getting handled maybe before all of them are registered.

Therefore move the critical clock handling down to the end of the soc-
specific clock registration function, so that all clocks are registered
before they're maybe handled as critical clock.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Michael Niewoehner <linux@mniewoehner.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-10 13:55:21 -07:00
Linus Torvalds 88a99886c2 This is the bulk of pin control changes for the v4.3 development
cycle
 
 Core changes:
 
 - It is possible configure groups in debugfs.
 
 - Consolidation of chained IRQ handler install/remove replacing
   all call sites where irq_set_handler_data() and
   irq_set_chained_handler() were done in succession with a
   combined call to irq_set_chained_handler_and_data(). This
   series was created by Thomas Gleixner after the problem was
   observed by Russell King.
 
 - Tglx also made another series of patches switching
   __irq_set_handler_locked() for irq_set_handler_locked() which
   is way cleaner.
 
 - Tglx also wrote a good bunch of patches to make use of
   irq_desc_get_xxx() accessors and avoid looking up irq_descs
   from IRQ numbers. The goal is to get rid of the irq number
   from the handlers in the IRQ flow which is nice.
 
 Driver feature enhancements:
 
 - Power management support for the SiRF SoC Atlas 7.
 
 - Power down support for the Qualcomm driver.
 
 - Intel Cherryview and Baytrail: switch drivers to use raw
   spinlocks in IRQ handlers to play nice with the realtime
   patch set.
 
 - Rework and new modes handling for Qualcomm SPMI-MPP.
 
 - Pinconf power source config for SH PFC.
 
 New drivers and subdrivers:
 
 - A new driver for Conexant Digicolor CX92755.
 
 - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
   PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
 
 - Reverse-egineered the S/PDIF settings for the Allwinner
   sun4i driver.
 
 - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
 
 - A new Freescale i.mx6ul subdriver.
 
 Cleanup:
 
 - Remove platform data support in a number of SH PFC
   subdrivers.
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.3 development
  cycle.

  Like with GPIO it's a lot of stuff.  If my subsystems are any sign of
  the overall tempo of the kernel v4.3 will be a gigantic diff.

[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
  we'll see - Linus ]

  Core changes:

   - It is possible configure groups in debugfs.

   - Consolidation of chained IRQ handler install/remove replacing all
     call sites where irq_set_handler_data() and
     irq_set_chained_handler() were done in succession with a combined
     call to irq_set_chained_handler_and_data().  This series was
     created by Thomas Gleixner after the problem was observed by
     Russell King.

   - Tglx also made another series of patches switching
     __irq_set_handler_locked() for irq_set_handler_locked() which is
     way cleaner.

   - Tglx also wrote a good bunch of patches to make use of
     irq_desc_get_xxx() accessors and avoid looking up irq_descs from
     IRQ numbers.  The goal is to get rid of the irq number from the
     handlers in the IRQ flow which is nice.

  Driver feature enhancements:

   - Power management support for the SiRF SoC Atlas 7.

   - Power down support for the Qualcomm driver.

   - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
     in IRQ handlers to play nice with the realtime patch set.

   - Rework and new modes handling for Qualcomm SPMI-MPP.

   - Pinconf power source config for SH PFC.

  New drivers and subdrivers:

   - A new driver for Conexant Digicolor CX92755.

   - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
     ProXtream2 and PH1-LD6b SoC pin control support.

   - Reverse-egineered the S/PDIF settings for the Allwinner sun4i
     driver.

   - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs

   - A new Freescale i.mx6ul subdriver.

  Cleanup:

   - Remove platform data support in a number of SH PFC subdrivers"

* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
  pinctrl: at91: fix null pointer dereference
  pinctrl: mediatek: Implement wake handler and suspend resume
  pinctrl: mediatek: Fix multiple registration issue.
  pinctrl: sh-pfc: r8a7794: add USB pin groups
  pinctrl: at91: Use generic irq_{request,release}_resources()
  pinctrl: cherryview: Use raw_spinlock for locking
  pinctrl: baytrail: Use raw_spinlock for locking
  pinctrl: imx6ul: Remove .owner field
  pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
  pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
  clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
  pinctrl: sun4i: add spdif to pin description.
  pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
  pinctrl: baytrail: Serialize all register access
  pinctrl: baytrail: Drop FSF mailing address
  pinctrl: rockchip: only enable gpio clock when it setting
  pinctrl/mediatek: fix spelling mistake in dev_err error message
  pinctrl: cherryview: Serialize all register access
  pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
  pinctrl: nomadik: reflect current input value
  ...
2015-09-04 10:22:09 -07:00
Heiko Stuebner 1089737034 clk: rockchip: register pll mux before pll itself
The structure is xin24m -> pll -> pll-mux (xin24m,pll,xin32k). The pll
does have an init callback to make sure the boot-selected frequency is
using the expected pll settings and resets the same frequency using
the values provided in the driver if necessary.

The setting itself also involves remuxing the pll-mux temporarily to
the xin24m source to let the new pll rate settle. Until now this worked
flawlessly, even when it had the flaw of accessing the mux settings
before the mux actually got registered.

With the recent clock-core conversions this flaw became apparent in
null pointer dereference in
[<c03fc400>] (clk_hw_get_num_parents) from [<c0400df0>] (clk_mux_get_parent+0x14/0xc8)
[<c0400ddc>] (clk_mux_get_parent) from [<c040246c>] (rockchip_rk3066_pll_set_rate+0xd8/0x320)

So to fix that, simply register the pll-mux before the pll, so that
it will be fully initialized when the pll clock executes its init-
callback and possibly touches the pll-mux clock.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-24 16:49:15 -07:00
Stephen Boyd 836ee0f7d9 clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)

Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@chromium.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:12 -07:00
Stephen Boyd 4c34875059 clk: rockchip: Convert to clk_hw based provider APIs
We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:48:53 -07:00
Heiko Stuebner 15ee1f7d14 clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-13 16:09:42 +02:00
Sjoerd Simons bea047e075 clk: rockchip: Fix SPIF special clock definition
Neither spdif_src nor spdif_pll exists, judging by the vendor kernel in
both cases spdif_pre was meant. This brings the naming in line and
hierachy in line with that of sclk_i2s0.

Also allow sclk_spdif and spdif_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_spdif

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-12 00:59:22 -07:00
Douglas Anderson 2bbfe00147 clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
 NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.

So:
  NB = NF / 2
  BWADJ[11:0] + 1 = NF / 2
  BWADJ[11:0] = NF / 2 - 1

Right now, we have:

{                                               \
        .rate   = _rate##U,                     \
        .nr = _nr,                              \
        .nf = _nf,                              \
        .no = _no,                              \
        .bwadj = (_nf >> 1),                    \
}

That means we set bwadj to NF / 2, not NF / 2 - 1

All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).

Let's change to working with "NB" and fix the off by one error.  This
may affect PLL jitter in a small way (hopefully for the better).

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:12 -07:00
Stephen Boyd 9cfad9bc47 Merge branch 'cleanup-clk-h-includes' into clk-next
* cleanup-clk-h-includes: (62 commits)
  clk: Remove clk.h from clk-provider.h
  clk: h8300: Remove clk.h and clkdev.h includes
  clk: at91: Include clk.h and slab.h
  clk: ti: Switch clk-provider.h include to clk.h
  clk: pistachio: Include clk.h
  clk: ingenic: Include clk.h
  clk: si570: Include clk.h
  clk: moxart: Include clk.h
  clk: cdce925: Include clk.h
  clk: Include clk.h in clk.c
  clk: zynq: Include clk.h
  clk: ti: Include clk.h
  clk: sunxi: Include clk.h and remove unused clkdev.h includes
  clk: st: Include clk.h
  clk: qcom: Include clk.h
  clk: highbank: Include clk.h
  clk: bcm: Include clk.h
  clk: versatile: Remove clk.h and clkdev.h includes
  clk: ux500: Remove clk.h and clkdev.h includes
  clk: tegra: Properly include clk.h
  ...
2015-07-28 11:59:09 -07:00
Stephen Boyd f684ff8b67 clk: rockchip: Properly include clk.h
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h if it's actually used.

Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:10 -07:00
Heiko Stuebner 3536c97a52 clk: rockchip: add rk3368 clock controller
Describe the clock tree and software resets of the rk3368 ARM64 SoC

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:09:22 -07:00
Heiko Stuebner 4534b1113e clk: rockchip: define the inverters of rk3066/rk3188 and rk3288
Both soc series' have inverters on the hsadc and camera interface clock
paths. So define them using the newly added inverter type.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:07:40 -07:00
Heiko Stuebner 7c494ad058 clk: rockchip: fix issues in the mmc-phase clock
The review for the new inverter clock type uncovered some issues (missing
headers and name handling) that are also present in the mmc-phase clock
type, I got (to much) inspiration from. Fix these there too.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:07:38 -07:00
Heiko Stuebner 8a76f443a9 clk: rockchip: add support for phase inverters
Most Rockchip socs have optional phase inverters connected to some
clocks that move the clock-phase by 180 degrees.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@codeaurora.org: Dropped lazy part of commit text]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:04:40 -07:00
Heiko Stuebner 6f08507253 clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant
A clock branch consisting of a mux and divider with non-standard
divider values.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:25 -07:00
Heiko Stuebner 2d7884a7d0 clk: rockchip: protect register macros against multipart values
The macros calculate the correct offset from the id in the parameter.
If this parameter does not consist of a single number, the calculation
will return wrong registers in the best case or create unaligned accesses
in the worst case. So protect the calculations against such values.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:24 -07:00
Heiko Stuebner 101762976b clk: rockchip: fix faulty vip parent name on rk3288
The video input processor (vip) was called camera interface (cif) on
older socs which seems to have resulted in a copy'n'paste error when
creating the rk3288 camera clocks.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:23 -07:00
Heiko Stuebner 4791eb61db clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac
The dwmac ethernet controller on the rk3288 supports phys connected
via rgmii and rmii. With rgmii phys it is expected that the mac clock
is provided externally while with rmii phys the clock can be external
but also generated from the plls. In the later case it of course needs
be at 50MHz, which gets set from the dwmac_rk driver.
As most devices use a rgmii phy it never surfaced so far that the mac
clk mux, doesn't go up one lever to the pll clock in the rmii case with
internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag,
and thus will not set the correct frequency in most cases.

Fixes: b9e4ba5416 ("clk: rockchip: add clock controller for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:03:23 -07:00
Uwe Kleine-König 4a1caed3d0 clk: make several parent names const
Since commit 2893c37946 ("clk: make strings in parent name arrays
const") the name of parent clocks can be const. So add more const in
several clock drivers.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04 14:27:06 -07:00
Krzysztof Kozlowski 9b030bc929 clk: rockchip: Staticize file-scope declarations
Add missing static to local (file-scope only) symbols.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05 22:50:42 -07:00
Uwe Kleine-König 692d8328e8 clk: don't use __initconst for non-const arrays
The statement

	static const char *name[];

defines a modifiable array of pointers to constant chars. That is

	*name[0] = 'f';

is forbidden, but

	name[0] = "f";

is not. So marking an array that is defined as above with __initconst is
wrong. Either an additional const must be added such that the whole
definition reads:

	static const char *const name[] __initconst;

or where this is not possible __initdata must be used.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-04-12 17:18:27 -07:00
Linus Torvalds 18a8d49973 The clock framework changes for 3.20 contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
 devices. Additionaly the framework core underwent a bit of surgery with
 two major changes. The boundary between the clock core and clock
 providers (e.g clock drivers) is now more well defined with dedicated
 provider helper functions. struct clk no longer maps 1:1 with the
 hardware clock but is a true per-user cookie which helps us tracker
 users of hardware clocks and debug bad behavior. The second major change
 is the addition of rate constraints for clocks. Rate ranges are now
 supported which are analogous to the voltage ranges in the regulator
 framework. Unfortunately these changes to the core created some
 breakeage. We think we fixed it all up but for this reason there are
 lots of last minute commits trying to undo the damage.
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Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes contain the usual driver additions,
  enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
  devices.

  Additionally the framework core underwent a bit of surgery with two
  major changes:

   - The boundary between the clock core and clock providers (e.g clock
     drivers) is now more well defined with dedicated provider helper
     functions.  struct clk no longer maps 1:1 with the hardware clock
     but is a true per-user cookie which helps us tracker users of
     hardware clocks and debug bad behavior.

   - The addition of rate constraints for clocks.  Rate ranges are now
     supported which are analogous to the voltage ranges in the
     regulator framework.

  Unfortunately these changes to the core created some breakeage.  We
  think we fixed it all up but for this reason there are lots of last
  minute commits trying to undo the damage"

* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
  clk: Only recalculate the rate if needed
  Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
  clk: qoriq: Add support for the platform PLL
  powerpc/corenet: Enable CLK_QORIQ
  clk: Replace explicit clk assignment with __clk_hw_set_clk
  clk: Add __clk_hw_set_clk helper function
  clk: Don't dereference parent clock if is NULL
  MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
  clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
  clk: shmobile: div6: Avoid division by zero in .round_rate()
  clk: mxs: Fix invalid 32-bit access to frac registers
  clk: omap: compile legacy omap3 clocks conditionally
  clkdev: Export clk_register_clkdev
  clk: Add rate constraints to clocks
  clk: remove clk-private.h
  pci: xgene: do not use clk-private.h
  arm: omap2+ remove dead clock code
  clk: Make clk API return per-user struct clk instances
  clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
  clk: tegra: Add support for the Tegra132 CAR IP block
  ...
2015-02-21 12:30:30 -08:00
David S. Miller 95f873f2ff Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
	arch/arm/boot/dts/imx6sx-sdb.dts
	net/sched/cls_bpf.c

Two simple sets of overlapping changes.

Signed-off-by: David S. Miller <davem@davemloft.net>
2015-01-27 16:59:56 -08:00
Michael Turquette b80418f3c0 The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
 very strange place, but the watchdog driver needs to read the clock
 rate from it and the setting of rk3288 plls to slow mode upon suspend.
 
 Other than that some more exported clocks and a CLK_SET_RATE_PARENT
 flag for the uart clocks.
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Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.

Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.
2015-01-27 16:26:12 -08:00
Heiko Stuebner e142a4e914 clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
The pclk supplying the watchdog is controlled via the SGRF register area.
Currently we don't have any clock-type handling external clock bits like
this one. Additionally the SGRF isn't even writable in every boot mode.

But still the clock control is available and in the future someone might
want to use it. Therefore define a simple clock for the time being so
that the watchdog driver can read its rate.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-22 15:42:24 +01:00
huang lin cc6430689e clk: rockchip: add PVTM clocks on rk3288
Process-Voltage-Temperatiure Monitor block on RK3288 has two clocks:
PVTM_CORE and PVTM_GPU.

Signed-off-by: Huang Lin <hl@rock-chips.com>
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-22 15:41:20 +01:00
Kever Yang f5c3018dd0 clk: rockchip: use the clock ID for usbphy480m_src
Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-22 15:41:16 +01:00
Heiko Stübner a5e1baf7dc clk: rockchip: fix deadlock possibility in cpuclk
Lockdep reported a possible deadlock between the cpuclk lock and for example
the i2c driver.

       CPU0                    CPU1
       ----                    ----
  lock(clk_lock);
                               local_irq_disable();
                               lock(&(&i2c->lock)->rlock);
                               lock(clk_lock);
  <Interrupt>
    lock(&(&i2c->lock)->rlock);

 *** DEADLOCK ***

The generic clock-types of the core ccf already use spin_lock_irqsave when
touching clock registers, so do the same for the cpuclk.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed initialization of "flags"]
2015-01-17 11:22:39 -08:00
Roger Chen 7f186025c7 GMAC: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
modify CRU config for GMAC driver

changes since v2:
1. remove SCLK_MAC_PLL

Signed-off-by: Roger Chen <roger.chen@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-31 19:14:18 -05:00
Doug Anderson a7d9500044 clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
We've been seeing some crashes at resume time on rk3288-based systems.
On some machines they simply never wake up from suspend.  Symptoms
include:

- System clearly got to sleep OK.  Power consumption is low, the PWM
  for the PWM regulator has stopped, and the "global_pwroff" output
  shows that the system is down.

- When system tries to wake up power consumption goes up.

- No kernel resume code (which was left in PMU SRAM) ran.  We added
  some basic logging to this code (write to a location in SRAM right
  at resume time) and didn't see the logging run.

It appears that we can fix the problem by slowing down APLL before we
suspend.  On the system I tested things seemed reliable if I disabled
1.8GHz and 1.7GHz.  The Mask ROM itself tries to slow things down
(which is why PLLs are in slow mode by the time we get to the kernel),
but apparently it is crashing before it even gets there.

We'll be super paranoid and not just go down to 1.6GHz but we'll match
what the Mask ROM seems to be doing and go into slow mode.  We'll also
be safe and put all PLLs (not just APLL) into slow mode (well, except
DPLL which is needed for SDRAM).  We'll even put NPLL into slow mode
which the Mask ROM didn't do (not that it's used for much important
stuff at early resume time).

Note that the old Rockchip reference code did something just like
this, though they jammed it into pm.c instead of putting it in the
syscore ops of the clock driver.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-31 16:20:52 +01:00
Heiko Stuebner 9880d4277f clk: rockchip: fix rk3288 cpuclk core dividers
Commit 0e5bdb3f9f (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.

Reported-by: Sonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f9f ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org
2014-12-28 23:31:44 +01:00
Heiko Stuebner 12551f0239 clk: rockchip: fix rk3066 pll lock bit location
The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 2c14736c75 ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: FUKAUMI Naoki <naobsd@gmail.com>
Cc: stable@vger.kernel.org
2014-12-28 23:30:08 +01:00
Romain Perier 5039d16abe clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri
Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work
and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by
commit 78eaf6095c ("clk: rockchip: disable unused clocks").

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-21 15:21:28 +01:00
Julien CHAUVEAU caa6934ac7 clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host
This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0
and hclk_usbotg1 because these clocks must remain enabled to use the
USB controllers in host mode.

This fixes a regression introduced by commit 78eaf6095c
("clk: rockchip: disable unused clocks").

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-21 15:18:24 +01:00
Doug Anderson 221dfbae2b clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
We'd like to be able to set the clock rate of the sclk_uart clocks and
actually be able to achieve clock rates greater than 24MHz.  To do
this we need to be able to pass rate changes upward.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-21 14:15:26 +01:00
Michael Turquette b572b5f821 - clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
 - some more exported clocks
 - fixes for some clocks (typos etc) all of them not yet used
   in actual drivers
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Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

- clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
- some more exported clocks
- fixes for some clocks (typos etc) all of them not yet used
  in actual drivers
2014-11-28 21:00:16 -08:00
Alexandru M Stan 89bf26cbc1 clk: rockchip: Add support for the mmc clock phases using the framework
This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).

The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adjust the phase by 90 deg.

There's also an option to have up to 255 delay elements (40-80 picoseconds long).
This driver uses those elements (under the assumption that they're 60 ps long)
to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as
90 deg if the delay elements are as big as 80 ps, so a finer division (smaller
than 22.5) was not picked because the phase might not be monotonic anymore.

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-28 00:44:24 +01:00
Sonny Rao 6d288b169b clk: rockchip: rk3288 export i2s0_clkout for use in DT
This exposes the clock that comes out of the i2s block which generally
goes to the audio codec.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
[removed CLK_SET_RATE_PARENT from original patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-28 00:37:47 +01:00
Jeff Chen a72da7c166 clk: rockchip: use clock ID for DMC (memory controller) on rk3288
The DMC clocks need to be turned off at runtime.  Use the newly
assigned clock IDs to export them.

Signed-off-by: Jeff Chen <cym@rock-chips.com>
[dianders: split into two patches; adjusted commit msg]
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-26 18:32:28 +01:00
Heiko Stuebner dd79c0bea7 clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls
Add the new flag to gpll and cpll on rk3188 and similar and to
gpll, cpll and npll on rk3288.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:22 +01:00
Heiko Stuebner 0bb66d3b6e clk: rockchip: add optional sync to pll rate parameters
In some cases firmware brings up plls with different parameters than the ones
noted in the rate table for the specific frequency. These firmware-selected
parameters are worse than the tested ones in the pll rate tables but cannot
be changed by a simple clk_set_rate call when the rate stays the same.

Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback
that checks the runtime-parameters against the matching rate table entry
and adjusts them to the table-ones if necessary.

If no rate table is set or the current rate does not match any rate-table
entry no changes are made.

Being able to limit this adjustment to specific plls is necessary to not
touch the ones supplying core components like the apll and dpll supplying
the armcores and dram.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:18 +01:00
Heiko Stuebner d0e7a0ca4b clk: rockchip: setup pll_mux data earlier
In some cases we might need to access the data of the pll mux before the actual
mux gets registered - like in the following patch adding an init-callback.

Therefore populate pll_mux before registering the core pll-clock.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:13 +01:00
Heiko Stuebner 4f8a7c549f clk: rockchip: add ability to specify pll-specific flags
This adds a flag parameter to plls that allows us to create
special flags to tweak the behaviour of the plls if necessary.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:07 +01:00
Michael Turquette da57b46010 Merge branch 'clk-fixes' into clk-next 2014-11-24 17:45:33 -08:00
Julien CHAUVEAU 12c0a0e81e clk: rockchip: fix rk3188 USB HSIC PHY clock divider
The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-23 01:55:14 +01:00
Julien CHAUVEAU b7bdb7f45e clk: rockchip: fix clock gate for rk3188 spdif_pre
In rk3188 clock branches, spdif_pre gate was set to RK2928_CLKGATE_CON(13) bit 13.
This appears to be a copy-paste error because such a register does not exist.
We correct it to RK2928_CLKGATE_CON(0) and find out that the rk3188 spdif clock
is the same as the rk3066 spdif clock, so we move it to the common clock branches.

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-23 00:39:57 +01:00
Julien CHAUVEAU f0c71718c2 clk: rockchip: fix parent clock for rk3188 hclk_lcdc1
The parent clock for hclk_lcdc1 was set to aclk_cpu instead of hclk_cpu.

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-18 16:40:46 +01:00
James Hogan e6d5e7d90b clk-divider: Fix READ_ONLY when divider > 1
Commit 79c6ab5095 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.

However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.

Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.

For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Max Schwarz <max.schwarz@online.de>
Cc: <stable@vger.kernel.org> # v3.16+
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 11:13:52 -08:00
Kever Yang 29e9446851 clk: rockchip: fix clock select order for rk3288 usbphy480m_src
According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-16 00:40:19 +01:00
Kever Yang 0132234160 clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register
According to rk3288 trm, the clk_usbphy480m_gate is located at
bit 14 of CRU_CLKGATE5_CON register.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-16 00:02:24 +01:00
Dmitry Torokhov 9aa75e6e09 clk: rockchip: ensure HCLK_VIO2_H2P and PCLK_VIO2_H2P stay enabled
Currently there is no driver owning these clocks and they have to stay
up for the system to function properly, so let's mark them as
CLK_IGNORE_UNUSED.

Without this patch we have trouble with suspend/resume and we have
trouble turning the eDP back on if it ever idles off.

Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-13 11:55:45 +01:00
Chris Zhong 33aa59c232 clk: rockchip: rk3288: add suspend and resume
save and restore some clks, which might be changed in suspend.

Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-10 20:56:42 +01:00
Heiko Stübner d1f931be7c clk: rockchip: fix rk3188 hsadc_frac definition
The arguments to COMPOSITE_FRAC for hsadc_frac were mangled, leaving out the
the general clock flags argument. This results in strange effects, as only
sometimes a zero-division is reported as the wrong register is read.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-07 23:41:14 +01:00
Kever Yang 78eaf6095c clk: rockchip: disable unused clocks
The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-04 22:52:51 +01:00
Kever Yang 49ed9ee442 clk: rockchip: change PLL setting for better clock jitter
dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we
use 594MHz for clock source of dclk_vop0/1.

HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit:
TMDS clock(MHz)		CTS require jitter (ps)
	297		84.2
	148.5		168
	74.25		336
	27		1247

PLL BW and VCO frequency effects the jitter of PLL output clock,
clock jitter is better if BW is lower or VCO frequency is higher.

If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4),
the TMDS Clock jitter is higher than 250ps, which means we can't
pass the test when TMDS clock is 297MHz or 148.5MHz.

If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
the TMDS Clock jitter is about 60ps and we can pass all test case.

So we need this patch to make hdmi si test pass.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-29 20:27:20 +01:00
Kever Yang 89c107a88d clk: rockchip: add npll to source of sclk_gpu
The possible sources for the rk3288-gpu-clock also include the npll,
making it the same list of sources as for uart0.

This patch make a common source for uart0 pll src and sclk_gpu,
so that gpu can get its clock from npll.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 14:00:18 +02:00
Jianqun 8f06f5d392 clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout
Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout
to select between its two parent without being able influence the core
i2s clock.

Tested on rk3288 board, suggested by Heiko.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 13:53:56 +02:00
Kever Yang cd9b4609a5 clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
This patch add 400MHz and 500MHz to clock rate table for rk3288.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 12:00:56 +02:00
Doug Anderson 61e309f322 clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_pre
We'd like to be able to call clk_set_rate() on aclk_cpu (a gate) at
bootup.  In order for this to have any effect we need its parent
(aclk_cpu_pre) to percolate the rate change to _its_ parent
(aclk_cpu_src).  Add CLK_SET_RATE_PARENT to make this happen.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 12:00:55 +02:00
Sonny Rao de7d6c3eeb clk: rockchip: fix parent for spdif_8ch_frac on rk3288
The parent should be spdif_8ch_pre not spdif_8ch_src, which doesn't
exist and looks to be a typo.  The TRM also confirms this.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 12:00:55 +02:00
Heiko Stübner 6f1294b5a8 clk: rockchip: add restart handler
Add infrastructure to write the correct value to the restart register and
register the restart notifier for both rk3188 (including rk3066) and rk3288.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-10-01 14:11:42 +02:00
Jianqun fc69ed70c1 clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
The relation of i2s nodes as follows:
          i2s_src               0           0            594000000  0
             i2s_frac           0           0            11289600   0
                i2s_pre         0           0            11289600   0
                   sclk_i2s0    0           0            11289600   0
                   i2s0_clkout  0           0            11289600   0
                      hclk_i2s0 1           1            99000000   0

sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
"i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".

Tested on rk3288 board using max98090, with command "aplay <music.wav>"

Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-01 10:55:13 +02:00
Heiko Stuebner 0e5bdb3f9f clk: rockchip: switch to using the new cpuclk type for armclk
This adds the necessary soc-specific divider values and switches the armclk
to use the newly introduced cpuclk type.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:46 +02:00
Heiko Stuebner f6fba5f696 clk: rockchip: add new clock-type for the cpuclk
When changing the armclk on Rockchip SoCs it is supposed to be reparented
to an alternate parent before changing the underlying pll and back after
the change. Additionally there exist clocks that are very tightly bound to
the armclk whose divider values are set according to the armclk rate.

Add a special clock-type to handle all that. The rate table and divider
values will be supplied from the soc-specific clock controllers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
On a rk3288-board:
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:41 +02:00
Heiko Stuebner 2b9bceeab7 clk: rockchip: make tightly bound armclk child-clocks read-only
Rockchip SoCs contain clocks tightly bound to the armclk, where the best
rate / divider is supplied by the vendor after careful measuring.
Often this ideal rate may be greater than the current rate.

Therefore prevent the ccf from trying to set these dividers itself by
setting them to read-only.

In the case of the rk3066, this also includes the aclk_cpu, which makes it
necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...)
into individual definitions for rk3066 and rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:17 +02:00
Heiko Stuebner f5f7004fde clk: rockchip: reparent aclk_cpu_pre to the gpll
aclk_cpu_pre on the rk3188 can either be sourced from the armclk or the gpll.
To reduce complexity on apll changes caused by cpufreq, reparent it always
to the gpll source.

If really necessary it could be reparented back on a per board level using
the assigned-clocks mechanism.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-09-27 17:57:14 +02:00
Jianqun ee17eb83c4 clk: rockchip: fix rk3288 pll status register location
In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>

Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:10 +02:00
Heiko Stuebner 11ff376fcf clk: rockchip: fix rk3066 pll status register location
The register providing the pll lock status is at a different address on the
rk3066. The error became apparent while working on cpufreq support for
the rockchip SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-09-27 17:57:07 +02:00
Doug Anderson 9c030ea70b clk: rockchip: change pll rate without a clk-notifier
The Rockchip PLL code switches into slow mode (AKA bypass more AKA
24MHz mode) before actually changing the PLL.  This keeps anyone from
using the PLL while it's changing.  However, in all known Rockchip
SoCs nobody should ever see the 24MHz when changing the PLL supplying
the armclk because we should reparent children to an alternate
(faster than 24MHz) PLL.

One problem is that the code to switch to an alternate parent was
running in PRE_RATE_CHANGE.  ...and the code to switch to slow mode
was _also_ running in PRE_RATE_CHANGE.  That meant there was no real
guarantee that we would switch to an alternate parent before switching
to 24MHz mode.

Let's move the switch to "slow mode" straight into
rockchip_rk3066_pll_set_rate().  That means we're guaranteed that the
24MHz is really a last-resort.

Note that without this change on real systems we were the code to
switch to an alternate parent at 24MHz.  In some older versions of
that code we'd appy a (temporary) / 5 to the 24MHz causing us to run
at 4.8MHz.  That wasn't enough to service USB interrupts in some cases
and could lead to a system hang.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-09-27 17:57:04 +02:00
Mike Turquette fa531042ac Merge branch 'clk-next-rockchip' into clk-next 2014-09-25 15:48:04 -07:00
Kever Yang cd24850292 clk: rockchip: add clock node in PD_VIDEO
This patch add the clock node in PD_VIDEO

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 15:47:45 -07:00
Kever Yang 89d83e14f4 clk: rockchip: use the clock id for nodes init
This patch use the new defined clock ID to initial the clock nodes.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 15:06:43 -07:00
Heiko Stübner d1a559a1cb clk: rockchip: add missing rk3288 npll rate table
The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 14:48:40 -07:00
Mark yao f9c0d14062 clk: rockchip: rk3288: fix softreset register count
The rk3288 actually has 12 softresets, so fix the register count.

Signed-off-by: Mark yao <mark.yao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 14:45:58 -07:00
Mike Turquette a52ae5a755 Merge branch 'clk-fixes' into clk-next 2014-09-17 11:47:56 -07:00
Heiko Stübner 2fed71e57a clk: rockchip: also protect hclk_peri as critical
The dwc2 usb controller also uses agressive clock gating, which in this
case leads to hclk_peri getting disabled and hanging the system.
Therefore move it to the critical clocks until we also control that
part of the system.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-10 10:42:02 -07:00
Doug Anderson f4ee3c8446 clk: rockchip: Fix the clocks for i2c1 and i2c2
The clocks for i2c1 and i2c2 are flipped.  The clock tree matched the
Technical Reference Manual (TRM) but the TRM was wrong.  Swap them in
the clock tree.  This was determined experimentally (by Addy) and
confirmed by the Rockchip IC team.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Reported-by: Addy Ke <addy.ke@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-03 11:24:50 -07:00
Heiko Stübner fe94f974e9 clk: rockchip: protect critical clocks from getting disabled
The clock-tree contains clocks that should never get disabled automatically.
One example are the base ACLKs, the base supplies for all peripherals.

Therefore add a structure similar to the sunxi clock-tree to protect these
special clocks from being disabled.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:18 -07:00
Heiko Stübner 1a4b181995 clk: rockchip: make rockchip_clk_register_branch static
It is only used locally in clk/rockchip/clk.c and thus can be static.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:17 -07:00
Heiko Stübner b2155a71a7 clk: rockchip: implement the fraction divider branch type
Rockchip SoCs may provide fraction dividers for some clocks, mostly for
i2s and uarts. In contrast to the other registers, these do not use
the hiword-mask paradigm, but instead split the register into the upper
16 bit for the nominator and the lower 16 bit for the denominator.

The common clock framework got a generic fractional divider clock type
recently that can accomodate this setting easily. All currently known
fraction dividers have a separate gate too, therefore implement the
divider as composite using the ops-struct from fractional_divider clock
and add the gate if necessary.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:17 -07:00
Heiko Stübner b9e4ba5416 clk: rockchip: add clock controller for rk3288
Add the clock tree definition for the new rk3288 SoC.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:10 -07:00
Heiko Stübner 2c14736c75 clk: rockchip: add clock driver for rk3188 and rk3066 clocks
This adds a clock driver that handles the specific muxes, dividers and gates
of rk3188 and rk3066 SoCs.

The structure of the clock list resembles the arrangement of their
counterparts in the clock architecture diagrams found in the SoC
documentation.

Clocks exported to the clock provider are currently limited to well known
or measured ones. So additional clock exports may be necessary in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:09 -07:00
Heiko Stübner 85fa0c7f8d clk: rockchip: add reset controller
All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset-
controller for SoC peripherals in their clock controller.
While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change
register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary.
To be compatible with both schemes the reset controller takes a flag to
decide which scheme to use, similar to the other HIWORD_MASK flags used in the
clock framework.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:07 -07:00
Heiko Stübner 90c5902540 clk: rockchip: add clock type for pll clocks and pll used on rk3066
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to
handle their plls:
                       |--\
xin32k ----------------|mux\
xin24m -----| pll |----|pll|--- pll output
       \---------------|src/
                       |--/

The pll output is sourced from 1 of 3 sources, the actual pll being one of
them. To change the pll frequency it is imperative to remux it to another
source beforehand. This is done by adding a clock-listener to the pll that
handles the remuxing before and after the rate change.

The output mux is implemented as a separate clock to make use of already
existing common-clock features for disabling the pll if one of the other
two sources is used.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:06 -07:00
Heiko Stübner a245fecbb8 clk: rockchip: add basic infrastructure for clock branches
This adds infrastructure for registering clock branches. On Rockchip SoCs
most clock branches are a combination of mux,divider and gate components,
thus a composite clock is used when appropriate.

Clock branches are supposed to be declared in an array using the COMPOSITE*
or MUX, etc makros defined in the header and then registered using
rockchip_clk_register_branches.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:06 -07:00
Rob Herring 5c46f43f08 clk: rockchip: fix function type for CLK_OF_DECLARE
Adding function type checking to CLK_OF_DECLARE found a type mismatch with
rk2928_gate_clk_init. The function only takes a single struct device_node
parameter.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-05-20 14:25:22 -05:00
Heiko Stübner 646572c77d clk: add support for Rockchip gate clocks
This adds basic support for gate-clocks on Rockchip SoCs.
There are 16 gates in each register and use the HIWORD_MASK
mechanism for changing gate settings.

The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all 160 gates can be put into
one gate clock spanning all registers or they can be divided into
the 10 individual gates containing 16 clocks each.
The code supports both approaches.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-20 15:58:27 -07:00