2 Commits

Author	SHA1	Message	Date
Andrea Venturi	8f0767611a	clk: sunxi: mod1 clock should modify it's parent ... add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>	2016-04-22 00:29:21 +02:00
Emilio López	9b038bc58a	clk: sunxi: mod1 clock support ... The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>	2015-10-21 21:51:29 +02:00