Commit Graph

18 Commits

Author SHA1 Message Date
Geert Uytterhoeven e7ad751628 pinctrl: sh-pfc: r8a77970: Remove MMC_{CD,WP}
Hardware Manual Errata for rev. 1.50 of March 26, 2019 removed the bit
definitions for MMC_CD and MMC_WP in the documentation for the IPSR6 and
IPSR7 registers, as these pin functionalities do not exist on R-Car
V3M.

Remove the definitions, and the corrresponding pins and groups.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven bd79c92039 pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variant
There are two variants of the CPU_ALL_PORT() macro in use:
  1. A three-parameter variant, to be provided for SoCs with a linear
     GPIO pin space ("PORT style"),
  2. A two-parameter variant, to be provided for SoCs with 32-port GPIO
     banks ("GP port style").

Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and
to increase naming consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven baaa2effc6 pinctrl: sh-pfc: r8a77970: Fix spacing
Replace "F_(0,0)" by "F_(0, 0)".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-04 12:01:18 +02:00
Takeshi Kihara 624a7a12cc pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of
Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and
IPSR registers are renamed to RTS{0,1,3,4}_#.
This patch updates the pin control drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car H3 ES1.x, V3M, V3H, and D3]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:02:40 +02:00
Takeshi Kihara 662dc924a0 pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
Jun 4, 2018, the CC5_OSCOUT pin is removed.  Update the pin control
drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car V3M, V3H]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:02:22 +02:00
Geert Uytterhoeven 69f7be1c63 pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
Currently the PINMUX_CFG_REG_VAR() macro must be followed by
initialization data, specifying all enum IDs.  Hence the macro itself
does not know anything about the enum IDs, preventing the macro from
performing any validation on it.

Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence both the register field widths and the enum
IDs are wrapped using the GROUP() macro.

No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:57:58 +02:00
Geert Uytterhoeven efca8da0c5 pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
Currently the PINMUX_CFG_REG() macro must be followed by initialization
data, specifying all enum IDs.  Hence the macro itself does not know
anything about the enum IDs, preventing the macro from performing any
validation on it.

Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence the enum IDs are wrapped using a new macro
GROUPS().

No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:57:55 +02:00
Geert Uytterhoeven 2f9f5094f8 pinctrl: sh-pfc: Add missing #include <linux/errno.h>
Source files using -Exxx error codes should include <linux/errno.h>.
On ARM, this header file is included indirectly; on SuperH, it is not,
leading to "error: ‘EINVAL’ undeclared" failures when enabling
compile-testing later.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 09:57:50 +02:00
Marek Vasut d92ee9cf8e pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
The TDSELCTRL register is responsible for configuring the SDHI/MMC clock
return path delay and may be adjusted by the bootloader. Retain the value
across suspend/resume to prevent hardware instability after resume.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-03-18 16:56:50 +01:00
Geert Uytterhoeven 1c5c110175 pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018)
renamed the various miscellaneous I/O control registers (IOCTRLx) on
R-Car V3M, to reflect better their actual purposes, and matching other
SoCs.

Update the code to match this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-03-18 16:56:49 +01:00
Geert Uytterhoeven 81c585c96b pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
Use union vin_data12 and VIN_DATA_PIN_GROUP() to reduce redundancies in
pin definitions for the VIN0 and VIN1 channels.

This reduces kernel size by 288 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-01-21 13:24:52 +01:00
Geert Uytterhoeven 67d7745bc7 pinctrl: sh-pfc: r8a77970: Add missing MOD_SEL0 field
The Module Select Register 0 contains 20 (= 5 x 4) reserved bits, and 12
single-bit fields, but the variable field descriptor lacks a field of 4
reserved bits.

Fixes: b92ac66a18 ("pinctrl: sh-pfc: Add R8A77970 PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18 11:25:56 +01:00
Dmitry Shifrin 3ad8fbd83f pinctrl: sh-pfc: r8a77970: Add QSPI pins, groups, and functions
Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver.

[Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/
SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to
be in the alphanumeric order, removed unneeded empty lines, renamed the
patch.]

Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:08:25 +01:00
Kuninori Morimoto 63b6d7e762 pinctrl: sh-pfc: Convert to SPDX identifiers
This patch updates license to use SPDX-License-Identifier
instead of verbose license text.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:25:32 +02:00
Niklas Söderlund 550b6f7e8c pinctrl: sh-pfc: r8a77970: remove SH_PFC_PIN_CFG_DRIVE_STRENGTH flag
The datasheet does not document any registers to control drive strength,
and no drive strength registers are for this reason described for this
SoC. The flags indicating that drive strength can be controlled are
however set for some pins in the driver.

This leads to a NULL pointer dereference when the sh-pfc core tries to
access the struct describing the drive strength registers, for example
when reading the sysfs file pinconf-pins.

Fix this by removing the SH_PFC_PIN_CFG_DRIVE_STRENGTH from all pins.

Fixes: b92ac66a18 ("pinctrl: sh-pfc: Add R8A77970 PFC support")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-14 12:47:04 +02:00
Sergei Shtylyov f9931a4d87 pinctrl: sh-pfc: r8a77970: Fix pin I/O voltage control support
I've included the pin I/O voltage control into the R8A77970 PFC driver but
it was incomplete because:
- SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly;
- sh_pfc_soc_info::ioctrl_regs wasn't set at all...

Fixes: b92ac66a18 ("pinctrl: sh-pfc: Add R8A77970 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-16 13:31:42 +02:00
Sergei Shtylyov b3cbd8a567 pinctrl: sh-pfc: r8a77970: Add EtherAVB pin groups
Add the EtherAVB pin groups to the R8A77970 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-14 14:39:52 +01:00
Sergei Shtylyov b92ac66a18 pinctrl: sh-pfc: Add R8A77970 PFC support
Add the PFC support for the R8A77970 SoC including pin groups for some
on-chip devices such as CAN-FD, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM,
VIN...

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop EtherAVB for now]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-05 14:14:39 +01:00