Similar to commit a9f0c0e563 ("clk: rockchip: fix rk3188 sclk_smc
gate data") there is one other gate clock in the rk3188 clock driver
with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Fixes the signedness bug returning '(-22)' on the return type by removing the
sanity checker in rockchip_ddrclk_get_parent(). The function should return
and unsigned value only and it's safe to remove the sanity checker as the
core functions that call get_parent like clk_core_get_parent_by_index already
ensures the validity of the clk index returned (index >= core->num_parents).
Fixes: a4f182bf81 ("clk: rockchip: add new clock-type for the ddrclk")
Cc: stable@vger.kernel.org
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add and correct PLL rates for better hdmi output.
This includes minimizing jitter on 213 MHz for better 71 MHz,
250.5 MHz for better 83.5 MHz, 428 MHz for better 25.175 Mhz,
low jitter 273 MHz for better 68.25 mhz, 356 MHz for better 118.68 Mhz
and 300MHz.
Increase the used Fvco for 308, 324 MHz, 292.5 MHz, 273.6 MHz,
238 MHz and 216 MHz.
And add some additional rates allowing to reach better hdmi-related
rates in general.
These match the rates used by ChromeOS, so have been quite widely tested.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
from power on and the VDD_LOG is about 0.9V. When the kernel boots
normally into the system, the PWM2 keeps outputing PWM signal.
But the kernel hangs randomly after "Starting kernel ..." line on that
board. When it happens, PWM2 outputs high level which causes VDD_LOG
drops to 0.4V below the normal operating voltage.
By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
PWM clock is ensured to be prepared at startup and the PWM2 output is
normal. After repeated tests, the early boot hang is gone.
This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.
Signed-off-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Register, shift and mask were wrong according to datasheet.
Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Cc: stable@vger.kernel.org
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new px30 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The new Rockchip socs have optional half divider:
The formula is shown as:
freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.
So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specific
ids to the devicetree.
As the old code was in the kernel for 1-2 releases when the new mode
of operation was added we kept it for backwards compatibility.
That deprecation notice is in the binding since july 2014, so nearly
4 years now and I think it's time to drop the old cruft.
Especially as at the time using the mainline kernel on Rockchip devices
was not really possible, except for experiments on the really old socs of
the rk3066 + rk3188 line, so there shouldn't be any devicetrees still
around that rely on that code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
match_string() returns the index of an array for a matching string,
which can be used intead of open coded variant.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The newly added clock notifier may return an error code but so far the
error output in the function would only return an error pointer from
registering the clock.
So when the clock notifier fails the clock would be unregistered but the
return would still be the clock pointer which could then not be
dereferenced correctly. So fix the error handling to prevent that.
Fixes: 60cf09e45f ("clk: rockchip: Restore the clock phase after the rate was changed")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We can't restore every phase, for instance the invalid phase and
the phase for coming rate which is out of the scope of boards'
ability. And this patch also corrects the error path to return
invalid pointer to clk if clk_notifier_register failed introduced
by the same offending commit.
Fixes: 60cf09e45f ("clk: rockchip: Restore the clock phase after the rate was changed")
Reported-by: wlq <wlq@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: wlq <wlq@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if
clock rate is zero") catches some gremlins for clk-rk3328.c that the
parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not
sclk_{sdmmc, sdio, emmc}.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
if clock rate is zero") catches one gremlin again for clk-rk3228.c
that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
sclk_sdmmc. However, the naming of the sdmmc clocks varies in the
manual with the card clock having the 0 while the hclk is named
without appended 0. So standardize one one format to prevent
confusion, as there also is only one (non-sdio) mmc controller on
the soc.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There are many factors affecting the clock phase, including clock
rate, temperature, logic voltage and silicon process, etc. But clock
rate is the most significant one here, and the driver should be aware
of the change of the clock rate. As mmc controller need a fixed phase
after tuning was completed, at least before explicitly doing re-tune,
so this patch try to restore the clock phase by monitoring the event
of rate change.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rockchip_clk_register_branch() and rockchip_clk_register_frac_branch()
should free the memory internally when seeing any failure.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
dclk_lcdc can be sourced from a general pll source as well
as the hdmiphy's pll output. We will want to set this source
by hand (to the system-pll-source in most cases) and also
want rate changes to this clock to be able to also touch
the pll source clock if needed, so add CLK_SET_RATE_PARENT
and CLK_SET_RATE_NO_REPARENT for dclk_lcdc.
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
[ammended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
NIU clocks are supplying the interconnect connections to specific
peripherals and are currently not controlled in any way.
So to prevent things falling apart at strange moments, mark all
niu clocks as critical.
Most of them where marked as CLK_IGNORE_UNUSED, but that doesn't
help if a parent clock then gets disabled.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The clock wrongly was called hclk_vio and exported, while it actually is
a clock of the interconnect-vio connection and should therefore be always
on till we actually model the interconnect.
So fix that and don't export it as HCLK_VIO.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
large change that introduces runtime PM support to the clk framework. Now we
properly call runtime PM operations on the device providing a clk when the clk
is in use. This helps on SoCs where the clks provided by a device need
something to be powered on before using the clks, like power domains or
regulators. It also helps power those things down when clks aren't in use. The
other core change is a devm API addition for clk providers so we can get rid of
a bunch of clk driver remove functions that are just doing
of_clk_del_provider().
Outside of the core, we have the usual addition of clk drivers and smattering
of non-critical fixes to existing drivers. The biggest diff is support for
Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch
of data.
By the way, we're trying something new here where we build the tree up with
topic branches. We plan to work this into our workflow so that we don't step
on each other's toes, and so the fixes branch can be merged on an as-needed
basis.
Core:
- Runtime PM support for clk providers
- devm API for of_clk_add_hw_provider()
New Drivers:
- Mediatek MT2712 and MT7622
- Renesas R-Car V3M SoC
Updates:
- Runtime PM support for Samsung exynos5433/exynos4412 providers
- Removal of clkdev aliases on Samsung SoCs
- Convert clk-gpio to use gpio descriptors
- Various driver cleanups to match kernel coding style
- Amlogic Video Processing Unit VPU and VAPB clks
- Sigma-delta modulation for Allwinner audio PLLs
- Allwinner A83t Display clks
- Support for the second display unit clock on Renesas RZ/G1E
- Suspend/resume support for Renesas R-Car Gen3 CPG/MSSR
- New clock ids for Rockchip rk3188 and rk3368 SoCs
- Various 'const' markings on clk_ops structures
- RPM clk support on Qualcomm MSM8996/MSM8660 SoCs
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have two changes to the core framework this time around.
The first being a large change that introduces runtime PM support to
the clk framework. Now we properly call runtime PM operations on the
device providing a clk when the clk is in use. This helps on SoCs
where the clks provided by a device need something to be powered on
before using the clks, like power domains or regulators. It also helps
power those things down when clks aren't in use.
The other core change is a devm API addition for clk providers so we
can get rid of a bunch of clk driver remove functions that are just
doing of_clk_del_provider().
Outside of the core, we have the usual addition of clk drivers and
smattering of non-critical fixes to existing drivers. The biggest diff
is support for Mediatek MT2712 and MT7622 SoCs, but those patches
really just add a bunch of data.
By the way, we're trying something new here where we build the tree up
with topic branches. We plan to work this into our workflow so that we
don't step on each other's toes, and so the fixes branch can be merged
on an as-needed basis.
Summary:
Core:
- runtime PM support for clk providers
- devm API for of_clk_add_hw_provider()
New Drivers:
- Mediatek MT2712 and MT7622
- Renesas R-Car V3M SoC
Updates:
- runtime PM support for Samsung exynos5433/exynos4412 providers
- removal of clkdev aliases on Samsung SoCs
- convert clk-gpio to use gpio descriptors
- various driver cleanups to match kernel coding style
- Amlogic Video Processing Unit VPU and VAPB clks
- sigma-delta modulation for Allwinner audio PLLs
- Allwinner A83t Display clks
- support for the second display unit clock on Renesas RZ/G1E
- suspend/resume support for Renesas R-Car Gen3 CPG/MSSR
- new clock ids for Rockchip rk3188 and rk3368 SoCs
- various 'const' markings on clk_ops structures
- RPM clk support on Qualcomm MSM8996/MSM8660 SoCs"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
clk: stm32h7: fix test of clock config
clk: pxa: fix building on older compilers
clk: sunxi-ng: a83t: Fix i2c buses bits
clk: ti: dra7-atl-clock: fix child-node lookups
clk: qcom: common: fix legacy board-clock registration
clk: uniphier: fix DAPLL2 clock rate of Pro5
clk: uniphier: fix parent of miodmac clock data
clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep()
clk: hi3660: fix incorrect uart3 clock freqency
clk: kona-setup: Delete error messages for failed memory allocations
ARC: clk: fix spelling mistake: "configurarion" -> "configuration"
clk: cdce925: remove redundant check for non-null parent_name
clk: versatile: Improve sizeof() usage
clk: versatile: Delete error messages for failed memory allocations
clk: ux500: Improve sizeof() usage
clk: ux500: Delete error messages for failed memory allocations
clk: spear: Delete error messages for failed memory allocations
clk: ti: Delete error messages for failed memory allocations
clk: mmp: Adjust checks for NULL pointers
...
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
superfluous memory allocation error message.
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Merge tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk drivers updates from Heiko Stuebner:
- new clock ids for rk3188 and rk3368
- removal of a superfluous memory allocation error message
* tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: use new cif/vdpu clock ids on rk3188
clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
clk: rockchip: add more rk3188 graphics clock ids
clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()
This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
sclk_timer5 is for arm arch counter, so need always on.
but no dts node to handle this clk, so make it as critical clock
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A copy-paste error made them use the wrong bits in the register.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pclk_pmu need always on, and no dts node to handle this clk,
so make it as critical clock
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Silence the sparse warning
clk/rockchip/clk.c:172:6: warning: symbol 'rockchip_fractional_approximation' was not declared. Should it be static?
Cc: Elaine Zhang <zhangqing@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The source clock ordering is wrong, as shown in the TRM:
cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This MAC has no internal phy for rv1108 and the whole clock
infrastructure hasn't been used yet, so is safe to fix.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In some special circumstances, may be need to reparent clk for sclk_sdio_src.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>From Rockchips fractional divider description:
3.1.9 Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
fractional divider. Generally you must set that denominator is 20 times
larger than numerator to generate precise clock frequency. So the
fractional divider applies only to generate low frequency clock like
I2S, UART.
Therefore add a special approximation function that handles this
special requirement.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rk3128 and rk3126 have some gate registers describe differences.
So need to make some distinctions.
The RK3126 and RK3128 Same clock description we move it to
the common clock branches.
And the different clks description use the own clock branches.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
the bus/periph/nclk_ddrupctl/pclk_ddrmon/pclk_acodecphy/pclk_pmu
no driver to handle them,
Chip design requirements for these clock to always on.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rename some of clks to keep the consistency with the TRM.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1. fix up the parent name
2. remove the CLK_IGNORE_UNUSED flag for some clk not need to always on.
3. fix up some clks regs describe error.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the description of the missing clock,
make the clock more complete.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
fix up the lock_shift describe error.
remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
fix up the cpuclk rates table for support more freqs.
fix up the mux_core_mask describe error.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.
The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,
The pmu_hclk_otg0 is Chip design defect, must be always on,
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.
The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,
The pmu_hclk_otg0 is Chip design defect, must be always on,
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.
The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,
The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.
All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).
The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk_testout1 and clk_testout2 are used for camera handling, so add their ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
support more cpu freq, and add armcore div setting.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
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Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
General rockchip clock changes for 4.12. Contains some new clock-ids
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add pll_wait_lock for pll_enable
clk: rockchip: rename RK1108 to RV1108
dt-bindings: rk1108-cru: rename RK1108 to RV1108
clk: rockchip: mark some rk3368 core-clks as critical
clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
clk: rockchip: fix up rk3368 timer-ids
clk: rockchip: add rk3328 clk_mac2io_ext ID
clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
If pll is power down,when power up pll need wait pll lock.
The reference documents section:
PLL frequency change and lock check
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[include rename in rk1108.dtsi to prevent compile errors]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the newly introduced clk type for muxes in the grf we now can
describe some missing clocks, like the clk_gmac2io and clk_gmac2phy
that selects between clk_mac2io_src and gmac_clkin based on a bit
set in the general register files.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.
This turned up during the 4.11 merge-window when commit
6a171b2993 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.
Fixes: 5190c08b29 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The PMU Cortex M0 on rk3399 is intended to be used for things like
DDRFreq transitions, suspend/resume, and other things that are the
purview of ARM Trusted Firmware and not the kernel. As such, the
kernel shouldn't be messing with the clocks. Add CLK_IGNORE_UNUSED to
these clocks.
Without this change, the following was observed on a Chromebook with a
rk3399 (using not-yet-upstream ARM Trusted Firmware code and
not-yet-upstream kernel code based on kernel-4.4):
1. We init the clock framework.
2. We start up "DDRFreq", which causes ATF to occasionally fire up the
M0 for transitions. Each time ATF fires up the M0 it will turn on
these clocks and each time it is done it will turn them off.
3. We finally get to the the part of the kernel that calls
clk_disable_unused() and we disables the clocks.
You can see the race above. Basically everything is fine as long as
ARM Trusted Firmware isn't starting up the M0 at exactly the same time
that the kernel is disabling unused clocks. ...but if the race
happens then we go boom.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
NIU clocks are related to the interconnect and it's important to other blocks.
Since we don't have a driver to handle it, we should always enable it to avoid
casually close.
Make all of them critical,so that we don't have to each clock on its own
once things break.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
[dropped the matching CLK_IGNORE_UNUSED flags]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reference the newly added vip clock-ids in the clock-tree.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5.
Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the newly added clock ids to the clock entries of the rk3066/rk3188
clock driver. We won't be needing them in the kernel for a bit yet
but as they're used in the new u-boot ddr setup code/dts we should make
sure the clock ids stay identical and do not differ.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reference the newly added isp clock-ids in the clock-tree.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
When we used to defer setting the "grf" member to
rockchip_clk_get_grf() it was important to init the "grf" member to an
error value in rockchip_clk_init(). With recent changes, we now set
"grf" right in rockchip_clk_init() (two lines below the place where we
initted it). That makes the old init useless. Get rid of it.
Fixes: 6f339dc271 ("clk: rockchip: lookup General Register Files in rockchip_clk_init")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new rk3328 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask, the rk3328 soc
pll mode only one bit(rk3036 soc have two bits)
so these should be independent and separate from
the series of rk3328s.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the newly introduced clk type for muxes in the grf we now can
describe some missing clocks, like the aclk_vcodec that selects between
aclk_vdpu and aclk_vepu based on a bit set in the general register files.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the general register
files. Add a clock-type that can control these as well, so that we
don't need to work around them being absent.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Pull rockchip clk driver updates from Heiko Stuebner:
A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP),
a fix making sure the cpuclk rate is actually valid, before trying to
set it and a copy-paste fix for the rk3399's testclk.
* tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add clock controller for rk1108
dt-bindings: add documentation for rk1108 cru
clk: rockchip: add dt-binding header for rk1108
clk: rockchip: fix copy-paste error in rk3399 testclk
clk: rockchip: validity should be checked prior to cpu clock rate change
Add the clock tree definition and driver for rk1108 SoC.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(rk3036, rk3399) does now take into account the mode that the PLL is
actually running at.
As always also some additional and optimized PLL rates for rk3066 and
rk3399, some additional clock ids for rk3066 and some additional clocks
on rk3399 are now sucessfully handled inside their respective driver.
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Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk driver updates from Heiko Stuebner:
PLL initialization for PLLs having both an integral and fractional mode
(rk3036, rk3399) does now take into account the mode that the PLL is
actually running at.
As always also some additional and optimized PLL rates for rk3066 and
rk3399, some additional clock ids for rk3066 and some additional clocks
on rk3399 are now sucessfully handled inside their respective driver.
* tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused
clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree
clk: rockchip: add 400MHz to rk3066 clock rates table
clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399
clk: rockchip: Use clock ids for cpu and peri clocks on rk3066
clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
clk: rockchip: add 533.25MHz to rk3399 clock rates table
If validity is not checked prior to clock rate change, clk_set_rate(
cpu_clk, unsupported_rate) will return success, but the real clock rate
change operation is prohibited in post clock change event. Alough post
clock change event will report error due to unsupported clock rate is
set, but this error message is ignored by clock framework.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Tested-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockchip RK3399 PLLs can be used in two separate modes: integral and
fractional. We can select between these two modes with the unambiguously
named DSMPD bit.
During boot, we check all PLL settings to confirm that they match our
PLL table for that frequency, and reinitialize the PLLs where they
don't. The settings checked for this include the fractional divider
field that is only used in fractional mode, even if we're in integral
mode (DSMPD = 1) and that field has no effect.
This patch changes the check to only compare the fractional divider if
we're actually in fractional mode. This way, we won't reinitialize the
PLL in cases where there's absolutely no reason for that, which may
avoid glitching child clocks that should better not be glitched (e.g.
PWM regulators).
Signed-off-by: Julius Werner <jwerner@chromium.org>
[cloned the fix to the pretty similar rk3036 pll]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We need this to init PLL_CPLL to 400MHz at boot.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.
Let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add bindings for ACLK_CPU, HCLK_CPU, PCLK_CPU, ACLK_PERI, HCLK_PERI, PCLK_PERI.
We need this to init it's rate at boot time.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rockchip_clk_register_ddrclk should not return NULL when failing
to call clk_register, otherwise rockchip_clk_register_branches
prints "unknown clock type". The actual case is that it's a known
clock type but we fail to register it, which may makes user confuse
the reason of failure. And the pr_err here is pointless as
rockchip_clk_register_branches will also print the similar message.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.
As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.
Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.
And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.
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Merge tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
The biggest addition is probably the special clock-type for ddr clock
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.
As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.
Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.
And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.
* tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: use the dclk_vop_frac clock ids on rk3399
clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers
clk: rockchip: add 2016M to big cpu clk rate table on rk3399
clk: rockchip: add rk3399 ddr clock support
clk: rockchip: add dclk_vop_frac ids for rk3399 vop
clk: rockchip: add new clock-type for the ddrclk
soc: rockchip: add header for ddr rate SIP interface
clk: rockchip: add SCLK_DDRC id for rk3399 ddrc
clk: rockchip: handle of_iomap failures in legacy clock driver
clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical
clk: rockchip: use general clock flag when registering pll
clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399
clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Currently the fractional divider clock time can't handle the
CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
there is no clk_divider_bestdiv() function to try speeding up the parent
to see if it helps things.
Eventually someone could try to figure out how to make fractional
dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
confuse the common clock framework (and anyone using it) by setting the
flag.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We would prefer the 2016M as 2.0G than 1992M which seems odd, adding
it to big cpu clk rate table then we can set 2016M in dts.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Changing the rate of the DDR clock needs special care, as the DDR
is of course in use and will react badly if the rate changes under it.
Over time different approaches to handle that were used.
Past SoCs like the rk3288 and before would store some code in SRAM
while the rk3368 used a SCPI variant and let a coprocessor handle that.
New rockchip platforms like the rk3399 have a dcf controller to do ddr
frequency scaling, and support for this controller will be implemented
in the arm-trusted-firmware.
This new clock-type should over time handle all these methods for
handling DDR rate changes, but right now it will concentrate on the
SIP interface used to talk to ARM trusted firmware.
The SIP interface counterpart was merged from pull-request #684 [0]
into the upstream arm-trusted-firmware codebase.
[0] https://github.com/ARM-software/arm-trusted-firmware/pull/684
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We don't have code to handle any of the noc clocks in rk3399 and they're
all just listed as critical clocks. Let's do the same for
aclk_emmc_noc.
Without this clock being marked as critical we have problems around
suspend/resume after commit 20c389e656 ("clk: rockchip: fix incorrect
aclk_emmc source gate bits on rk3399"). Before that change we were
presumably not actually gating any of these clocks because we were
setting the wrong gate.
Fixes: 20c389e656 ("clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Sorry to refer incorrect clock diagram, we double check it that the bits
configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin board.
1. the hclk_host0 and hclk_host1 are endpoint clocks:
cpll --> G5[1] --> aclk_perihp_cpll_src --\ |--> hclk_host0
| --> ... ---> |
gpll --> G5[0] --> aclk_perihp_gpll_src --/ |--> hclk_host1
2. there is no clock below the cpll_aclk_perihp_src,
and the hclk_hostX are below the gpll_aclk_perihp_src:
pll_cpll 1 1 800000000 0 0
cpll 7 19 800000000 0 0
cpll_aclk_perihp_src 0 0 800000000 0 0
...
pll_gpll 1 1 594000000 0 0
gpll 10 10 594000000 0 0
gpll_aclk_perihp_src 2 2 594000000 0 0
hclk_perihp 5 5 74250000 0 0
hclk_host1_arb 2 2 74250000 0 0
hclk_host1 2 2 74250000 0 0
hclk_host0_arb 2 2 74250000 0 0
hclk_host0 2 2 74250000 0 0
3. by default, G5[0] and G5[1] are enabled:
localhost ~ # mem r 0xff760314
0x000003e0
4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable,
the DUT still works well:
localhost ~ # mem w 0xff760314 0xffff03e2
localhost ~ # mem r 0xff760314
0x000003e2
plug/unplug, the work statue is ok
5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable,
the DUT will be crashed:
localhost ~ # mem w 0xff760314 0xffff03e1
localhost ~ # mem r 0xff760314
0x000003e1
plug/unplug, the DUT is crashed
Summary:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Fixes: 3bd14ae9da ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
[here the clock-documentation in the manual was actually stating the wrong
bits and thus only Xing's testing above revealed the issue]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The aclk_vio_noc should be put into critical list, as the interconnect
is not handled right now, but is required by VOP.
And the Type-C DP need these clocks: aclk_hdcp_noc, hclk_hdcp_noc,
pclk_hdcp_noc. Mark them as critical to avoid someone close them.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the general flags the pll list already contains to the clock init,
so that needed clock flags can be used for plls.
Signed-off-by: Heiko Stübner <heiko@sntech.de>
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.
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Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.
* tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
clk: rockchip: export rk3228 MAC clocks
clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
clk: rockchip: export rk3228 audio clocks
clk: rockchip: include rk3228 downstream muxes into fractional dividers
clk: rockchip: fix incorrect rk3228 clock registers
clk: rockchip: add clock-ids for rk3228 MAC clocks
clk: rockchip: add clock-ids for rk3228 audio clocks
clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.
Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch exports related MAC clocks for dts reference.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The sclk_macphy_50m is confusing, the sclk_mac_extclk describes
a external clock clearly.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch exports related i2s/spdif clocks for dts reference.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect,
we need to fix them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.
This was missing on the newly added rk3399 clock tree.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Like rk3288, the pclk supplying the watchdog is controlled via the
SGRF register area. Additionally the SGRF isn't even writable in
every boot mode.
But still the clock control is available and in the future someone
might want to use it. Therefore define a simple clock for the time
being so that the watchdog driver can read its rate.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
It maybe due to a copy-paste error the error handing should be
cclk not clk when checking if the cpuclk registration succeeded.
Reported-by: Lin Huang <lin.huang@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This reverts commit 7a03fe6f48 ("clk: rockchip: reset init state
before mmc card initialization").
Though not totally obvious from the commit message nor from the source
code, that commit appears to be trying to reset the "_drv" MMC clocks to
90 degrees (note that the "_sample" MMC clocks have a shift of 0 so are
not touched).
The major problem here is that it doesn't properly reset things. The
phase is a two bit field and the commit only touches one of the two
bits. Thus the commit had the following affect:
- phase 0 => phase 90
- phase 90 => phase 90
- phase 180 => phase 270
- phase 270 => phase 270
Things get even weirder if you happen to have a bootloader that was
actually using delay elements (should be no reason to, but you never
know), since those are additional bits that weren't touched by the
original patch.
This is unlikely to be what we actually want. Checking on rk3288-veyron
devices, I can see that the bootloader leaves these clocks as:
- emmc: phase 180
- sdmmc: phase 90
- sdio0: phase 90
Thus on rk3288-veyron devices the commit we're reverting had the effect
of changing the eMMC clock to phase 270. This probably explains the
scattered reports I've heard of eMMC devices not working on some veyron
devices when using the upstream kernel.
The original commit was presumably made because previously the kernel
didn't touch the "_drv" phase at all and relied on whatever value was
there when the kernel started. If someone was using a bootloader that
touched the "_drv" phase then, indeed, we should have code in the kernel
to fix that. ...and also, to get ideal timings, we should also have the
kernel change the phase depending on the speed mode. In fact, that's
the subject of a recent patch I posted at
<https://patchwork.kernel.org/patch/9075141/>.
Ideally, we should take both the patch posted to dw_mmc and this
revert. Since those will likely go through different trees, here I
describe behavior with the combos:
1. Just this revert: likely will fix rk3288-veyron eMMC on some devices
+ other cases; might break someone with a strange bootloader that
sets the phase to 0 or one that uses delay elements (pretty
unpredicable what would happen in that case).
2. Just dw_mmc patch: fixes everyone. Effectly the dw_mmc patch will
totally override the broken patch and fix everything.
3. Both patches: fixes everyone. Once dw_mmc is initting properly then
any defaults from the clock code doesn't mattery.
Fixes: 7a03fe6f48 ("clk: rockchip: reset init state before mmc card initialization")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
[emmc and sdmmc still work on all current boards in mainline after this
revert, so they should take precedence over any out-of-tree board that
will hopefully again get fixed with the better upcoming dw_mmc change.]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There was a typo, swapping 'c' <--> 'g'.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We never want to kill the GIC.
Noticed when making other clock fixups, and seeing the newly-constructed
clock tree try to disable cpll, where we had this parent structure:
aclk_gic <------\
|--- aclk_gic_pre <-- cpll <-- pll_cpll
aclk_gic_noc <--/
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The flags element of clk_init_data was never initialized for mmc-
phase-clocks resulting in the element containing a random value
and thus possibly enabling unwanted clock flags.
Fixes: 89bf26cbc1 ("clk: rockchip: Add support for the mmc clock phases using the framework")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Pull rockchip clk updates from Heiko Stuebner:
Another small rk3399 fixup as well as simplifications around
our handling of the General-Register-Files syscon.
* tag 'v4.7-rockchip-clk4' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: drop old_rate calculation on pll rate changes
clk: rockchip: simplify GRF handling in pll clocks
clk: rockchip: lookup General Register Files in rockchip_clk_init
clk: rockchip: fix the rk3399 sdmmc sample / drv name
Previously when everything happened in the set_rate callbacks itself we
needed the old_rate value for the possible rate rollback, so that made
it easy to also use it in the debug output.
Now with the param-handling being done in separate functions, reading and
recalculating the current pll rate only to use it in a debug message that
won't get displayed in regular cases anyway is quite a waste.
Therefore drop that value from the debug output. In the worst case that
previous rate will have been displayed on the rate change before.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the previous commit, the clock drivers now know at init time if the
GRF regmap is available. That means if it isn't available then, it also
won't become available later and we can therefore switch PLLs, that need
the GRF for the lock-status, to read-only mode - similar behaviour as the
aborting of rate changes we did before.
This saves some conditionals on every rate change and we can also drop
the rockchip_clk_get_grf function completely.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In the distant past syscons were initialized pretty late and weren't
available at the time the clock init ran. As the GRF is mainly needed
for PLL lock-status checking, we had this lazy init that tried to grab
the syscon on PLL rate changes and denied these changes if it was not
available.
These days syscons are available very early and recent addition to
rockchip clocks, like the PLL clk_init actually also rely on them
being available at that time, so there is no need to keep that lazy
init around, as it will also result in some more simplifications in
other parts of the clock-code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3399 clock table had a simple typo in it, calling the SDMMC sample
and drive clocks by the wrong name. Fix this minor typo.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Acked-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:
A spelling fix and a bunch of rk3399 clock fixes.
* tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix the rk3399 cifout clock
clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
clk: rockchip: add some frequencies on the rk3399 PLL table
clk: rockchip: assign more necessary rk3399 clock ids
clk: rockchip: export some necessary rk3399 clock ids
clk: rockchip: rename rga clock-id on rk3399
clk: rockchip: add general gpu soft-reset on rk3399
clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
The cifout clock is incorrect due to the manual error, we need to
fix it.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We don't need to many clocks enable after startup, to reduce some
power consumption.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch add some necessary frequencies for the RK3399 clock.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
fix spelling mistake, unsucessful -> unsuccessful
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rk3399 header and also in the clock code itself.
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Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull some checkpatch silencers from Heiko Stuebner:
Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.
* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix checkpatch warning in core code
clk: rockchip: drop unnecessary header comment
clk: rockchip: reign in some overly long lines in the rk3399 controller
clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
We seem to have accumulated a bunch of checkpatch warnings, with mainly
overlong lines and two unnecessary allocation error messages.
Most were introduced with the recent multi-controller-support but some
were quite a bit older.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The internal clk header did contain a comment indicating that some of the
defined registers were shared over multiple clock controller variants.
In recent times, it was simply extended all the time and stopped providing
any meaningful information, so drop it and it's overlong line.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.
Fix the newly added rk3399 clock code to respect that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Main change is probably the added support for the new rk3399 soc
and necessary infrastructure changes surrounding it.
The biggest chunk is probably that clock code is now able to
handle multiple clock providers in one system, as the rk3399
has two of those. A general one and another smaller one in a
separate power domain. The rk3399 also uses another new pll type.
Thankfully it just fits nicely into our current structure.
It also needs some parts like the cpuclk mux parameters to be
a bit more flexible and an new fractional divider subtype without
gate.
Apart from this big change we have some more fixes and removal
of forgotten variables.
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Merge tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:
This is first big chunk of Rockchip clock-related changes for 4.7.
Main change is probably the added support for the new rk3399 soc
and necessary infrastructure changes surrounding it.
The biggest chunk is probably that clock code is now able to
handle multiple clock providers in one system, as the rk3399
has two of those. A general one and another smaller one in a
separate power domain. The rk3399 also uses another new pll type.
Thankfully it just fits nicely into our current structure.
It also needs some parts like the cpuclk mux parameters to be
a bit more flexible and an new fractional divider subtype without
gate.
Apart from this big change we have some more fixes and removal
of forgotten variables.
* tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add clock controller for the RK3399
dt-bindings: add bindings for rk3399 clock controller
clk: rockchip: add dt-binding header for rk3399
clk: rockchip: release io resource when failing to init clk
clk: rockchip: remove redundant checking of device_node
clk: rockchip: fix warning reported by kernel-doc
clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data
clk: rockchip: add new pll-type for rk3399 and similar socs
clk: rockchip: Add support for multiple clock providers
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
The rockchip_softrst_ops structure is never modified. Make it const.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the clock tree definition for the new RK3399 SoC.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rockchip_clk_of_add_provider is used by sub-clk driver which
already call of_iomap before calling it. If device_node does
not exist, of_iomap returns NULL which will fail to init the
sub-clk driver. So really it's redundant.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null
drivers/clk/rockchip/clk.h:133: warning: missing initial short
description on line:
* struct rockchip_clk_provider: information about clock provider
drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:164: warning: missing initial short
description on line:
* struct rockchip_pll_clock: information about pll clock
drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'parent_names'
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'num_parents'
drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef
member 'parent_name' description in 'rockchip_pll_clock'
drivers/clk/rockchip/clk.h:235: warning: missing initial short
description on line:
* struct rockchip_cpuclk_reg_data: describes register offsets and
masks of the cpuclock
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
mux_core_reg isn't been used anywhere, let's remove it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3399's pll and clock are similar with rk3036's, it different
with base on the rk3066(rk3188, rk3288, rk3368 use it), there are
different adjust foctors and control registers, so these should be
independent and separate from the series of rk3066s.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.
Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.
Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Because there are some frac clock mux nodes don't have a gate node on
the RK3399.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
new device support in terms of LoC, but there has been some cleanup
in the core as well as the usual minor clk additions to various
drivers.
Core:
- parent tracking has been simplified
- CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started
- of_clk_init() doesn't consider disabled DT nodes anymore
- clk_unregister() had an error path bug squashed
- of_clk_get_parent_count() has been fixed to only return unsigned ints
- HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone
New Drivers:
- NXP LPC18xx creg
- QCOM IPQ4019 GCC
- TI dm814x ADPLL
- i.MX6QP
Updates:
- Cyngus audio clks found on Broadcom iProc devices
- Non-critical fixes for BCM2385 PLLs
- Samsung exynos5433 updates for clk id errors, HDMI support,
suspend/resume simplifications
- USB, CAN, LVDS, and FCP clks on shmobile devices
- sunxi got support for more clks on new SoCs and went through a minor
refactoring/rewrite to use a simpler factor clk construct
- rockchip added some more clk ids and added suport for fraction dividers
- QCOM GDSCs in msm8996
- A new devm helper to make adding custom actions simpler (acked by Greg)
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The clk changes for this release cycle are mostly dominated by new
device support in terms of LoC, but there has been some cleanup in the
core as well as the usual minor clk additions to various drivers.
Core:
- parent tracking has been simplified
- CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started
- of_clk_init() doesn't consider disabled DT nodes anymore
- clk_unregister() had an error path bug squashed
- of_clk_get_parent_count() has been fixed to only return unsigned ints
- HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone
New Drivers:
- NXP LPC18xx creg
- QCOM IPQ4019 GCC
- TI dm814x ADPLL
- i.MX6QP
Updates:
- Cyngus audio clks found on Broadcom iProc devices
- Non-critical fixes for BCM2385 PLLs
- Samsung exynos5433 updates for clk id errors, HDMI support,
suspend/resume simplifications
- USB, CAN, LVDS, and FCP clks on shmobile devices
- sunxi got support for more clks on new SoCs and went through a
minor refactoring/rewrite to use a simpler factor clk construct
- rockchip added some more clk ids and added suport for fraction
dividers
- QCOM GDSCs in msm8996
- A new devm helper to make adding custom actions simpler (acked by Greg)"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (197 commits)
clk: bcm2835: fix check of error code returned by devm_ioremap_resource()
clk: renesas: div6: use RENESAS for #define
clk: renesas: Rename header file renesas.h
clk: max77{686,802}: Remove CLK_IS_ROOT
clk: versatile: Remove CLK_IS_ROOT
clk: sunxi: Remove use of variable length array
clk: fixed-rate: Remove CLK_IS_ROOT
clk: qcom: Remove CLK_IS_ROOT
doc: dt: add documentation for lpc1850-creg-clk driver
clk: add lpc18xx creg clk driver
clk: lpc32xx: fix compilation warning
clk: xgene: Add missing parenthesis when clearing divider value
clk: mb86s7x: Remove CLK_IS_ROOT
clk: x86: Remove clkdev.h and clk.h includes
clk: x86: Remove CLK_IS_ROOT
clk: mvebu: Remove CLK_IS_ROOT
clk: renesas: move drivers to renesas directory
clk: si5{14,351,70}: Remove CLK_IS_ROOT
clk: scpi: Remove CLK_IS_ROOT
clk: s2mps11: Remove CLK_IS_ROOT
...
Here's our branch of ARM64 contents for this merge window, now
containing all ARM64 changes other than device tree files.
- Various new platforms get added
- Allwinner A64 SoC
- Annapurna Labs Alpine SoCs
- Broadcom Vulcan
- Marvell Armada 3700 SoCs
- Amlogic S905
- Various defconfig changes to enable platform specific drivers
This branch includes the clk git tree to resolve a build-time
dependency.
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Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC 64-bit changes from Arnd Bergmann:
"Here's our branch of ARM64 contents for this merge window, now
containing all ARM64 changes other than device tree files.
- Various new platforms get added:
* Allwinner A64 SoC
* Annapurna Labs Alpine SoCs
* Broadcom Vulcan
* Marvell Armada 3700 SoCs
* Amlogic S905
- Various defconfig changes to enable platform specific drivers
This branch includes the clk git tree to resolve a build-time
dependency"
* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
arm64: defconfig: Increase MMC_BLOCK_MINORS to 16
arm64: defconfig: Add Qualcomm sdhci and restart functionality
ARM64: Enable Amlogic Meson GXBaby platform
arm64: defconfig: Enable Samsung MFD and related configs
arm64: alpine: select the Alpine MSI controller driver
arm64: defconfig: enable the Alpine family
arm64: add Alpine SoC family
arm64: defconfig: Enable exynos thermal config
arm64: add defconfig options for Allwinner SoCs
arm64: defconfig: Enable DesignWare APB GPIO controller
arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
clk: samsung: Don't build ARMv8 clock drivers on ARMv7
MAINTAINERS: Add entry for Broadcom Vulcan SoC
arm64: cputype info for Broadcom Vulcan
arm64: Broadcom Vulcan support
arm64: defconfig: Add Broadcom Vulcan to defconfig
arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
Documentation: arm: add Marvell Armada 7K and 8K families
Documentation: arm: add link to Armada 38x Functional Spec
...
The emac needs constant and very specific rate but the possible PLL-sources
are very limited, so we expect the PLL source to be set manually on per
board and don't want it to get changed in an automatic way later.
So add the necessary clock-id and disable reparenting on set_rate calls.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Associate the new clock id the clock.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.
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Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull second batch of rockchip clk updates from Heiko Stuebner:
Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.
* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: include downstream muxes into fractional dividers on rk3368
clk: rockchip: set the clock ids for RK3228 HDMI
clk: rockchip: set the clock ids for RK3228 VOP
clk: rockchip: add the tsadc clocks found on rk3228 SoCs
clk: rockchip: add the new clock ids for RK3228 HDMI
clk: rockchip: add the new clock ids for RK3228 VOP
clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
clk: rockchip: fix coding style for clk-cpu.c
clk: rockchip: don't return NULL when registering mmc branch fails
clk: rockchip: don't return NULL when registering inverter fails
clk: rockchip: check grf when waiting pll lock
clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
Mark Yao