- use the mvebu-mbus driver
- prep for LPAE support
Depends:
- mvebu/cleanup (tags/cleanup_for_v3.10)
- mvebu/drivers (tags/drivers_for_v3.10)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJRbApqAAoJEAi3KVZQDZAeiUkH+gI3KNnIEmwbMANGy+zdX70Y
mVj5X51MkXCawqNPLT6KYTO16Ap8STBXDxLfQfll1BuIeATgQgqs8dCcykiYQ4me
45Hj9+6uZhfPpN43u4syFPoYaLSAMT9Oe/9ntcpdnyu4fEsRmGGh2Dg8bhYcG1B2
+IVB67qSJ3vU0D2bcqsbSPuSu9MW2Qloc5+SMR74TcsyseZw10kbvL6cdwi9DpNt
ru2c/bXqO88U1pmeedJ8Cxl0KGFDhocYWV6orqph+2jIxuCDYd7DjOXFKeMHwcDX
lj54wMUyp8EzTs+huhnK3qL6waXTyccmMDDvgIL6WiFywvklTOJOFz0BnfHIHpk=
=RK7u
-----END PGP SIGNATURE-----
Merge tag 'tags/soc_for_v3.10' into mvebu/dt
Pulling in mvebu branches which contain changes to armada*.dts? files for LPAE
conversion.
mvebu soc changes for v3.10
- use the mvebu-mbus driver
- prep for LPAE support
Depends:
- mvebu/cleanup (tags/cleanup_for_v3.10)
- mvebu/drivers (tags/drivers_for_v3.10)
- Kirkwood
- a couple of small fixes for the Iomega ix2-200 board (ether and led)
- mvebu
- allow GPIO button to work on Mirabox when running SMP
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJRZZxwAAoJEAi3KVZQDZAerwcIAKR1xRKuagtXvfij+xfVVRQ6
1G645hTIthFXmNiEeo3Y/mswHhVooZvu8SWh3o3J2Wsbnzeh+ch6jTsl+g6Tnb3E
KmRFU0mcalRmsyYsh4PH9nDi8/oWyP+i3ZytgfcMlsSPNiE+Ek35NdTTWMLCTT8V
MkGysVc8MWoOmMf47mNboy5UUUTXRdnSUJSjv1ubrsTK33LT7Ii9Ce+eoNvpvF+5
+6RenfRMzRSwkZf9AaCRPAhXISQKbMAwz6lKGo2GGAW+73Z+JclXXmiCfQ8pWie2
pfyqiEYigZFqe6Ly5BUtGoVfDjmOLDs+ATTUDOlOj0uaEc7pOwwKoAtpVRdck24=
=yK1f
-----END PGP SIGNATURE-----
Merge tag 'tags/mvebu_fixes_for_v3.9_round3' into mvebu/dt
pulling in mvebu branches which changes armada*.dts? files for LPAE changes
mvebu fixes for v3.9 round 3
- Kirkwood
- a couple of small fixes for the Iomega ix2-200 board (ether and led)
- mvebu
- allow GPIO button to work on Mirabox when running SMP
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so
we enable the corresponding PCIe interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell evaluation board (DB) for the Armada 370 SoC has 2
physical full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Globalscale Mirabox platform uses one PCIe interface for an
available mini-PCIe slot, and the other PCIe interface for an internal
USB 3.0 controller. We add the necessary Device Tree informations to
enable those two interfaces.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
be used to plug mini-PCIe devices. We therefore enable the PCIe
interface that corresponds to this slot.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
units (two 4x or quad 1x and two 4x/1x). We therefore add the
necessary Device Tree informations to make those PCIe interfaces
usable.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to be able to support the LPAE, the internal registers
virtual base must be aligned to 2MB. In LPAE section size is 2MB, in
earlyprintk we map the internal registers and it must be section
aligned.
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
When LPAE is activated on Armada XP, all registers and IOs are still
32bit, the 40bit extension is on the CPU to DRAM path (windows) only.
That means that all the DMA transfer are restricted to the low 32 bits
address space. This is limitation is achieved by selecting ZONE_DMA.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that all Marvell EBU platforms have been converted to use the
mvebu-mbus driver, we can remove the common plat-orion/addr-map.c code
that isn't compiled anymore.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit convers the mach-mv78xx0 sub-architecture to use the
mvebu-mbus driver. We simply have to call mvebu_mbus_init() in the
->init_early() function, and modify the PCIe code so that it uses the
new functions provided by mvebu-mbus to create the needed PCIe
windows.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit migrates the mach-orion5x platforms to use the mvebu-mbus
driver and therefore removes the Orion5x-specific addr-map code.
The dove_init_early() function now initializes the mvebu-mbus driver
by calling mvebu_mbus_init().
We also convert a number of orion5x_setup_xyz_win() calls to the
appropriate mvebu_mbus_add_window() calls, as each board was doing its
own setup for the NOR window or other devices. Ultimately, those
devices will be probed from the DT.
The common address decoding windows are now registered in the
orion5x_setup_wins() function. It is worth noting that the four PCIe
address decoding windows will ultimately no longer have to be
registered here: it will be done automatically by the PCIe driver once
Dove has been migrated to use the upcoming mvebu PCIe driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit migrates the mach-dove platforms to use the mvebu-mbus
driver and therefore removes the Dove-specific addr-map code.
The dove_init_early() function now initializes the mvebu-mbus driver
by calling mvebu_mbus_init().
The address decoding windows are now registered in the
dove_setup_cpu_wins() function. It is worth noting that the four PCIe
address decoding windows will ultimately no longer have to be
registered here: it will be done automatically by the PCIe driver once
Dove has been migrated to use the upcoming mvebu PCIe driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit migrates the mach-kirkwood platforms to use the mvebu-mbus
driver and therefore removes the Kirkwood-specific addr-map code.
The kirkwood_init_early() function is now responsible for initializing
the mvebu-mbus driver by calling mvebu_mbus_init().
The address decoding windows are now registered in the
kirkwood_setup_wins() function. It is worth noting that the four PCIe
address decoding windows will ultimately no longer have to be
registered here: it will be done automatically by the PCIe driver once
Kirkwood has been migrated to use the upcoming mvebu PCIe driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The changes needed to migrate the mach-mvebu (Armada 370 and Armada
XP) to the mvebu-mbus driver are fairly minimal, since not many
devices currently supported on those SoCs use address decoding
windows. The only one being the BootROM window, used to bring up
secondary CPUs.
However, this BootROM window needed for SMP brings an important
requirement: the mvebu-mbus driver must be initialized at the
->early_init() time, otherwise the BootROM window cannot be setup
early enough to be ready before the secondary CPUs are started.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that the clock driver supports the gatable oscillator as one single
clock, drop osc24M_fixed and move the relevant properties to osc24M
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add da850 EHRPWM & ECAP DT node along with pin-mux details.
Also adds OF_DEV_AUXDATA for EHRPWM & ECAP driver to use EHRPWM & ECAP
clock.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
If the device-tree blob is present during boot, then register the SDMA
controller with the device-tree DMA driver so that we can use device-tree
to look-up DMA client information.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
- Fix a timer problem that causes missed ticks and hangs.
- Fix a problem with the decompressor UART dropping characters.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQIcBAABAgAGBQJRaIk3AAoJEOa6n1xeVN+C50wP/3G+sbUV1r+64OwUMWoyu0t0
YeVebBN4QQzMq1/NkhWjwNeM5yzQsz5MZO2AiN88yEh6vQa7uXQz/RwR4GYzX8le
Mt5dSnbAEk5pNVSooLw9aNpaRPcxuW3m4XHxPUYjc4wChMzNTVc4YJcZrXxIlfNh
qzQaPNa8ZstOgeEoo3sC6P5XWHzpumhW6THMJldYHuHSCnb5hIwFzxO3g3q/59Mq
X0sBM103U6QG+rfK2FzFMPwRNJ8kqILmNaOOwNaFxt3MYXbNJvlHi864R4i9iqjk
QmPS8XB2OsFwb+Knash3jO8GYWjXD2ZLVbVP1rnBL2IretYZF3Vd/rRStvv9DNRj
DP0N29ASCvBT/C2yE+Pv7FkQsW5tbydyhqpDLRkDPNMo51fkynpfNAnhxVwyzELV
7w1doMZt5a38j0k025hPiFrmar/RjRP1PPlxRyzETqTIkwG4HeitZ/ECSPCCidj7
xTAFtGquK4B5A5tnbuVyAAODfzwLrWZBUfG9hiv2rrFV9rdLEX0qTMSEiR9pcD1g
3zIbakJckbpIf6quE8dhHBWSYrZv8DGCvQnn1Aw3VgJFU6cgZNqfLVv8zl6/V/c/
l7nh0PJx5xMD7Td2mOkCnczCWFDMNpDaHje+vEie0gpTPFoqcnBpMMCXI4wI8+w+
9Zu4chBfSrpxZCVf1Rsz
=hLJp
-----END PGP SIGNATURE-----
Merge tag 'msm-fix-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/fixes-non-critical
From David Brown:
Some minor fixes for MSM for 3.10
- Fix a timer problem that causes missed ticks and hangs.
- Fix a problem with the decompressor UART dropping characters.
* tag 'msm-fix-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm:
ARM: msm: Fix uncompess.h tx underrun check
ARM: msm: Stop counting before reprogramming clockevent
Signed-off-by: Olof Johansson <olof@lixom.net>
The msm_defconfig is quite out of date. This allows the targets we
are actively working on to be more easily build and run tested.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQIcBAABAgAGBQJRaIoXAAoJEOa6n1xeVN+C+YoP/Rry5Q6h1i+NFYM7rqIDLb1V
IRTcnD3EIdstvVdm/tBNYz6WSQsCb3d8oIKRcl2ThzD9ooXJCE1cjNGnsY3fmJQv
KEKu7Qjz4yo62XW6dl6DRycwZ3EubvP7OshPogbv3aGdNwFt7JrR6G+EH57wiuhY
Og2YTaVu8+7K53KmJBjYf169Tw0+PVgZvVT6uWtGIoVi6MAcs7LB4poudoxD0FQJ
NGOYvwVZ4tM8KuZUljMVA6Vb3m3PHmpAJET7TMLA20GiJcaUmpbUTZ/v8lOwM8Jj
eU29gU61Ba3qh5fVvrjt+xrlw4NgHWUJ6TiyREGaM0/fQFHdKER/XgmsK8+UfF1i
ZGusQW+J7pC8u/1WnxDudsD6k7Kt7el2YuAv2v46lfQRpRWo/YQ8XnzCQ+UG0wTQ
rQmSUmvJJklsk1qn/Cu8XrMoWozLTxwhnxygfZ4hQ35R2T+ETUaeiSqioeuYBRyM
OFePQ36FI0el1RuT1IWBwWnil5J58mtotLbL4bTne/EmRQiXr2mLtozhYjC8X6NU
9FTGCI1ScHhJ0Hv1l754EJyJXb4P1whumBs1OpWpNsDmNX61qiZ0/BNDczcskKq1
UUNT/QdVxbdquVuaoBtoRmOkVCaX7i00+CMv9bM/j4lqmQIWNqG8ENGuq6alDBGo
82orUqpwmQ/3ZaG7B13Q
=Gh/Z
-----END PGP SIGNATURE-----
Merge tag 'msm-defconfig-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/boards
From David Brown:
Defconfig updates for MSM
The msm_defconfig is quite out of date. This allows the targets we
are actively working on to be more easily build and run tested.
* tag 'msm-defconfig-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm:
ARM: msm: enable SSBI driver in defconfig
ARM: msm: Concentrate defconfig on DT supported devices
These patches are changes to the MSM timer code that will be for
upcoming targets, including a generalization of the binding and
preventing a missing timer interrupt.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQIcBAABAgAGBQJRaInuAAoJEOa6n1xeVN+CP5oP/3HMkT/Ihqcm85H9SXSG9M9d
1LY2Nu6wWoSZk5qbBc8zAEFaoP3WDOJ/zgonXRFxOa59x5ZopEyw2xzQ5HO7+vHe
umH9uGA644rrTysSsx1Zox1H6AskxKTzPXTrDeTXH1W4s3Rmsqzg+08Ie72WTKJn
UROFI/zv1HS6G8Eq33fpbsq4juZtbqTJLiIDICDB3x1pEXh96MZTgC6LXuU6RTHh
ORN7QNf8LjaNU1lZdRdYXsdO8CIb51Ur2OKNG8G+L711Khr4fdwIEEFQUH4CS9Mq
RXPY47h+rwc4q7KHzEpF3rRITDDJnq5nbazEpSMFKq8ACr6fH6u5zUr0nknIWAL+
cYZMu6axuYLCMe4QCEf2xuASdggsHiXnq8MWJCsrx4h4VWKq9TcsfZkytdZu5epi
M9RY2c1VfcCFEIsBhb/s00ZRZkZaQq8S9wvbt431bSHBlvsGp9Ofqxj2siYcmMC+
ozE6ClI4IQMB+iBdk3MNV0sK8Boj0ywo/2KgnfCGJ+f+LcuAhQMScvOY4JPjMxpZ
8RcfZzg49mbN7hV4+IHJWW9Nfo6mPlw4k3vavx6kcChYQeQiGANO0kg+2ldagDIE
blxh0PxXSgpkB91Epova/tGPXncGPgG2k9eOrZ3pmZtmBL4215Axlx2zjc8elFeG
/pEkYdZqddjwVm8ryHWQ
=SbqQ
-----END PGP SIGNATURE-----
Merge tag 'msm-core-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/soc
From David Brown:
Patches for MSM core
These patches are changes to the MSM timer code that will be for
upcoming targets, including a generalization of the binding and
preventing a missing timer interrupt.
* tag 'msm-core-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm:
ARM: msm: Wait for timer clear to complete
ARM: msm: Rework timer binding to be more general
Signed-off-by: Olof Johansson <olof@lixom.net>
These are some patches for various parts of MSM that gradually bring
us closer to being part of single zimage.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQIcBAABAgAGBQJRaImzAAoJEOa6n1xeVN+CBYQQALoydAc36RZ0WK5Ksz77bv0r
jv8jSu6XyorjI+OJAeGOCUuotpa8nLnhBmwOtgM2Sd83hA/voIUt1olc1skO/Ahb
MSwHCWrHicGrq8RPrWmhRRlAGG4394p3wfro58QAlxh/Wgi8AHzXfR+ahlBCU23F
Dj2BFh+INx8h/A6H1BzZWUwvjVWThLAqcPfsAovyEH7//DLJP4Mbd3KhUeqtFrWO
nrh05ymss5PgElxdZQP8eowVsTEXcsQGn0IoXmGtxhBSvAKxw6pnrL3/e29f1poM
A9/Ci+qgMXW6TjjBdxID/MWzeL1v/Om1xJ7DI6be1D5PqodZpCWkh5mKJwaI0Q2j
U6aobtRiV/wEUq7iWFMVzCywQIGua7/wfh6PshTMtOjHNXOn9mAh1bCrv9wKUt+D
VkkCzx6dnpjQv3hDQ4wdz2R8hsXj/8NEV48g+NwFWaDpKJgVQA92sWpIjNdaDsk+
OzWC5gkMpCE7/SmEaClcyybjuA4N+W7Tan4zQot0mlXZzuuSAIhXIfRnR+OiExnY
jsQSfxyWGUm9yR4kJdJjcyYM+IvKEq4Tm7oyPH551qs7Ww8TxUgcJhPdevN0eFBM
cvljVzU54zZo9S08No14lp7LvRbM+o3/wphz9/NZijgpFGw24W1kj85Pa2ywQhzs
zn5Qqg5adOGS/R/v+PaD
=rBJL
-----END PGP SIGNATURE-----
Merge tag 'msm-cleanup-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/cleanup
From David Brown:
Cleanups for MSM for 3.10
These are some patches for various parts of MSM that gradually bring
us closer to being part of single zimage.
* tag 'msm-cleanup-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm:
ARM: msm: Remove unused cpu.h header file
gpio: Make gpio-msm-v1 into a platform driver
mmc: msm_sdcc: Remove unnecessary include
ARM: msm: Move dma.h #defines that are private to dma.c
Signed-off-by: Olof Johansson <olof@lixom.net>
With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Enable a cold or warm reset to the HW from userspace.
Also fix a few sparse errors:
warning: symbol 'sys_manager_base_addr' was not declared. Should it be static?
warning: symbol 'rst_manager_base_addr' was not declared. Should it be static?
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch replaces V4L2_STD_525_60/625_50 with V4L2_STD_NTSC/PAL
respectively as this are the proper video standards.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Reported-by: Hans Verkuil <hans.verkuil@cisco.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
add support for V4L2 video display to DM355 EVM.
Support for SD modes is provided, along with Composite
output
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Create platform devices for various video modules like venc,osd,
vpbe and v4l2 driver for dm355.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
add support for V4L2 video display to DM365 EVM.
Support for SD and ED modes is provided, along with Composite
and Component outputs.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Create platform devices for various video modules like venc,osd,
vpbe and v4l2 driver for dm365.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
By default the VPSS clocks were enabled in capture driver
for davinci family which creates duplicates for dm355/dm365/dm644x.
This patch adds support to enable the VPSS clocks in VPSS driver,
which avoids duplication of code and also adding clock aliases.
This patch uses PM runtime API to enable/disable clock, instead
of DaVinci clock framework. con_ids for master and slave clocks of
vpss is added in pm_domain.
This patch cleanups the VPSS clock enabling in the capture driver,
and also removes the clock alias in machine file. Along side adds
a vpss slave clock for DM365 as mentioned by Sekhar
(https://patchwork.kernel.org/patch/1221261/).
The Suspend/Resume in dm644x_ccdc.c which enabled/disabled the VPSS clock
is now implemented as part of the VPSS driver.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* Enable anatop, well bisa and RBC for suspend to optimize the power
consumption a little bit
* Clock changes for TVE, LDB, PATA, SRTC support
* Add System Reset Controller (SRC) support for imx5 and imx6
* Add initial imx6dl support based on imx6q code
* Kconfig for cpufreq-cpu0, defconfig updates and few other changes
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRZ/viAAoJEFBXWFqHsHzOyqUH/2t7CCwlfTVUJYDCeo6PaE9x
41cV5zG6RvX1OfkRUmJ2N2klGn4zhwg6GHsCDQmvs+IODs4E7JeB9M92FAaPng71
NnuuwCQ01iIoaTtkz8z/n3tSet3fYB+xfNCMJoWIyS0edFFkCjOgnqRsA0pHRIOp
G6ey1kU80D0f4+DjAUg1mkIvJrZxbRKDwmwqfDGJzQ4VU7cv70n027YuMKbeMyCC
zdeKmpKSEl9AY+O/zeMrf03zEW+kdZ4eB6cTUFlpzYwPYY9o+XHx0U0535F7/x4+
KObUZ9Qg7liP5WO3ZzkVff5HJqPs6s/q99eOsU4/okF1x0fpq2mSgIHlSw4HpK8=
=TuTx
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc2
From Shawn Guo:
The imx soc changes for 3.10:
* Enable anatop, well bisa and RBC for suspend to optimize the power
consumption a little bit
* Clock changes for TVE, LDB, PATA, SRTC support
* Add System Reset Controller (SRC) support for imx5 and imx6
* Add initial imx6dl support based on imx6q code
* Kconfig for cpufreq-cpu0, defconfig updates and few other changes
* tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (275 commits)
ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock
ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
ARM i.MX53: make tve_ext_sel propagate rate change to PLL
ARM i.MX53: Remove unused tve_gate clkdev entry
ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
ARM: i.MX5: Add PATA and SRTC clocks
ARM: imx: do not bring up unavailable cores
ARM: imx: add initial imx6dl support
ARM: imx1: mm: add call to mxc_device_init
ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS
ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
ARM: i.MX53 Add the cko1, cko2 clock outputs.
staging: drm/imx: Use SRC to reset IPU
ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)
ARM: imx: do not use regmap_read for ANADIG_DIGPROG
ARM i.MX6q: set the LDB serial clock parent to the video PLL
ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
ARM i.MX6q: fix ldb di divider and selector clocks
ARM i.MX53: fix ldb di divider and selector clocks
ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Trivial change/change conflict in arch/arm/mach-imx/mach-imx6q.c resolved.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYvOSAAoJEA0Cl+kVi2xqSxAQAKYKxx8PRNweKw3IeqIRQ+gs
Ia+0ZkHqPgoD/ezASGUmaTDGvAGVlNFqFTpzYiCLqFII5O4NzjFO9BfwE80PxaDe
I/tcofrU6aWNfYtT/0YsrvcdqVsSNxJwPBxfpEHyCK+4xoXsV6xJV0IpvE/u9bNT
2hLMfGndPkeTTqk7H3MpdJVB5DZOnE6LEwFVz1hVpBcCoQPJnpltIAGs/m4Rri7p
hlgdHxKAqo+VUcmmcP3HanylFvWwbJdtemdgPXTalzOFTZJ16RFJ3+ylRf7PbWjK
zVmjg7tFCmuAnh6HQTdm4hsnIohkL/GJfJClvNS52xL8ovfVWvjSF/x8LLZi5+4G
HBRZh2A1jIOGWxfSbpkPD64/rAp1aYZBeBVEQwAkeJdPCqlgvx8YS7vxZZT8i/1g
vck+d4zKzUCldGADu1YAHGBhRFAbmv1sJR4fzvkYrKGyzd+5jbyFx4fdZFpj6XEO
95P5CJgN6UIywBHrTG0CLP/828sdM7V8rmAnkvmAFXFv/MUJfPR5H81OUMWL5KAY
3a+ZJLPcwizb/cBMl7Qqq/YIXoV+o1byd49+/1rJvcD9KLlGwLawnbE/ZZp6PlQz
td2TNONzj3bqEXBDNx+PwpqcjSvO7KQFp+iFijZI7yRR6t+kfoqad5Vv+J0H7ATP
MxNZ7mSIKLa/rTDWK8LV
=YqMV
-----END PGP SIGNATURE-----
Merge tag 'dt-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt2
update device tree for exynos4 and exynos5
* tag 'dt-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (125 commits)
ARM: dts: add PDMA0 changes for exynos5440
ARM: dts: Add cpufreq controller node for Exynos5440 SoC
ARM: dts: Fix gmac clock ids due to changes in Exynos5440
ARM: dts: add device tree file for SD5v1 board
ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440
ARM: dts: add PMU support in exynos5440
ARM: dts: Add node for GMAC for exynos5440
ARM: dts: list the interrupts generated by pin-controller on Exynos5440
ARM: dts: Add FIMD DT binding Documentation
ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts
ARM: dts: Add FIMD node to exynos4
ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series
ARM: dts: Add display timing node to exynos5250-smdk5250.dts
ARM: dts: Add FIMD node to exynos5
ARM: dts: Add virtual GIC DT bindings for exynos5440
ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings
ARM: dts: add usb 2.0 clock references to exynos5250 device tree
ARM: dts: Add architected timer nodes for exynos5250
ARM: dts: Declare the gic as a15 compatible for exynos5250
ARM: dts: Add HDMI HPD and regulator node for Arndale board
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch moves the arch-vt8500 irq code to drivers/irqchip and converts
it to use the new IRQCHIP_DECLARE and irqchip_init. This allows the removal
of some more functions from common.h
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds the required node for the SDHC controller on WM8505 SoCs.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Olof Johansson <olof@lixom.net>
The spi-s3c64xx uses a Samsung proprietary interface for
talking to the DMA engine, which does not work with
multiplatform kernels.
This version of the patch leaves the old code in place,
behind an #ifdef. This can be removed in the future,
after the s3c64xx platform start supporting the regular
dmaengine interface. An earlier version of this patch was
tested successfully on exynos5250 by Padma Venkat.
The conversion was rather mechanical, since the samsung
interface is just a shallow wrapper around the dmaengine
interface.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Use imx_clk_mux_flags to set the appropriate flags for the TVE
selector clock. This is needed so tve_clk rate changes can propagate
up to pll4_sw.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Remove the tve_di clock from the CCM clock tree. It will be provided
by the Television Encoder driver, as this clock is an output signal
of the TVE module.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This is needed so the Television Encoder driver can set the rate
on tve_clk and have it propagated up to pll4_sw.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds the clock gates and the binding documentation
for PATA and SRTC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 Quad can be fused as i.MX6 Dual chip, and similarly i.MX6
DualLite can be fused as i.MX6 Solo. The actual number of available
cores can be found out from SCU.
Since we do not reflect the fusing thing in device tree, the function
arm_dt_init_cpu_maps() will always call set_cpu_possible(true) for 4
cores on i.MX6 Quad/Dual and 2 cores for i.MX6 DualLite/Solo. This
causes failures when kernel tries to bring those unavailable cores
online. For example, the following failure message will be seen when
booting an i.MX6 Solo chip.
CPU1: failed to come online
Though kernel will still boot fine, the message is somehow annoying.
Let's get rid of it by calling set_cpu_possible(false) on those
unavailable cores.
While at it, the set_cpu_possible(true) for available cores is removed,
since it's already been done in arm_dt_init_cpu_maps().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly
compatible with i.MX6 Quad/Dual. And that's why we choose to support
it using imx6q code with cpu_is_imx6dl() check when necessary.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
mxc_device_init() is mandatory for mxc_aips and mxc_ahb bus registration, needed
as parents, at least, for gpio and dma.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add CONFIG_GPIO_SYSFS as it is helpful for accessing GPIO from userspace.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
These two clocks connect to external pins and can be muxed to
various internal clocks.
They are typically used either for debugging or to provide
clocks to external chips (eg audio codecs).
Currently only the selectable clocks that already exist in the clock tree
have been added.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is
called to identify silicon version. Users might query silicon version
earlier than regmap subsystem is ready. For example, imx6q clock driver
query revision in mx6q_clocks_init(), where regmap is not initialized
yet.
Change imx_anatop_get_digprog() to map anatop block and read
ANADIG_DIGPROG in the native way, so that the function can work at very
early stage.
While at it, let's move imx_print_silicon_rev() back to
imx6q_timer_init() to have the message show up a little earlier.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There are some config options not selected by imx27 and imx5 that are
necessary to use the cpufreq-cpu0 driver.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds the missing GPU2D and GPU3D mux and gate clocks,
and the graphics arbiter gate clock.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Fix the following sparse warnings:
arch/arm/mach-imx/anatop.c:56:6: warning: symbol 'imx_anatop_pre_suspend' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:62:6: warning: symbol 'imx_anatop_post_resume' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:68:6: warning: symbol 'imx_anatop_usb_chrg_detect_disable' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:78:5: warning: symbol 'imx_anatop_get_digprog' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:86:13: warning: symbol 'imx_anatop_init' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:
1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;
As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.
For RBC settings, there are some rules as below
due to hardware design:
1. All interrupts must be masked during operating
RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
RBC setting is changed.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Anatop module have sereval configurations for user
to reduce the power consumption in suspend, provide
suspend/resume interface for further use and enable
fet_odrive to reduce CORE LDO leakage during suspend.
As we have a common anatop file, remove all the operations
of anatop module in other files, use anatop interfaces to
do that.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRZBpzAAoJEFBXWFqHsHzOfyAH/RdvhORI0rNhBAOrSxleWlMy
AMP9x6G5tXNK/fgtxopvCiS4VXw5MB01uqJWMVM9+hx6676oCXWc/L3I6iT5l87B
qPY/e9LyGJa5aOYczPuUT2sG+Ga8989GhOksA+L6kWHZ2df0BIB9rBRZnoPezEAx
u2ATdioyzfj2rAnDNFOxsw6oai265mowt/f8J/7EQfxgkAMcKov7/BpVac0po55R
tv+Hr3T7OBg3p/h5PYi5iAehVCToCKOD31QpnlhS+dmKS52w7tEO6T75INt7HzC8
CJT0zi5jJ3/tDJsdYJ1SS4MHK4U43y0oV7cw7sO7TzNreyOB6bzTWDqhdJY2oMM=
=N7xl
-----END PGP SIGNATURE-----
Merge tag 'imx-cleanup-3.10' into imx/soc
The imx cleanup for 3.10:
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
The definitions have moved to include/linux/usb/samsung-usb-phy.h,
and plat/usb-phy.h is unavailable from drivers in a multiplatform
configuration.
Also fix up the plat/usb-phy.h header file to use the definitions
from the new header instead of providing a separate copy.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The registers for the Samsung S3C serial port are currently defined in
the platform specific arch/arm/plat-samsung/include/plat/regs-serial.h
file, which is not visible to multiplatform capable drivers.
Unfortunately, it is not possible to move the file into a more local
place as we should normally try to, because the same registers
may be used in one of four places:
* In the driver itself
* In platform-independent ARM code for early debug output
* In platform_data definitions
* In the Samsung platform power management code
I have also found no way to logically split out a platform_data
file, other than possibly move everything into
include/linux/platform_data, which also felt wrong. The only
part of this file that makes sense to keep specific to the s3c24xx
platform are the virtual and physical addresses defined here,
which are needed in no other location.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Move the integrator-cp timer init to timer-sp.c and use CLKSRC_OF. There is
no reason to use the aliases, so drop them from the init code.
The integrator-cp timers are mistakenly called sp804 timers in the dts, but
in fact they are not sp804 dual timers, but single timers with the same
programming model. Fix the dts to reflect this.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The timer-sp initialization code clears the control register before
initializing the timers, so every platform doing this is redundant.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The motherboard sp804 timer is used, but core tile sp804 timer is not.
According to Russell King, the clock configuration is undocumented and
defaults to 32kHz which is not desireable. So mark core tile sp804 timer
as disabled.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Remove the vexpress specific setup for the sp804 timer now that
clocksource_of_init will do it.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
This adds CLKSRC_OF based init for sp804 timer. The clock initialization is
refactored to support retrieving the clock(s) from the DT.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
This converts arm and arm64 to use CLKSRC_OF DT based initialization for
the arch timer. A new function arch_timer_arch_init is added to allow for
arch specific setup.
This has a side effect of enabling sched_clock on omap5 and exynos5. There
should not be any reason not to use the arch timers for sched_clock.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Originally from a default machine descriptor patch from Arnd, pull out
just the default call to clocksource_of_init part. This is needed so that
platforms can simply remove .init_time calls as they are converted to use
clocksource_of_init.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Only 32-bits of the arch timer were being used and wrapping was needlessly
being done in s/w. By using the full counter (56-64 bits), we don't need
to deal with wrapping and can simplify the implementation when using
arch timer.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Use r8a7790 timer setup code to force the
arch timer to be enabled regardless of the bootloader setting
- This is necessary for the lager board to boot
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-boards3-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-r8a7790-for-v3.10
The merge was made to provide the r8a7790 timer setup code
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRZm1XAAoJENfPZGlqN0++ef0QAIFBOCTdU7IhHWQ1IPmq50bo
V+OEnlZ/FBD8s9ZmFEzS32HFbYvnsXa/fW7FNqx+Cocj2eRDx+els/kKU5oq9ZRn
jUnFU2fWF/WoLwQmkD+88yYAt6muVL+RxP1k4nfT2Zi8yaj0IrHWHUDF7YZDLygy
6QiVVxaDfArQNlxytK7VqJWQM+iaMJr+eT5i7u351pNQofaBHWRujFgohTv4of51
lcy+ign3iDASsoxo09biw8uqCAsNd0WklqljrBL0E0ag88MFfBUTuKSTMZPSUtM1
ZeTPBAz9faQdtvBWylcHuQ9+PStLl35J6nUfv0r/N7ehoslaCUDamFsTrJhNfB1S
sjhoPXHTWHuM+dAfl+xoT1jTsgJIfilzX0QJy3/6YShUXULquznlBRA6RiXzxtJD
SsPqJ+C0EeDoci5WOTnDbKGbLObnaP1hsHRyUb3rZM7M2VNuIkuM0G/KGae5zg8w
l9806XCM6Ak7qIBBIoq3vVk8+FJSfCV376uZVNwoO6kCidFi9PDo6DTJq+zhs5/3
H4FY4bhLF7WzKNHyfwbyiHbnkacu14mFxYrq3mo5wOhB42dtUnoQvNVo807tM79t
sOc8L2m4Y3gMJ1H10FsvmGiyhuUVOrVYq2trvDc6mDD85srVdzPOyT/DnrKvvzjN
qM8mQphgaA2FfnLGYqwB
=7y6e
-----END PGP SIGNATURE-----
Merge tag 'renesas-boards-lager-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2
From Simon Horman:
Renesas ARM based SoC lager board updates for v3.10
* Use r8a7790 timer setup code to force the
arch timer to be enabled regardless of the bootloader setting
- This is necessary for the lager board to boot
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-boards3-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-r8a7790-for-v3.10
The merge was made to provide the r8a7790 timer setup code
* tag 'renesas-boards-lager-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: use r8a7790 timer setup code on Lager
ARM: shmobile: force enable of r8a7790 arch timer
ARM: shmobile: Add second I/O range for r8a7790 PFC
Signed-off-by: Olof Johansson <olof@lixom.net>
* Force architecture timer to be activated regardless of bootloader
- This is necessary for the lager board to boot
* Add second memory range to r8a7790 PFC device
- This is in preparation for further PFC work.
It should not break anything as it is not used yet.
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRZmnuAAoJENfPZGlqN0++6AAP/3edyVpqono4N8ACAKt5EMUN
EOkJdTtsvdmI+1O3kSWNIp3WSaObYzzqGYpmKMZqIjlCzWVgNpazYvTGGPgBCy/B
J3VGmLerTdy6GMX8lr0Xk3/wU6nKVU9j1znwTDXzcaU9Mpo7naHmirrULL2uAiVX
ZJVNIN0P4cz8yWN4MtTz7slWFoR1aHr1GHEE7/PqFiMFWNeCjSI6z7HQYZggSlz5
p4EH0ZwmVs9jBNoP/TniOobUXqYVtTkO4TsAWnhKWnz2VJGSfs1wY7dYq95tX4pZ
ffuaFfrTRE9dY/dJvnbWpyD8iF7VU4XuvqJBdy7U6JWB9HBBRY6mSNFn5MGMLGI1
sf7ndPZDHLkRV67Sg8/znkssBqR/UW1b90b5yK9jSYdfVmm7lX+GupNjLd1eI5Y7
j+RmA5F3s+nwew0Z5Q0PxWTY2RuuykkawHSrryCvxOXTZ3pVzVxrgFACzanISPeZ
gxU7m7ahrDve0UECX1HH2QErdZwPSY02ZZF9fZoOEnOivNI44e/Vhgh2KKgj/C4e
oDASEUVJwi2KiQAnvt7hO8FG7K4CnPMAjDQaABGML9zUiYd7P/qWoyyos0b9XbKR
LN9iqKjRvNxIuraUpkH5qnotfcPmorNdMOz6D6Qlm2hSwk8XTChCMb3E3gCRO5CZ
WiEq+JcSc2r9LxL/hdpj
=qNDI
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-r8a7790-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
From Simon Horman:
Renesas ARM based r8a7790 SoC update for v3.10
* Force architecture timer to be activated regardless of bootloader
- This is necessary for the lager board to boot
* Add second memory range to r8a7790 PFC device
- This is in preparation for further PFC work.
It should not break anything as it is not used yet.
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc2-for-v3.10
* tag 'renesas-soc-r8a7790-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: force enable of r8a7790 arch timer
ARM: shmobile: Add second I/O range for r8a7790 PFC
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch selects the devbus driver as part of the mvebu default
config, along with the required options to detect and support
CFI flash memories.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Plat'home Openblocks AX3 has a 128 MiB NOR flash device connected
to the Device Bus. This commit adds the device tree node to support this device.
The SoC supports a flexible and dynamic decoding window allocation scheme;
but since this feature is still not implemented we need to specify the window
base address in the device tree node itself.
This base address has been selected in a completely arbitrary fashion.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada XP Development Board DB-MV784MP-GP has a NOR flash device
connected to the Device Bus. This commit adds the device tree node
to support this device.
This SoC supports a flexible and dynamic decoding window allocation
scheme; but since this feature is still not implemented we need
to specify the window base address in the device tree node itself.
This base address has been selected in a completely arbitrary fashion.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Armada 370 and Armada XP SoC have a Device Bus controller to
handle NOR, NAND, SRAM and FPGA devices.
This patch adds the device tree node to enable the controller.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The plat/regs-iis.h and plat/regs-ac97.h files in the samsung platform
are only needed by the ASoC drivers, so they can be moved into the same
directory, as one more step towards a multiplatform build.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
With multiplatform kernels, we cannot use hardwired IRQ
numbers in device drivers. This changes the idma driver
to use a proper resource, like all other drivers do.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Bit 3 of the SR register is set if there is a tx underrun. If
this bit isn't set, we should loop on the tx ready bit until we
can transmit again. Otherwise we should skip the loop and
transmit immediately. The code is doing the opposite though,
checking for an underrun and then looping on the tx ready bit
causing us to never loop on the tx read bit when the tx buffer
may not be ready.
This doesn't seem to affect my 8960 device too often, but in some
cases I see a lost character or two from the decompressor prints.
This also matches what we do in the assembly in debug-macro.S.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
- Kirkwood
- a couple of small fixes for the Iomega ix2-200 board (ether and led)
- mvebu
- allow GPIO button to work on Mirabox when running SMP
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJRZZxwAAoJEAi3KVZQDZAerwcIAKR1xRKuagtXvfij+xfVVRQ6
1G645hTIthFXmNiEeo3Y/mswHhVooZvu8SWh3o3J2Wsbnzeh+ch6jTsl+g6Tnb3E
KmRFU0mcalRmsyYsh4PH9nDi8/oWyP+i3ZytgfcMlsSPNiE+Ek35NdTTWMLCTT8V
MkGysVc8MWoOmMf47mNboy5UUUTXRdnSUJSjv1ubrsTK33LT7Ii9Ce+eoNvpvF+5
+6RenfRMzRSwkZf9AaCRPAhXISQKbMAwz6lKGo2GGAW+73Z+JclXXmiCfQ8pWie2
pfyqiEYigZFqe6Ly5BUtGoVfDjmOLDs+ATTUDOlOj0uaEc7pOwwKoAtpVRdck24=
=yK1f
-----END PGP SIGNATURE-----
Merge tag 'mvebu_fixes_for_v3.9_round3' of git://git.infradead.org/users/jcooper/linux into fixes
From Jason Cooper <jason@lakedaemon.net>:
mvebu fixes for v3.9 round 3
- Kirkwood
- a couple of small fixes for the Iomega ix2-200 board (ether and led)
- mvebu
- allow GPIO button to work on Mirabox when running SMP
* tag 'mvebu_fixes_for_v3.9_round3' of git://git.infradead.org/users/jcooper/linux:
arm: mvebu: Fix the irq map function in SMP mode
Fix GE0/GE1 init on ix2-200 as GE0 has no PHY
ARM: Kirkwood: Fix typo in the definition of ix2-200 rebuild LED
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The s3c-fb driver requires header files from the samsung platforms
to find its platform_data definition, but this no longer works on
multiplatform kernels, so let's move the data into a new header
file under include/linux/platform_data.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-fbdev@vger.kernel.org
Acked-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Note that the branch has dependencies to two other branches:
- omap-devel-b-for-3.10 from Paul to get the AM33xx missing
hwmod and thus avoid a regression with Santosh's hwmod
cleanup including in this DT series [1]. It avoids breaking
bisect if this series is merged before Paul's fixes.
- omap-for-v3.10/usb branch to avoid nasty merge conflict in
omap3.dtsi and omap4.dtsi due to the DTS patches contained
in the USB branch because of a screw up by the unnamed person
typing this signed tag based on Benoit's comments.
[1] https://patchwork.kernel.org/patch/2366291/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRY41OAAoJEBvUPslcq6Vz584QANm+lTNlS2+RYkRD/nUDtdS4
B4NZmeai/KBA/x4tApuI0wFmMPU57EU64K1SYSv/rP49Ohuxqf84POTLLFyhTxFC
0mBrffcRHFH480imZRpoJ+QwSvkreneyHs79ZbnB7OOd6tJC6njeex+Hp8uzCDXM
n0E6eOqOzGuNTT42BnyC1b9oM26/Tb7KMvkJbwuPEoyLIDR11h0r8+Dn5/fHpuYc
bVyTfRJfLCLfoLqheoW+BIuKtWT1ZjSzO1WNzRbrc6Ri78HTsOFxSKt2uA3lC1cx
tT5uaWKzYyo6ZV6uPTil6EIpYhDukpvncbwHw1n8g2gOQcPDngXw+zbNFDw7Vpq3
D4FbK4Lp/51scIQlmqAX31Wd/CvSlLLCCQzQ0JW6AznCx5OHOvfBDF9xMQZIlGGy
LoabMyILad7xYacVEvp1xyEMy3hX64laLf7Eu3GahiKrwvBMTKnbOqBODZZYKWwp
uqlSdUlkXTQ2aA7GQK0Dda+8xGcf603TLD5u20ZUEhXbdwmu91Ov++k1pOcoTFHx
qNLSu5SfUJW2VsEupw0DLsohnDQqGlkDYCo+m4AKwG1n4siASD12Y1z/DDaeNt09
WZZ5s4qi7vWcAMMnUcGQJdun2MVDGErCiTlg1VfmOtXmys/6f79g1W+Bj/4sMNqq
pbNDU9x/VzIvytxinzF5
=X5rc
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/dt-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt2
From Tony Lindgren:
Device tree updates for omaps via Benoit Cousson <b-cousson@ti.com>.
Note that the branch has dependencies to two other branches:
- omap-devel-b-for-3.10 from Paul to get the AM33xx missing
hwmod and thus avoid a regression with Santosh's hwmod
cleanup including in this DT series [1]. It avoids breaking
bisect if this series is merged before Paul's fixes.
- omap-for-v3.10/usb branch to avoid nasty merge conflict in
omap3.dtsi and omap4.dtsi due to the DTS patches contained
in the USB branch because of a screw up by the unnamed person
typing this signed tag based on Benoit's comments.
[1] https://patchwork.kernel.org/patch/2366291/
* tag 'omap-for-v3.10/dt-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (69 commits)
ARM/dts: OMAP3: fix pinctrl-single configuration
ARM: dts: Add OMAP3430 SDP NOR flash memory binding
ARM: dts: Add NOR flash bindings for OMAP2420 H4
ARM: dts: Update OMAP3430 SDP NAND and ONENAND properties
ARM: dts: OMAP2+: Identify GPIO banks that are always powered
ARM: OMAP2+: Populate DMTIMER errata when using device-tree
ARM: dts: OMAP2+: Update DMTIMER compatibility property
ARM: OMAP: Add function to request timer by node
ARM: OMAP: Force dmtimer restore if context loss is not detectable
ARM: OMAP: Simplify dmtimer context-loss handling
ARM: dts: AM33XX: Corrects typo in interrupt field in SPI node
ARM: dts: OMAP4460: Add CPU OPP table
ARM: dts: omap4-panda: move generic sections to panda-common
ARM: dts: OMAP443x: Add CPU OPP table
ARM: dts: OMAP3: use twl4030 vdd1 regulator for CPU
ARM: dts: OMAP36xx: Add CPU OPP table
ARM: dts: OMAP34xx/35xx: Add CPU OPP table
Documentation: dt: gpio-omap: Move interrupt-controller from #interrupt-cells description
ARM: OMAP2+: hwmod: Don't call _init_mpu_rt_base if no sysc
ARM: OMAP2+: hwmod: extract module address space from DT blob
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Merging in dependencies for the omap/dt branch.
* omap/fixes-non-critical:
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
ARM: OMAP: fix typo "CONFIG_SMC91x_MODULE"
ARM: OMAP5: clock: No Freqsel on OMAP5 devices too
ARM: OMAP5: Make errata i688 workaround available
ARM: OMAP5: Update SAR memory layout for WakeupGen
ARM: OMAP5: Update SAR RAM base address
ARM: OMAP5: Reuse prm read_inst/write_inst
ARM: OMAP5: prm: Allow prm init to succeed
ARM: OMAP5: timer: Update the clocksource name as per clock data
ARM: OMAP5: Update SOC id detection code for ES2
Signed-off-by: Olof Johansson <olof@lixom.net>
- Remove sunxi.dtsi and only use one dtsi for each SoC
- Various compatible renamings to be consistent with the other platforms
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRZDknAAoJEBx+YmzsjxAgxVsQAKZrcA+wcznKXjDIqYy2RS+J
cGW/aJIOtqt9mrTr5eBTfpUrDLKQ5EsxuAWDL4vskmKkp6BMSYCZkgVGrwSW1AQv
cNDCnIoHxGQaxtTdQA43wx8QNuaROIpXxQP/NUokGwWJzEUj5WZDcbQfnInBX9kW
Pd1UUSTMA4pYN483TW7D5Q6gXcazESrSM2PMClbQtn4Ji96cHbmkYRKETEdPQRv0
qehRrArQtIem9yFIx+ulA2i2EY8I1u67E8dWeKXNo3KlUVq21Nj4w8B2mtvboZXu
fSYG6To1Z7la+9ROzQHidKo9/gj3s47a7gUPJmmW0Eb/qoKATnkk0IcEFLk27kM+
yvMi+7ZLOX78E+7ecpzbQcCVjkEGbIcsfAiIvrHtqiKDftiXJOwPOUjJY9lKmn72
Ht+8QMIcX9W1L3yJIsA4smUYCw9DkQynOttOM3+WP0NI1/5gPsYkiXKNOWxlJzMS
0lrwd0mSmBe5CuXOCpRJ1OIfeas08AYIgexhU8wLaui2+OGh5MTD5XdF0YGbvK+9
7fdmpiwr28yTnVzIerqkce294yozTgGw5p3sxoDsfO6aox7G6JJMDKnVso0rys4O
oHVLSdk/gm10xYsLbYfiu1nev1FdzZP5XEkIh+McwZnYQsDE4S3OCc8tfFdYOxUE
XM10vZvCBobTs4GCNGam
=AIlR
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-3.10-3' of git://github.com/mripard/linux into next/dt
From Maxime Ripard:
SunXi dt additions for 3.10, take 3
- Remove sunxi.dtsi and only use one dtsi for each SoC
- Various compatible renamings to be consistent with the other platforms
* tag 'sunxi-dt-for-3.10-3' of git://github.com/mripard/linux:
ARM: sunxi: dt: Update watchdog compatible string
ARM: sunxi: dt: Update interrupt controller compatible string
ARM: sunxi: dt: Update timer compatible string
ARM: sunxi: dt: Reorganize the dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
- Remove sunxi.dtsi
- Switch to clocksource/irqchip device tree handlers
- Cleanup the watchdog code
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRZDauAAoJEBx+YmzsjxAgu8IP/3V/W2NsFOwQTz7+nVxw19zu
cGyCqqTTXed0ku0lmA4mP9x234eSwCplkzyFhnNU2hOdNaObZql8Mibkp3FBIcVn
eSq6lbCNpu0VPTjmTqaHYueYFrxmM3DeVQgiZ6m3bDdloTinfndjPKyFK1b8k6ti
OluYF25TaW8OFBJDUhXMxRiEbCLls38Z83aFpL/6k3krf/Royn75ey8uq066jyRL
d26tL2Rh0vJWojR+RUFdu6+y3CzLdOl5vUwJ/29SaarBDDxWKMIbUY4ezwmxXq2N
eCqGsxwtM6VuhYps5b//T+FdKTZbB/3U2ybH4xCU2RYDXZPigeVFT7unE0npYRry
LIern3PAKv3jOJ6kwKyEYCX1++6Yt6kyoWNKLk2FYik92KB9Pdw9yCCcpm5F/C9N
DetA4GPY/4009bNkKJrlA4Iks+TzrYp+z/qg0OxvDLYaLbknecjYutNL7on9wKrV
f5eUlVoRvecHHuf/S+V+DMId4CQrH1RP+jsDKDD6Z8hLpFQ6bnFv2QgSaVwC0f+8
dRMbN9GAReibMAR3BiYodQZnb5x9yF9sBYnRY+ZVgkS7VvsRFi6C9F7cZYQnIia1
j1x8AlFxEvNsSv1bKg5bFaWT3EpO1X2zmT30wPYuGO2XL/UVsz23Einw6jSHiJDi
M77vFMzmH30YQ2GLNbKn
=227f
-----END PGP SIGNATURE-----
Merge tag 'sunxi-cleanup-for-3.10' of git://github.com/mripard/linux into next/cleanup
From Maxime Ripard:
Cleanups for Allwinner sunXi architecture:
- Remove sunxi.dtsi
- Switch to clocksource/irqchip device tree handlers
- Cleanup the watchdog code
* tag 'sunxi-cleanup-for-3.10' of git://github.com/mripard/linux:
ARM: sunxi: Rework the restart code
irqchip: sunxi: Rename sunxi to sun4i
irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro
clocksource: sunxi: Rename sunxi to sun4i
clocksource: sunxi: make use of CLKSRC_OF
clocksource: sunxi: Cleanup the timer code
clocksource: make CLOCKSOURCE_OF_DECLARE type safe
Signed-off-by: Olof Johansson <olof@lixom.net>
Add/change conflict in drivers/clocksource/Makefile resolved.
Bringin in clk subsystem dependencies needed by sunxi.
* depends/clk-for-3.10: (26 commits)
clk: sunxi: drop an unnecesary kmalloc
clk: sunxi: drop CLK_IGNORE_UNUSED
clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flag
clk: mvebu: Use common of_clk_init() function
clk: fix clk_mux::flags kerneldoc
clk: allow reentrant calls into the clk framework
clk: abstract locking out into helper functions
clk: zynq: Add missing zynq clk header
clk: sunxi: rename compatible strings
arm: sunxi: Add useful information about sunxi clocks
clk: arm: sunxi: Add a new clock driver for sunxi SOCs
clk: ux500: Fix prcmu clocks registration
ARM: imx: adapt clk_busy_mux to new clk_mux struct
clk: Add composite clock type
clk: add table lookup to mux
clk: Fix incorrect return type in clk.c
clk: prima2: fix return value check in sirfsoc_of_clk_init()
clk:SPEAr1340: Correct parent clock configuration
documentation: clk: fix couple of misspelling
...
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRZBpzAAoJEFBXWFqHsHzOfyAH/RdvhORI0rNhBAOrSxleWlMy
AMP9x6G5tXNK/fgtxopvCiS4VXw5MB01uqJWMVM9+hx6676oCXWc/L3I6iT5l87B
qPY/e9LyGJa5aOYczPuUT2sG+Ga8989GhOksA+L6kWHZ2df0BIB9rBRZnoPezEAx
u2ATdioyzfj2rAnDNFOxsw6oai265mowt/f8J/7EQfxgkAMcKov7/BpVac0po55R
tv+Hr3T7OBg3p/h5PYi5iAehVCToCKOD31QpnlhS+dmKS52w7tEO6T75INt7HzC8
CJT0zi5jJ3/tDJsdYJ1SS4MHK4U43y0oV7cw7sO7TzNreyOB6bzTWDqhdJY2oMM=
=N7xl
-----END PGP SIGNATURE-----
Merge tag 'imx-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup
From Shawn Guo:
The imx cleanup for 3.10:
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
* tag 'imx-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: i.MX: remove unused ARCH_* configs
ARM i.MX53: remove platform ahci support
ARM: imx: remove mx6q.h
ARM: imx: remove Makefile.boot
ARM: imx: clk-imx27: Do not register peripheral clock for SSI
ARM: imx: avic: Move avic_saved_mask_reg under CONFIG_PM
ARM: imx: Remove cpufreq driver
ARM: imx: remove pl310_get_save_ptr() declaration
ARM: imx: remove duplicated function declaration
Signed-off-by: Olof Johansson <olof@lixom.net>
* A bunch of fixes for sparse warings
* One fix for the typo in use of Kconfig symbol
MACH_EUKREA_CPUIMX27_USEUART4
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRZBgrAAoJEFBXWFqHsHzOMAQH/ixzgREmkaMif54CUHJy3XB/
WzzfhUsmwucm6PY1rAPtDGxEawV4Mj+Q9tkbLljzozWNRtaDaUrkIH+MAB3NHuna
t6ANGdHjz9zvpHUHHSfslHI0gRDPM8/kGeU91QHnPi2ynBZxh1ey3+O4wz/5K0qq
GstzV88KReGIN417UtcbbbU3Urt0hdKAavB+5+/G4DNGtqGnKFhDPJ4yTUvLIZgy
DGbTfK2Zk3ynHGTj5wckmrg8oKnl1y4YkPHOyPjLocatFak8kpDf9o0CqPGzvvbL
tdjs+CnJb5AL/5zQhcMQS+TyHQVbLeQjDYs0IapRseUvz9qOqKntpUOAxdV+LCU=
=WY+i
-----END PGP SIGNATURE-----
Merge tag 'imx-noncritical-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/fixes-non-critical
From Shawn Guo:
The imx noncritical fixes for 3.10:
* A bunch of fixes for sparse warings
* One fix for the typo in use of Kconfig symbol
MACH_EUKREA_CPUIMX27_USEUART4
* tag 'imx-noncritical-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
ARM: mach-imx: mach-imx6q: Fix sparse warnings
ARM: mach-imx: src: Include "common.h
ARM: mach-imx: gpc: Include "common.h"
ARM: mach-imx: avic: Staticize *avic_base
ARM: mach-imx: tzic: Staticize *tzic_base
ARM: mach-imx: clk: Include "clk.h"
ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
ARM: mach-imx: irq-common: Remove imx_irq_set_priority()
ARM: mach-imx: clk-gate2: Include "clk.h"
ARM: mach-imx: clk-pllv2: Staticize clk_pllv2_ops
ARM: mach-imx: clk-pllv1: Staticize clk_pllv1_ops
ARM: mach-imx: cpu-imx5: Include "common.h"
ARM: mach-imx: iomux-imx31: Staticize mxc_pin_alloc_map
ARM: mach-imx: mm-imx3: Staticize imx3_init_l2x0()
ARM: mach-imx: cpu: Include "common.h"
Signed-off-by: Olof Johansson <olof@lixom.net>
The ARM perf core code used to rely on the pmu node being
compatible with "arm,cortex-a9-pmu", even when the PMUs
of the different Cortex-A processors are not really
compatible... This is no longer required and actually
became harmful, so remove all the offending values
from Versatile Express DTS files.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
A series dealing with gpio configuration cleanup from Haojian Zhuang.
* 'armsoc/pxa' of git://github.com/hzhuang1/linux:
ARM: pxa: move debug uart code
ARM: pxa: select PXA935 on saar & tavorevb
ARM: mmp: add more compatible names in gpio driver
ARM: pxa: move PXA_GPIO_TO_IRQ macro
ARM: pxa: remove cpu_is_xxx in gpio driver
Signed-off-by: Olof Johansson <olof@lixom.net>
Move debug uart code from mach-pxa/mach-mmp to debug directory.
Since they are similar, merge them together.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Eric Mico <eric.y.miao@gmail.com>
Since more driver names are added into platform id, do the same thing on
compatible names for DT mode.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Since PXA_GPIO_TO_IRQ() & MMP_GPIO_TO_IRQ() macro are depended on
arch code, move them from gpio driver to platform driver instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Avoid to use cpu_is_xxx() in pxa gpio driver. Use platform_device_id
to identify the difference.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This converts sched_clock to simply a call to a function pointer in order
to allow overriding it. This will allow for use with 64-bit counters where
overflow handling is not needed.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Allow multiple calls to setup_sched_clock and switch to the new counter
if it is higher frequency.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Commit 92702df357 ("ARM: OMAP4: PM: fix PM regression introduced by recent
clock cleanup") makes the 'ocp2scp_usb_phy_phy_48m' as optional
functional clock causing regression in MUSB. But this 48MHz clock is a
mandatory clock for usb phy attached to ocp2scp and hence made as the main
clock for ocp2scp.
Cc: Keerthy <j-keerthy@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[paul@pwsan.com: add comment to the hwmod data to try to prevent any
future mistakes here]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
LaCie has released two products under the CloudBox name. The
netspace_mini_v2 machine is embedded in the oldest product. The cloudbox
machine is embedded in the newest one. In order to allow a CloudBox user
to select the right machine support, this patch adds some informations
to the netspace_mini_v2 Kconfig description. A comment is also added to
the dts file.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds DT board setup for the LaCie NAS CloudBox. The CloudBox
is a low cost NAS based on the Network Space v2.
Chipset list:
- CPU MARVELL 88F6702 1Ghz
- SDRAM memory: 256MB DDR2-800 (2x128MB x8) 400Mhz
- 1 Ethernet Gigabit port (PHY MARVELL 88E1318)
- SPI flash, NOR 512KB
- 1 push button
- 2 LEDs (red and blue)
There is no EEPROM and no USB ports embedded.
Note that this board must not be confused with the Network Space Mini v2
which is embedded in a previous LaCie product also named CloudBox.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch sorts board entries in files Kconfig, Makefile and
kirkwood_defconfig by ASCII-code order.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch fix the regression introduced by the commit 3202bf0157
"arm: mvebu: Improve the SMP support of the interrupt controller":
GPIO IRQ were no longer delivered to the CPUs.
To be delivered to a CPU an interrupt must be enabled at CPU level and
at interrupt source level. Before the offending patch, all the
interrupts were enabled at source level during map() function. Mask()
and unmask() was done by handling the per-CPU part. It was fine when
running in UP with only one CPU.
The offending patch added support for SMP, in this case mask() and
unmask() was done by handling the interrupt source level part. The
per-CPU level part was handled by the affinity API to select the CPU
which will receive the interrupt. (Due to some hardware limitation
only one CPU at a time can received a given interrupt).
For "normal" interrupt __setup_irq() was called when an irq was
registered. irq_set_affinity() is called from this function, which
enabled the interrupt on one of the CPUs. Whereas for GPIO IRQ which
were chained interrupts, the irq_set_affinity() was never called and
none of the CPUs was selected to receive the interrupt.
With this patch all the interrupt are enable on the current CPU during
map() function. Enabling the interrupts on a CPU doesn't depend
anymore on irq_set_affinity() and then the chained irq are not anymore
a special case. However the CPU which will receive the irq can still
be modify later using irq_set_affinity().
Tested with Mirabox (A370) and Openblocks AX3 (AXP), rootfs mounted
over NFS, compiled with CONFIG_SMP=y/N.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reported-by: Ryan Press <ryan@presslab.us>
Investigated-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Ryan Press <ryan@presslab.us>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
As multi-platform build is being adopted by more and more ARM platforms,
initcall function should be used very carefully. For example, when
CONFIG_ARM_OMAP2PLUS_CPUFREQ is built in the kernel, omap_cpufreq_init()
will be called on all the platforms to initialize omap-cpufreq driver.
Further, on OMAP, we now use Soc generic cpufreq-cpu0 driver using device
tree entries. To allow cpufreq-cpu0 and omap-cpufreq drivers to co-exist
for OMAP in a single image, we need to ensure the following:
1. With device tree boot, we use cpufreq-cpu0
2. With non device tree boot, we use omap-cpufreq
In the case of (1), we will have cpu OPPs and regulator registered
as part of the device tree nodes, to ensure that omap-cpufreq
and cpufreq-cpu0 don't conflict in managing the frequency of the
same CPU, we should not permit omap-cpufreq to be probed.
In the case of (2), we will not have the cpufreq-cpu0 device, hence
only omap-cpufreq will be active.
To eliminate this undesired these effects, we change omap-cpufreq
driver to have it instantiated as a platform_driver and register
"omap-cpufreq" device only when booted without device tree nodes on
OMAP platforms.
This allows the following:
a) Will only run on platforms that create the platform_device
"omap-cpufreq".
b) Since the platform_device is registered only when device tree nodes
are *not* populated, omap-cpufreq driver does not conflict with
the usage of cpufreq-cpu0 driver which is used on OMAP platforms when
device tree nodes are present.
Inspired by commit 5553f9e26f
(cpufreq: instantiate cpufreq-cpu0 as a platform_driver)
[robherring2@gmail.com: reported conflict of omap-cpufreq vs other
driver in an non-device tree supported boot]
Reported-by: Rob Herring <robherring2@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The OPP library support is needed for exynos5440 cpu frequency
dynamic scaling driver.
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This patch moves cpufreq driver of ARM based sa11x0 platform to drivers/cpufreq.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Just like the OHCI counter part we just can remove the architecture
specific symbols which prevent these configuration symbols from being
selected by platforms/architectures requiring it. The original
implementation did not scale at all since it required each and every
single architecture to be added for these configuration symbols to be
selected. Now it is up to the EHCI driver and/or platform to select
these configuration symbols accordingly.
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRZDATAAoJEA0Cl+kVi2xqWoYQALCp4Pg0OkedFNijPU4w7DOT
twK/ckrsNr/JM3Kh6ZXqyTRtIMp9rjU9GIzNUiO/rIIUUAwrf+M9TvUdgmIe7Izc
S+MYDny4cm+tCsuxsrcAIQXCknHYiw1ffmDSn6XB71BSRJJ3IrF6YbWDmBRwAl11
CY1+g+q7FLyriS3kw4FGyPvks0kQhk3U63wFhR5+s3i8y1VVMEp5hU6U9p6pCgBR
4oeTy2vzQAmoKs7Ngo38QgRVlv6m4HPx7SiXYBgoD/I09itUh+V8C3rv4gdqH6DT
+Klf2xzd6PSYYyA0dryKM+gZTSzXeChHNh49gOza5p8z5GI5EpGPFpKdPcmXWLFQ
nIRcJzf2talieO8WvD4nlYy0Wa3Fyn6U3GJewV/tKgzmY3hxMyVSOGA6WwO/3iil
Z0jPOF3ZfOPWRhjMNDmO7yYltawin86tItfCmdspFxtLVsjfc/K0n52QzFQMKG7b
/sgC9JZCTgAQsF/WASZ7xkMEQAbysDcXqxyiXJYrmkrgwUoH8PUWR2YhEMf6BLwK
6BSfyXZ4UiPYo7zKgxtIOcWCXll0DpunAFmVHBIiMjzD7LGKHrpXg8z7SdqFomYK
wKP8EgCfg34gCnFOFfke+8xa72osz6EQ/yf2YLoibl/9vA+Ym02Mt5gU81h1xRNA
f7xTUKayXrp4rSlf+ZRS
=X1N2
-----END PGP SIGNATURE-----
Merge tag 'devel-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim <kgene.kim@samsung.com>:
including various development for samsung for v3.10
* tag 'devel-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: replace cpumask by the corresponding macro
ARM: EXYNOS: handle properly the return values
ARM: EXYNOS: factor out the idle states
ARM: SAMSUNG: check processor type before cache restoration in resume
ARM: S3C64XX: Slow down mic detection rate for wm5102
ARM: S3C64XX: Clear DMA flags on channel request
ARM: EXYNOS: Clear ENABLE_WAKEUP_SW bit when entering suspend
ARM: EXYNOS: Remove hardcode wakeup unmask for EINT_0
ARM: EXYNOS: Add support for rtc wakeup
ARM: SAMSUNG: Export MIPI CSIS/DSIM PHY control functions
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYvj+AAoJEA0Cl+kVi2xqyK8P/09bx/H2Ud/1WL3/eGV3qfCd
MuSGk/nIHCZ75MBQnIwtKoJ44cyqopJh8xC5wptORMKP6k9MDh5gXYPiClmAQBOT
82SH0zZorPtANMHivTvxWr7mBs0/fCIXjR6Sg43vMRzM5Nz9l6RFjzZr7RiAm7lr
G1gjfG3LDAoaiomVG6Okof7og4wfJQe9ROdRe2oCRepCCUJ9l5tYptYwA/ulo6ge
3H/+OcxkOQYu7X+zKZWjnZTFLzBkaivnfUxQo969yowrAtdTkrWQdDEih+hsxXl+
KPEhwhKJnS7Kl6ZRSK2/Y8baNIZrFHsc7r4ZdZ7IVVhAoPCQsO0C0k8w5hD1mXwL
7kEtw/0uioTb5uE03GUdCg7Ibq+kVhAdRLfBDFx7rHb9Ef7WJ/OZXj2zYv3yHFrG
PQA58jJ75uBym/104QdlB5D68bn8D2+HqqYu1glnd+SnjabtNtNXiONRo6HWEBfM
V2mGlDBUps91zcuiUKlNkO1v0ZK63VmxDj+JnKvKbI3gXCMeZg9aGYSorGSlq6vv
t8Qws2cQKMdkJzYQNqOXOYl32T3tvRjWbu0g874w6lXGBxt7sQgD8maljdFPH8/s
YC/3gk7E6ugOiQ1dqBQEjR29cLwYQ6SzF9t3N8kvLQog81VS3uVDxt2sIwaqariS
wHPrZPKsma6XE5jldGAA
=L8iS
-----END PGP SIGNATURE-----
Merge tag 'timer-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
including fix for GENERIC_GPIO based on previous pull-request for timer-samsung
* tag 'timer-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: change GENERIC_GPIO to ARCH_REQUIRE_GPIOLIB
Signed-off-by: Arnd Bergmann <arnd@anrdb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYugaAAoJEA0Cl+kVi2xqvi0QAKyF/UbDR6aOSIOoCzgm1iUC
+F9WvvCLyJdy0y09IKEbwM+aZyzsfC7vO/9wp58ROv1AhD9f1/yk1H+O8NRS668v
jt8RZlrL30ea0HkRjHRgTCS2sObCXG2pGOduX9i5XKCC4EnM9P/qNe4uJjziY8K8
FmAanWpJahe0E9szLnWDuF7hhsRkTpjrLWtYYmc1H4LXydoZnxEgGM3xjbqL+m4/
BPwlCrPtu/WsZzM7Tdx6fVIC2wryrwoH5e1EL3fI2IrWhreOtVWYzoTwUoSy7Xbz
ERjQoCt3yNVmPO1TwfS9nR/bc0+j8gsFuJRzN42PsP09JFQPVt8Q1o1cpIIHWgvZ
/pkJAsaBfbQgPOLNof5uHasPVSZYe38TIey782hYA0pmT1RCt46FuJ6zM9M0483q
4vysYCU/Vc3GOtAQOpsCNbsEMthRzjtjsJoZ5owDsCaiV+eNWC3VrWI2Wm1EO7Mn
FUthkBY58jPM/9BdFC67ZwBPtSSUhAeZpcUXkcaNj8pgw8Rvfcip/09Vy0Uh0Ef8
A5dYZec8CNyZKECspzUTlgwyK7xiWD0r3uyr4/a413qb1pr9zdOFlZeespT9bgfI
uD+tMPpJ+R9fK9BSbRw9FMx1Pe395vZRUmu9WepvQDwQDvoYSi/SVKBMYtn27Bsm
CD/r/wUs1ktL2rPNcXVz
=Os9U
-----END PGP SIGNATURE-----
Merge tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add support exynos mct device tree and move into drivers/clocksource
* tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
clocksource: mct: Add terminating entry for exynos_mct_ids table
clocksource: mct: Add missing semicolons in exynos_mct.c
ARM: EXYNOS: move mct driver to drivers/clocksource
ARM: EXYNOS: remove static io-remapping of mct registers for Exynos5
ARM: dts: add mct device tree node for all supported Exynos SoC's
ARM: EXYNOS: allow dt based discovery of mct controller using clocksource_of_init
ARM: EXYNOS: add device tree support for MCT controller driver
ARM: EXYNOS: prepare an array of MCT interrupt numbers and use it
ARM: EXYNOS: add a register base address variable in mct controller driver
Conflicts:
drivers/clocksource/Makefile
drivers/clocksource/exynos_mct.c
[arnd: adapt to CLOCKSOURCE_OF_DECLARE interface change]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYueLAAoJEA0Cl+kVi2xqRggP/1dM6P8T68AB8iJC1DQuE3B7
d6Edy+mRRU1lFvJ0QCn/QxzWl7r3pYr47yvMcKpnlFpyaqOMtqVGzff5rCts6Hsu
9km3UA42W7dO9/NLdSOg8GKZPV/3pFTjEnNNdux17pgihBv4ZciIGiivek5kVXCR
mDh7lMAA6GJuEHxoaUumUp0v+dVfquQcRra8ZxV9rHpHzfy48YFJO7wPlTd2b0EY
fFMq/cJxHre2+jEuLZiuEvuRgBKpXG1oc7BeU5Gt3moCTdD+HRODEgSZJaTUmAtK
/jKKUCjvJaDEuL5Xr4Votby0bNniEq4XGGkIAH9iNC47S8tzsiyKNhl5y1H1lFcv
JOZvVFQ0aT4XY+vX8wXwNfafsecF4n4lUky6xUORDH8NBMsuUw9PCQmGLpZY/IqR
j/XhO2KLkb7HaIHNj2DsMwslQiTj9dxSH8C+zBQbVoIb/3XipQooUx9FdLDA99a/
Ni9U6xAF9L4B48rIamB0Af10Ig5sKCE1dFS15yJy2KTesABUyxbbbEVyi0sl1Ugt
zEWpcISUdKbA0GDivN/hsBsfFBkwG4F/Su6iF62NSxWlXj9kSOpTdjluM0haUlfG
nbYU5lyF8dVUFLaWBdRF6tYW9EollgmXJBDdaIeS6qVoqWOy0Cjz+VS4eOvAm0ew
Hi2tJDHMW41K3jBVxJV6
=Sitv
-----END PGP SIGNATURE-----
Merge tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
s3c24xx irq cleanup and move into drivers/irqchip
* tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
irqchip: s3c24xx: add devicetree support
irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
irqchip: s3c24xx: globally keep track of the created intc instances
irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
irqchip: s3c24xx: fix irqlist of second s3c2416 controller
irqchip: s3c24xx: fix comments on some camera interrupts
ARM: S3C24XX: move irq driver to drivers/irqchip
ARM: S3C24XX: add handle_irq function
ARM: S3C24XX: make s3c24xx_init_intc static
ARM: S3C24XX: move s3c24xx_init_irq to s3c2410_init_irq
ARM: S3C24XX: fix irq parent check
ARM: S3C24XX: fix redundant checks in the irq mapping function
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The tegra assembly files are written for ARMv7 and are not compatible
with ARMv6, which leads to build warnings when compiling a dual
ARMv6/v7 kernel. Since this code is only ever run on Tegra ARMv7
hardware, we can tell the assembler which architecture level to
use.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The TWD and SCU configs are selected by default as long as
MSM_SCORPIONMP is false and/or MCT is false. Implementing the
logic this way certainly saves lines in the Kconfig but it
precludes those machines which select MSM_SCORPIONMP or MCT from
participating in the single zImage effort because when those
machines are combined with other SMP capable machines the TWD and
SCU are no longer selected by default.
Push the select out to the machine entries so that we can compile
these machines together and still select the appropriate configs.
Cc: Barry Song <baohua.song@csr.com>
Acked-by: David Brown <davidb@codeaurora.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Simon Horman <horms@verge.net.au>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Viresh Kumar <viresh.linux@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The only part of proc_dir_entry the code outside of fs/proc
really cares about is PDE(inode)->data. Provide a helper
for that; static inline for now, eventually will be moved
to fs/proc, along with the knowledge of struct proc_dir_entry
layout.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
The OMAP5 idle driver can re-use most of OMAP4 CPUidle driver
implementation. Also the next derivative SOCs are going to re-use
the MPUSS so, same driver with minor updates can be re-used.
Prepare the code so that its easier to add CPUidle support for
OMAP5 devices.
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Current OMAP4 CPUIdle driver is using omap4_mpuss_read_prev_context_state()
to check whether the MPU cluster lost context or not before calling
cpu_cluster_pm_exit(). This was initially done an optimization for
corner cases, where if the cluster low power entry fails for some
reason, the cluster context restore gets skipped. However, since
reading the previous context is expensive (involving slow accesses to
the PRCM), it's better to avoid it and simply check the target cluster
state instead.
Moving forward, OMAP CPUidle drivers needs to be moved to drivers/idle/*
once the PRM/CM code gets moved to drivers. This patch also reduces one
dependency with platform code for idle driver movement.
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[khilman@linaro.org: minor changelog edits]
Signed-off-by: Kevin Hilman <khilman@linaro.org>
It is useful to know the CPU power state along with MPUSS power state
in a supported C-state. Since the data is available via sysfs, one can
avoid scrolling the source code for precise construction of C-state.
Reported-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
If the CPUidle device registration fails for some reason, we should
unregister the driver on error path.
Fix the code accordingly. Also when at it, check of the driver registration
failure too.
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
OMAP4 CPUidle driver registration call is under a loop which leads
to calling cpuidle_register_driver twice which is not intended.
Fix it by moving the driver registration outside the loop.
Reported-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
The TIME_VALID flag is specified for the different states but
the time residency computation is not done, no tk flag, no time
computation in the idle function.
Set the en_core_tk_irqen flag to activate it.
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- Adds devicetree binding and documentation for the smc handler
Updates from V1:
- Created this separate patch for the DT portion
- Added SoC compatible to smc binding
Signed-off-by: Christian Daudt <csd@broadcom.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
- Adds a module to provide calls into secure monitor mode
- Uses this module to make secure monitor calls to enable L2 cache.
Updates from V1:
- Split DT portion into separate patch
- replace #ifdef-ed L2 code with "if".
- move init call to board init
Signed-off-by: Christian Daudt <csd@broadcom.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
This branch contains the majority of the device tree changes for Tegra.
Highlights include:
* Many changes for Tegra114, and the Dalmore board, to enable pinctrl,
SDHCI/MMC, PWM, DMA, I2C, KBC, SPI, battery, regulators.
* Adding or enabling suspend wakeup sources on many boards, and adding
suspend timing parameters, to support the system suspend patches.
* Adding clocks to the audio-related nodes, so that in 3.11, the audio
driver can pull these clocks from device tree rather than hard-coding
clock names.
* Some small DT fixes/cleanup.
This branch is based on the previous clk pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXv7mAAoJEMzrak5tbycxfzIQAMPNW66IgtRLDKat5R2ixBqp
2LE4qQnndwYvql54WeIHCHPm71mO0E6oOtss+0jmDh0nmeQ0D0CzxCrV1JjbFNJK
Eo9ayRdujCrYn3V3ru6k4NyVZa3keupCVKTJRwxGxRYqwXBxFLBPhzBiHhBoOi9W
lJZNUQ+MRa4YpTQgUa9xmVwHaPJZMoWs1WQwJMllFyWABTlP+/y3JmfyqQ0A+CGF
myToy57ZN6YDAoWxNw+dixRW7O0wk4kweVZuf3s+/Sg0FxuJL+FZgtPVD8DeeFxz
zhROxF2Cy75V9Z+48cECbjm0HxqBZAhkkomTOpL6eSMw61DCr4OzWLEi6A7ILO/Y
02kRDqbQ/IRL4Di7nvoKhY6wLg3AdZXyvZkf+W0bLu19WrHbah7ruba/9uTA72ZI
W7gx3QYKRrCvJOFNkeIHO84Lp7FEV60L/GYQgWXHTwozxP9PLmqg4bRSLX20rhPD
3Vi9zjpRJ9C2GstljVr+aORRn4A1QbWciYAkv2CCIIrh0xwm8YSclgWiTf95AVka
xmPp3fwhc3VZLGHhD1wpT5UJnzzZekBQzP0+QF6K+nSp7TMtPrTFuWwMCJybq463
vjagS6m7DDXNCTvJee+D/3dHkeDCgIPGGr0LbjopxB/FKsCevZWFOtNCJxkbi+t6
ojwrLwqs++Yq59pBFvee
=avad
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt2
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: device tree changes
This branch contains the majority of the device tree changes for Tegra.
Highlights include:
* Many changes for Tegra114, and the Dalmore board, to enable pinctrl,
SDHCI/MMC, PWM, DMA, I2C, KBC, SPI, battery, regulators.
* Adding or enabling suspend wakeup sources on many boards, and adding
suspend timing parameters, to support the system suspend patches.
* Adding clocks to the audio-related nodes, so that in 3.11, the audio
driver can pull these clocks from device tree rather than hard-coding
clock names.
* Some small DT fixes/cleanup.
This branch is based on the previous clk pull request.
* tag 'tegra-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits)
clk: tegra: Fix cdev1 and cdev2 IDs
ARM: dts: tegra: add the PM configurations of PMC
ARM: tegra: add non-removable and keep-power-in-suspend property for MMC
ARM: tegra: whistler: add wakeup source for KBC
ARM: tegra: add power gpio keys to DT
ARM: tegra: keep power on to SD slot on Dalmore
ARM: tegra: add clocks property to AC'97 sound nodes
ARM: tegra: add clocks property to sound nodes
ARM: tegra: dalmore: add fixed regulator node
ARM: tegra: dalmore: add TPS65090 node
ARM: tegra: dalmore: add cpu regulator node
ARM: tegra: Add sbs-battery node to Dalmore
ARM: tegra: add DT binding for i2c-tegra
ARM: tegra: add SPI nodes to Tegra114 DT
ARM: tegra: add KBC nodes to Tegra114 DT
ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114
ARM: tegra: add I2C nodes to Tegra114 DT
ARM: tegra: add APB DMA nodes to Tegra114 DT
ARM: tegra: add PWM nodes to Tegra114 DT
ARM: tegra: fix the status of PWM DT nodes
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A trivial patch to replace for_each_cpu(cpu_id, cpu_online_mask) by
the corresponding macro.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The cpuidle_register_driver return value is not checked.
The init function returns always -EIO when cpuidle_register_device
fails but the error could be different.
This patch fixes that by checking the cpuidle_register_driver properly
and returning the correct value when cpuidle_register_device fails.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The states are defined in the driver. We can get rid of the
intermediate cpuidle states initialization and the memcpy by
directly initializing the driver states.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This branch contains most fixes and enhancements to the Tegra common
clock driver. The main new feature is a driver for Tegra114, which
coupled with later device tree changes enables many devices on that
chip, such as MMC, I2C, etc.
This branch depends on a patch in:
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
Mike has stated that this branch is stable, and is aware of this
dependency and merge.
Mike's branch is based on v3.9-rc3, which includes a USB change which
causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence,
this branch pulls in v3.9-rc4 to ensure bisectability as much as
possible.
This branch is based on v3.9-rc4, followed by a merge of previous Tegra
"soc" pull request, followed by a merge of clk-for-3.10.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXv21AAoJEMzrak5tbycxRAsQAK0U+y5RWQJVR1wQYAuw2AhP
wX/5BcpDWhH4HrFKUGp0NrVvASHv706bbvnbSsUFeKtMGqRFaiOW756B80R0mnIG
xjILt64A7kXCMRJeUoXhdJtXQfzNbgGqKUsBJknVHHBw72OhYBXop5ihMWqI9Kk6
yEsr+/CB9VlV7ZbiLaAXelKuh7oSdaG8ada6qFeRCJhpVVdrFP4aGYkt0iipOBAU
GBnoISkmp/ocExXlC2n5nIEE0rukJ+KyPwR1bY4+Yj2ZFXL24Nczh8cEZFrV2yz8
Sa+/6qrowGTw/wPUK+R8+vCvfzKdCYG6rrnyWwwb9UbsP6LAcYz/WB+q0puPZeuZ
2T82osvbFxjGMYWnR2Uc4CRTid1ophxGWRh810fg1UGMIK4HRMmCxrV6D5Af3FPz
rXNEf3CCd4iKJQBBYXZAR1TNn5vSX/USeqXvb0810qwe2jwJsiZP5FhZH5Ogfvod
W825UpmS1zmEz4MI65/CE3fxZ8SsM9Khdp4tl25YfTJ5RMjShzRdsl4BATa8nXpr
nDfBb8pE2s6hyUWXbnNHw+k4jmQMreEHp+guE6LWYmqBcVlrJpq5joIHqwRl4dyD
iri9unSvbOAN+fJMXti0uW8zruitfbZgfzwRwwFy1TP0DPQBWVWwN7AABFlItD6M
pWI9Uf3VL5wAHZmWe6Gq
=Hasc
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: clock driver development
This branch contains most fixes and enhancements to the Tegra common
clock driver. The main new feature is a driver for Tegra114, which
coupled with later device tree changes enables many devices on that
chip, such as MMC, I2C, etc.
This branch depends on a patch in:
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
Mike has stated that this branch is stable, and is aware of this
dependency and merge.
Mike's branch is based on v3.9-rc3, which includes a USB change which
causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence,
this branch pulls in v3.9-rc4 to ensure bisectability as much as
possible.
This branch is based on v3.9-rc4, followed by a merge of previous Tegra
"soc" pull request, followed by a merge of clk-for-3.10.
* tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
clk: tegra: fix enum tegra114_clk to match binding
clk: tegra: Remove forced clk_enable of uartd
ARM: dt: Add references to tegra_car clocks
clk: tegra: devicetree match for nvidia,tegra114-car
clk: tegra: Implement clocks for Tegra114
ARM: tegra: Define Tegra114 CAR binding
clk: tegra: Workaround for Tegra114 MSENC problem
clk: tegra: Add flags to tegra_clk_periph()
clk: tegra: Add new fields and PLL types for Tegra114
clk: tegra: move from a lock bit idx to a lock mask
clk: tegra: Add PLL post divider table
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
clk: tegra: Add TEGRA_PLL_BYPASS flag
clk: tegra: Refactor PLL programming code
clk: tegra: provide dummy cpu car ops
clk: tegra: defer application of init table
clk: tegra: Fix cdev1 and cdev2 IDs
clk: tegra: Make gr2d and gr3d clocks children of pll_c
clk: tegra: Export peripheral reset functions
clk: tegra: Fix periph_clk_to_bit macro
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is a snapshot of the stable clk branch at
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
which is a dependency for the tegra clock changes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The external pending interrupt register address (EINTPEND) offset is
0xa8, not 0x08. Without this patch the external interrupts are not
properly acknowledged, which may lead to an interrupt storm and the
system hang as soon as any external interrupt is requested.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Various new features are enabled:
* Tegra114 support.
* Various PMICs and related options for Tegra114 platforms.
* KEYBOARD_GPIO, mainly as a suspend wakeup source.
* tegra_defconfig is rebuilt based on v3.9-rc1, which causes various
layout changes.
This branch is based on v3.9-rc1.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXwAZAAoJEMzrak5tbycx0u8P/jhuyYd4HyKRhrZOR8+hVUeE
KmOuaVQ8wqrL3w+w2jkTgxw+JEfut3kzo4tKS96+Bm8tiLNnxnMDqU+U0kpkfWln
IFYq4SpsK17sRLaEJt8HY/u9mTRRFlwm6tk08l75PL4TcI9Y0NNTlFqiEhjjOh+X
EFxP1wIS3k4bP0/+MRsUUMI1ZhFKI+TSh5x1QJMlWwrDQ158k1ETBfRsYMq1srU6
KBKTk0D4SpEVXYAqwmklVW/DnxzwZUEyfysp10pueGoFHoZ0k8FkrUVvhTpbxR6G
CXrkD5xNSn9utw7F+uRnbXMFcabIMHwxCyg5d5Q+DBNAzXtoMXXjWW/s/g/wWPD1
ykPmyzZsCYEzZkI8Qh2kTaAGq7ROIwS/Bui8Dbut3rwCJ08Z9nyiR6S9Pfy6pzaz
UcnrqEHBPVMSWH6CDIDkACdQfClhPl5ncukUDvb0EiqnJG4bB2TyeFY4PnRvk4GP
kwqjxoh9KVDluMcO2kGyIurLv6G+H5m+6ZK4nZYdAXY0lqDcp3sEWFrFgD3Z7oso
Ybvs2pzej3pssAkgMCjhwJWod1G7Z21hZxp8c5r5AczQkASPZPQ0GkuZJRHUa2oX
r+hnue7cG6DmXdlF2EVJO3RqsS4CFam0sUg44BXzKOfU/+iLiLE/juvqR+5EZdsB
B6phxTsX+V5ygu3UmFW6
=hXL+
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: defconfig changes
Various new features are enabled:
* Tegra114 support.
* Various PMICs and related options for Tegra114 platforms.
* KEYBOARD_GPIO, mainly as a suspend wakeup source.
* tegra_defconfig is rebuilt based on v3.9-rc1, which causes various
layout changes.
This branch is based on v3.9-rc1.
* tag 'tegra-for-3.10-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: defconfig updates
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch converts Tegra to support multi-platform/single-zImage.
One header is made accessible to drivers. The earlyprintk implementation
is moved to the multi-platform location. Some Kconfig changes are made
to enable multi-platform. Some dead files are deleted.
The APIs exposed in the now-global tegra-powergate.h should be replaced
with standard reset and power domain APIs in the future.
This branch is based on (part of) the previous soc pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXv+xAAoJEMzrak5tbycxjscP/iw1p3mtm0/8levUUOty5vHB
a4/5P5nFZDCxDW8eWbf4cN6lg4dWLDaWo9SLF1pRZXc5opliyAai8/qVJYz++2T1
6FsJOg+PqMks0UKBXS5yR+P84cdTB55B71NQpaGe2oCwyIjuNnAZ5rTp4+/1RO4S
aXdshQA+1aWVrfGe3nvigrpyPSM2Mmul/Lf0dtyaoFVWknGJT+CWu6upgzwIAWiu
C8oolkkqmrsU/m9m+PJtmdtn0aD8oGQOPSuCcz/ExAy7GhTgcuTRdiUjmrcBgr7t
d4phwXQ2gKLdSHxToBKLxZbnRqM69I1h0Ybcxakz9ICsaQ3yE6J6qq4tYlqoezYZ
l9TH5VmdfnWdU/1ZBqyX/8+EyzUu2fI6uR4d78FYkmVfcEoAe/YvOx7A/CFUI5zN
kYvrLjaLTRCRsgM4WuRMLGR4TN3Zq6ciC/QECD83xMfyWjwZGWfi9+2DIdQv2ge4
DJoJhNTHCHq1fPWsadnYgL93DjXCF5+w+d3nVz0vxNHfVz6DEYJyepkfmX0poEu0
RJg32cnW8rwDcqM97vnzUnV3ZSU1VZUA3Upf7uZALPwjxV4m7fQbytQU9pd0YU5B
ZNRRb6MY9xjU/Z5lK5lGNttbwfuIbKobNDiVY0lJKTrSTJLAOO9MHs8HQ+lMzYXa
1jO31FETA5RpCKrPHvSi
=6+gD
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatform
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: multi-platform conversion
This branch converts Tegra to support multi-platform/single-zImage.
One header is made accessible to drivers. The earlyprintk implementation
is moved to the multi-platform location. Some Kconfig changes are made
to enable multi-platform. Some dead files are deleted.
The APIs exposed in the now-global tegra-powergate.h should be replaced
with standard reset and power domain APIs in the future.
This branch is based on (part of) the previous soc pull request.
* tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: convert to multi-platform
ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds a cpus/cpu@0 node for imx51 with default operating
points for the cpufreq-cpu0 driver. There is currently no regulator
support, so the voltages are 0 here.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds the PATA device and the pinctrl group for to the i.MX51 dts.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Wandboard is a development board that has two variants: one version based
on mx6 dual lite and another one based on mx6 solo.
For more details about Wandboard, please refer to: http://www.wandboard.org/
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The sabreauto and sabresd boards are common for imx6q and imx6dl.
Create imx6qdl-sabreauto.dtsi and imx6qdl-sabresd.dtsi for those
common parts.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add a pinctrl driver for i.MX6 SoloLite based on pinctrl-imx core
driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The imx6dl is a derivative of imx6q with very limited difference. These
two SoCs are so compatible that they can be handled as one platform in
software. That said, we will not have target SOC_IMX6DL but just
reusing SOC_IMX6Q. That's why the pinctrl-imx6dl driver is added here
with symbol PINCTRL_IMX6Q controlling the build of it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT must be configured as 1
instead of 0 to have AUD4 muxed on SD2 pins working.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add cpufreq-cpu0 platform device for imx5 DT init and register the clock
for imx5.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Adds cpufreq-cpu0 platform device for imx27 DT init and adds a clock
registration for cpufreq-cpu0 device.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The APF27Dev is a docking board for an APF27 SOM
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 already has a devicetree node for the GPT, but not yet
has the clocks. Add them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The GPT is the GPT timer found on i.MX SoCs. This patch adds the
devicetree node for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The GPT is the GPT timer found on i.MX SoCs. This patch adds the
devicetree node for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The GPT is the GPT timer found on i.MX SoCs.
Since this is the first user of the AIPS2 this patch also adds it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The GPT is the GPT timer found on i.MX SoCs.
This adds the missing GPT devicetree nodes. Also fixup the watchdog
register map size along the way. it's 0x1000, not 0x4000. This didn't
hurt before as the region was not occupied by another device, but now
overlaps with the GPT.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add a second pinctrl group of pins for i2c2.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add ecspi2 group of pins for imx51.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The APF51Dev is a docking board for an APF51 SOM
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Allow AUD3 to be used as audio output from the audmux block.
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function. Every time a new imx SoC support is
added, we need to add such a big mount of data. With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.
With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.
The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.
As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Replace /include/ (dtc) with #include (C pre-processor) for all imx DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.
This allows future use of #defines and header files in order to define
names for various constants, such as pinctrl settings. Use of those
features will increase the readability of the device tree files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add ARM Cortex A9 Performance Monitor Unit (PMU) support.
On i.MX6 a combined interrupt on hardware line #126 is used
(i.MX6 TRM: Performance Unit interrupt).
For more details see Documentation/devicetree/bindings/arm/pmu.txt
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Due to NR_IRQS being incorrectly defined not all IRQ domains can
be registered for S3C2440. It causes following errors on a s3c2440
SoC based board:
NR_IRQS:89
S3C2440: IRQ Support
irq: clearing pending status 00000002
------------[ cut here ]------------
WARNING: at kernel/irq/irqdomain.c:234 0xc0056ed0()
...
irq: could not create irq-domain
...
s3c2410-wdt s3c2410-wdt: failed to install irq (-22)
s3c2410-wdt: probe of s3c2410-wdt failed with error -22
...
samsung-uart s3c2440-uart.0: cannot get irq 74
Fix this by increasing NR_IRQS to at least (IRQ_S3C2443_AC97 + 1)
if CPU_S3C2440 is selected, so the subintc IRQ domain gets properly
registered.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
information. Also enable few HW errata workarounds for omap4.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRY1HIAAoJEBvUPslcq6VzAjgP/2nbQFegPSVWTSknj3c6q/Ko
uAdfxRL/wW9NYBqLtb/+ErX8jP8J9+vR8z2NKuFZTGLMH1PiNjEkN9HVoKhX8mEn
84S8pcSwM+8fMiJgwxGmY9Np13Lsm5YWJDr4QkrX4vOmqj/s766lMgMWJjkPg01D
pJw9QTXlXilZBIzoPrKXreLVc7Tw4cquKbqpgfJta+vRocKwofddpUWv1yJ8jCtc
8a0ey70NDNFnp+QSd8yaDJx4pvw8S+B4cmc+g+15euPlzZFbktXdPv2KCiW8B+/3
h+HYKxtJcsxcXg4Syz/WrG5nycOHAiSLkhNAiYY/9sQTWlL+68e9I6NF6Nv+QsgI
cPqbHhJbVTet7+FM9b05Aw/biyUlVdC8LGhFdho6z7Y7HjyvsaIXl8cW6P3qKaFz
uSRxDQQ2O76qjxXKY7R3Nlw96JeQ37FEfKnaaOZTrDPg5HHtZjkUqre7uCVcHfu4
riCdP47N1r3sumIVk70zX7yHdUAZWBk21/3f/3YkDfvsz7rUeHdp6wXOzOHa1Rc/
YB8oi9h+Q9f7G7T5iqV9AETLOVbv8UXtImy8pzzVyrg2PAhIrEaz/vYG+MmcHaIN
78+LDgdDi9gKlhk0wx1Hl5exf1qJaCN7aufAydzNZXYlyxaIyQnCv8vfxfaCxI54
KfZ4SieUzpm87A/tVqDj
=bKnC
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren <tony@atomide.com>:
Changes needed for enabling SOC_BUS for the SoC revision
information. Also enable few HW errata workarounds for omap4.
* tag 'omap-for-v3.10/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (236 commits)
ARM: OMAP4: Enable fix for Cortex-A9 erratas
ARM: OMAP2+: Export SoC information to userspace
ARM: OMAP2+: SoC name and revision unification
ARM: OMAP2+: Move common part of late init into common function
Includes an update to Linux 3.9-rc6
Conflicts:
arch/arm/mach-omap2/cclock44xx_data.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch includes major development on the core Tegra SoC support code
in the mach-tegra directory:
* SMP support for Tegra114.
* Exposes SoC chip ID and revision through standard sysfs files.
* System-level suspend/resume for Tegra20/30. At present, this only
supports "LP2" mode (CPU power-down), but provides the basis to
implement "LP0"/"LP1" (various levels of core/chip power-down) in the
hopefully near future.
* A minor cleanup of a duplicate include, which was introduced in this
branch.
This branch is based on the previous cleanup pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXvvtAAoJEMzrak5tbycxwdAP/ioto6+ekXniT3/Iqx9CmqG4
kDwS6LKn8Y91ePH6R8i23U98PjLwo/HgRWSTLjfwLMAi3AOEgsJ+bUnCmPAszxkY
Ayyv+SLbgYaR817ezACXKH0tJHF1yo07bwk76jXQwo9/d71wg8sLweQwuEA1p/u8
ZlMniF731p7oZCNcoK680eFsurTO850GTfCrBowmOiGcPgpbllTEifwRthzQNhD7
b0Yw55rTqz9gbhgYCN33Va6CzwD9CMaxKN28J6qPJ+j7JCXO5Qp2QCuQ5PxLTbGq
g1n65h2p5eXQwJwnf70jGuvF9xjdPO0zNTbQVP/hkrRMpB9VA0Z6zw0s12c1H70l
Hs/7Hn7IBzCf5jdn802knc0K0b3Q7MhUjfTU6Gmj2KWJ+SfjMQtfqRdTWKsmPXXU
3MVxlJnqHNCjttWXXkxN0lKSgdi5HN431RwD6P9i0NPIq9RKZutw4jFeNLclVuGa
xZMBtdDZ/U2KwL0aITkleacMHcb5/pK1z626//rB2CWRSRtVLGgye14FyEBi1U+I
EdA16bu9U6MiwlqT0I849pXFb3l0di0+FTVadE+D3aJGjk/IWond0Fk1VayaSCX0
X8SNUByRPtwhJRQH+oX+HDZXWW6gc2cixpYSoDmgdSXSJLBuLlAD+KPAXi2hvTUf
REyjYXwVXVyMY/XTz5fP
=1KXE
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: core SoC support development
This branch includes major development on the core Tegra SoC support code
in the mach-tegra directory:
* SMP support for Tegra114.
* Exposes SoC chip ID and revision through standard sysfs files.
* System-level suspend/resume for Tegra20/30. At present, this only
supports "LP2" mode (CPU power-down), but provides the basis to
implement "LP0"/"LP1" (various levels of core/chip power-down) in the
hopefully near future.
* A minor cleanup of a duplicate include, which was introduced in this
branch.
This branch is based on the previous cleanup pull request.
* tag 'tegra-for-3.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: pm: remove duplicated include from pm.c
ARM: tegra: cpuidle: remove redundant parameters for powered-down mode
ARM: tegra: pm: add platform suspend support
ARM: dt: tegra: add bindings of power management configurations for PMC
ARM: tegra: irq: add wake up handling
gpio: tegra: add gpio wakeup source handling
ARM: tegra: moving the CPU power timer function to PMC driver
ARM: tegra: add clock source of PMC to device trees
ARM: tegra: add speedo-based process id for Tegra114
ARM: tegra: expose chip ID and revision
ARM: tegra: bring up secondary CPU for Tegra114
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* It enables the multiplatform build for mach-mxs platform.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRYoD8AAoJEFBXWFqHsHzOM40H/iwJ8kf/xWXrSKstVwszLV/U
Q0hCvUQ0lp+IvywJi+yDD+X/TCFE4lDGY0nDo5ucQouMtfVUk1DfZEjFCYQRN4q8
32fqQbeBGKwMd0I2f/jCiRRfZlWmpYU6x1j+sFNpJmjUoD92cVByjOQzFvrO9SSM
LasJUAs9ujDTXfc+/eekG8PCeCweE0cZaKJtingyEF+Ri5kNEnF/1ZmadVuVukgY
8pND1jYVTOfhdyBgYFhJIFK1xuaGX5CjJTokn86Ue8d6VqPAA/q2eD1PdHkIKZ39
erOwCuizplU8Nce9cJpAQDz73I4Cxs2qG8UPcqErvLhZNttOw52pYPvhXZXojG8=
=IJY6
-----END PGP SIGNATURE-----
Merge tag 'mxs-multiplatform-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/multiplatform
From Shawn Guo <shawn.guo@linaro.org>:
The mxs multiplatform support for 3.10:
* It enables the multiplatform build for mach-mxs platform.
* tag 'mxs-multiplatform-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: enable multiplatform build
ARM: mxs: rename debug-macro.S for multiplatform build
ARM: mxs: call mxs_pm_init() as a machine_desc hook
Conflicts:
arch/arm/Kconfig.debug
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Linus Walleij <linus.walleij@linaro.org>:
Ux500 multiplatform support. This tag builds upon the MFD-specific base
tag "ux500-multiplatform-mfd". This removes all <mach/*> dependencies
and makes the ux500 fully multi-platform.
* tag 'ux500-multiplatform-asoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: build hotplug.o for ARMv7-a
ARM: ux500: move to multiplatform
ARM: ux500: make remaining headers local
ARM: ux500: make irqs.h local to platform
ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
staging: ste_rmi4: kill platform_data hack
ARM: ux500: move mach/msp.h to <linux/platform_data/*>
clk: ux500: pass clock base adresses in init call
ARM: ux500: make debug macro stand-alone
ARM: ux500: move debugmacro to debug includes
ARM: ux500: split out prcmu initialization
mfd: db8500-prcmu: drop unused includes
ARM: ux500: move PM-related PRCMU functions to machine
mfd: db8500-prcmu: get base address from resource
mfd: prcmu: pass a base and size with the early initcall
Conflicts:
arch/arm/Kconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Clean up timer code and move it into drivers/clocksource
* Clean up icoll code and move it into drivers/irqchip
* Clean up clock code to not include <mach/*> headers
* Clean up rtc-stmp3xxx, mxs-lradc and mxs-saif to not include <mach/*>
headers
* Clean up mach-mxs code to get it prepared for multiplatform support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRYnwxAAoJEFBXWFqHsHzOs34H/iSLBv6I+f6oPubu52kJz6fP
ctZPm6ZJPUKIiyVLLcmMf9kMr3h0wWH3XOBDzPdSj0Wtyb+rbpb/qa0jOg2EwZOs
2g+7LpehX2BgqKzdBPQEBC94NuU81F0X7SDZe0YechEWZY1VBGjaDnPso+Ugs23A
7hpjRHAOjd8gnJvkqU/uLKkbJiRX/pvXDcxkRhu15HsA9v6m18Elpq4FNw1QccLd
06o2M8aVvSL4IYy4Eh8lheUZrPNuyapG3TTjzhbYlPZtvXijFEFWniAQWyq5eGdg
3aiVbv3lCWYyJzFhmv9n6WYGqHthpnxej9ZMsREa1OVjmViDzSTda6vlhJvBOHQ=
=neCB
-----END PGP SIGNATURE-----
Merge tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup
From Shawn Guo <shawn.guo@linaro.org>:
The mxs cleanup for 3.10:
* Clean up timer code and move it into drivers/clocksource
* Clean up icoll code and move it into drivers/irqchip
* Clean up clock code to not include <mach/*> headers
* Clean up rtc-stmp3xxx, mxs-lradc and mxs-saif to not include <mach/*>
headers
* Clean up mach-mxs code to get it prepared for multiplatform support
* tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (26 commits)
clocksource: mxs_timer: Add semicolon at end of line
ARM: mxs: remove unused headers
ARM: mxs: merge imx23 and imx28 into one machine_desc
ARM: mxs: remove common.h
ARM: mxs: move mxs_get_ocotp() into mach-mxs.c
ARM: mxs: remove mm.c
ARM: mxs: use debug_ll_io_init for low-level debug
ARM: mxs: get ocotp base address from device tree
ARM: mxs: remove system.c
ARM: mxs: get reset address from device tree
ARM: mxs: remove empty hardware.h
ASoC: mxs-saif: remove mach header inclusion
iio: mxs-lradc: remove unneeded mach header inclusion
rtc: stmp3xxx: use stmp_reset_block() instead
clk: mxs: remove the use of mach level IO accessor
clk: mxs: get base address from device tree
ARM: mxs: remove unneeded mach-types.h inclusion
ARM: mxs: move icoll driver into drivers/irqchip
ARM: mxs: call stmp_reset_block() in icoll
ARM: mxs: get icoll base address from device tree
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJRWLTrAAoJEHm+PkMAQRiGe8oH/iMy48mecVWvxVZn74Tx3Cef
xmW/PnAIj28EhSPqK49N/Ow6AfQToFKf7AP0ge20KAf5teTq95AY+tH74DAANt8F
BjKXXTZiR5xwBvRkq7CR5wDcCvEcBAAz8fgTEd6SEDB2d2VXFf5eKdKUqt1avTCh
Z6Hup5kuwX+ddtwY2DCBXtp2n6fL0Rm5yLzY1A3OOBye1E7VyLTF7M5BR603Q44P
4kRLxn8+R7jy3hTuZIhAeoS8TKUoBwVk7DmKxEzrhTHZVOmvwE9lEHybRnIyOpd/
k1JnbRbiPsLsCVFOn10SQkGDAIk00lro3tuWP2C1ljERiD/OOh5Ui9nXYAhMkbI=
=q15K
-----END PGP SIGNATURE-----
Merge tag 'v3.9-rc5' into next/cleanup
This is a dependency for the mxs/cleanup branch.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch includes various cleanup of the core Tegra support.
* Unification of the separate board-dt-tegra*.c files into a single
tegra.c, now that everything is DT-driven and basically identical.
* Use of_clk_get() in the Tegra clocksource driver so that clocks are
described in DT rather than hard-coding clock names.
* Some cleanup of the PMC-related code, with the aim that the PMC
"driver" contains more of the code that touches PMC registers, rather
than spreading PMC register accesses through other files.
* Conversion of the "PMC" driver to acquire resources describe in device
tree rather than hard-coding them.
* Use of common code for the CPU sleep TLB invalidation.
This branch is based on the previous fixes pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXvqoAAoJEMzrak5tbycx4C0P/R6urrFPiYsPgith5+dpP6zv
duAIAt0+chtEjva0veewQsBneRtTVNU115FQ/QZaMjSszAuIjC7nRa2iBa88FX1+
pzQYmRUrIupjeQ1WxxKYOILDXrMJNejbgoLu7kcHzWDEGsJmnwNh8kmiklvIJpa8
UDpz7RWhr6aWzrmiwj1cPF1/NJBl1nbx/TZCUo1u8yq46C9oVUi3DCdAnDVEsAzA
vJaNSVWxeBOytd0jlLOiDAYtlrCtysCt/x7YjnN+9x7r99pzXHd0FOPOkKWBrOAN
TOk+bhyXMFkucEk229A8xRYxhRynYecqYl48kF6Wt7HssrUJptk4qXZTZeDIyvZS
33YCRDjCJSrCkHjgDIVddtiz4+iZs6D7f/p9lZ+ikLfTyNXf0a+Wo5zRRyrrYJ2J
Is4ZW0U3lvF4XmbNQRW3RhIGINSRhEY4POqygjO5h4fw7uAESAV3Pd3z/e59tMQi
Dh3A1f+yIXDwYQmyN/nFVTjFcFPlCD6BW9G/u+R/5YkPSmGqw8cUUw4BlO244wHL
NVF7VQBjtkELYPPsHnp6Pp+aJ0uxmmGcSNM56RHZERiMZlz1lv5CwT6b/6PqFEu6
IpXsAhV5SRvX+6Ky5mtb8A6JdNA6EuwVol3nmaNqFlbqHcR1HHyAsgCiTDkwkGYE
Ggk40fKiWRcras9gRJI+
=3GM9
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/cleanup
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: cleanup
This branch includes various cleanup of the core Tegra support.
* Unification of the separate board-dt-tegra*.c files into a single
tegra.c, now that everything is DT-driven and basically identical.
* Use of_clk_get() in the Tegra clocksource driver so that clocks are
described in DT rather than hard-coding clock names.
* Some cleanup of the PMC-related code, with the aim that the PMC
"driver" contains more of the code that touches PMC registers, rather
than spreading PMC register accesses through other files.
* Conversion of the "PMC" driver to acquire resources describe in device
tree rather than hard-coding them.
* Use of common code for the CPU sleep TLB invalidation.
This branch is based on the previous fixes pull request.
* tag 'tegra-for-3.10-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: use setup_mm_for_reboot rather than explicit pgd switch
ARM: tegra: replace the CPU power on function with PMC call
ARM: tegra: pmc: add power on function for secondary CPUs
ARM: tegra: pmc: convert PMC driver to support DT only
ARM: tegra: fix the PMC compatible string in DT
ARM: tegra: pmc: add specific compatible DT string for Tegra30 and Tegra114
ARM: tegra: refactor tegra{20,30}_boot_secondary
clocksource: tegra: move to of_clk_get
ARM: tegra: Unify Device tree board files
ARM: tegra: Rename board-dt-tegra20.c to tegra.c
ARM: tegra: Unify tegra{20,30,114}_init_early()
Conflicts:
drivers/clocksource/tegra20_timer.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
OMAP PM fixes for v3.10
Note that this has a dependency to omap-for-v3.10/cleanup-v2-signed.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRYvfIAAoJEBvUPslcq6VzqJ4QAOIK3KFoxO+Of0f86Y5P598q
tp91sQbXPzMW7MzawJ/YR0K9bX25vam5k6wuh8VnF6xQBfeF0jKBEKE5ksZbratM
jrA2Xz52iHtNaCPE44AdbyRLZSV8wl60cpOIAF5ymLZuGQ2ZJYgJvLQqY7wffMTd
T/S6EfJxz7r2cvlHeSJsDkVmovime7Zw0rj6AO2G4F62djQvL+BvOTkpva4aFH/e
sH43RTnqA3qxlXYfoxFHam2kgTr6A2N44hoddS5MV3IuSannsz9Jiuj2kBxyWmh0
/UHyonHRPDMQmWrYKEZnTkV05pLCZhC3KM/84y+im/jND2Q+zkamrKyaOPo2ZORt
sP5ZksBJyr4S/FmSdXCjtmbfrwhAcwC2btt+Vp8747O7ccnipWe5QA54rMuLbaiq
Kw7qYwrPPgmyX2umlCsYH5LeaZW+sK19cAAQcXVUf87z+LmCPD7HbN2oXDY9sR7c
zNPjY0GJLG2IKyLfIAFwpzE32I2Ld1KAj2owtE2qU4E/94Me3f+SBnFq38cpZyDd
WnvXh1OY5K++7VkBKAIcyEJ007BzK0plJYCifVAkPkoPFS1Y1SxKtYfTbdeV56hj
8JuxRu45gOc/pn3VPuRyNOT6BRhEZtI5NP13Bq1koBlz29mGCCb+E33rbp331nhm
GPokhwSA2USvDP8hgf1B
=qEVL
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/fixes-pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren <tony@atomide.com>:
Non-critical PM fix via Kevin Hilman <khilman@linaro.org>:
OMAP PM fixes for v3.10
Note that this has a dependency to omap-for-v3.10/cleanup-v2-signed.
* tag 'omap-for-v3.10/fixes-pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method
Signed-off-by: Arnd Bergmann <arnd@arndb.de<
This branch contains a variety of small build and run-time fixes that
weren't important enough for 3.9.
* Enable CPU errata WARs in secondary reset handler as a preparation
for multi-platform support, and a related fix.
* Don't touch DBLGAR in reset/resume handlers, so enable the code to
run on A15 cores.
* Minor build fixes.
* A fix to the Tegra clock driver.
* Some error-handling fixes.
This branch is based on the previous fixes-for-mmc pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXvmIAAoJEMzrak5tbycx+YkP/1cnb3ushPA1/7xG+NzOMv/e
eTx1FUL6yt0D5bSUFwFJ7YIlbnYyunGGY+hUfLWe1NjRWnDmLxM4ACOjDUqRoYc6
GjGG+66okOZOj2MlOxmvLYcKUW7L9LSz+GWqP2NVsGUlwsXb1M4UhX0tmKn6dqeg
P7o5zTysbLruFrmwWr1eT4Jugz286fN5cSyVZvMrSf7GZ25k4h2f9AvPvaSDrFNH
syOokOll1S5cpS7s95yiV4ANn8jT+5xGDNyukiiYLiCb/xq2lDIfDtZEKCk5Uh8D
QLB3Rbt3NQNeeQLvY8ARJcDjz4/pFYARk0LUU6y3MoP6pem+/usOxI1Xte3Luw+G
X0YHJjUN3kR1XIVKiwBPZhEN+FYg8jk2omUPUsiUptTHXBTrjbjghbcXL+/rk2FK
hspdyPD3KzcRus7cKjzXwGNFI9rkz9nqcO98YjnJzMrhopDWVOd+uE8qxcsGXKJW
tR+/rSgPZLCWsX+gAiEigIiZv+CiB57cVS6pD6NDy9SYV9Ax1xiYcSS8g5zOOlQE
KD+rCMFsVxJRZuiNeKVnj/qamytRGiNgmdZxG59KSWNqs9uPp9o3pGeNjaLeUcAw
pg7bYCeV7bcckNuL4FljdfT6rzLPuQIM52saCdQ26PZjOnI/sJdbWt9RqZhJ8wUc
cOB9LPyUUxJkhOGW+c32
=5rB4
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/fixes-non-critical
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: minor fixes
This branch contains a variety of small build and run-time fixes that
weren't important enough for 3.9.
* Enable CPU errata WARs in secondary reset handler as a preparation
for multi-platform support, and a related fix.
* Don't touch DBLGAR in reset/resume handlers, so enable the code to
run on A15 cores.
* Minor build fixes.
* A fix to the Tegra clock driver.
* Some error-handling fixes.
This branch is based on the previous fixes-for-mmc pull request.
* tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: powergate: Don't error out if new state == old state
ARM: tegra: Export tegra_powergate_sequence_power_up()
memory: tegra30: Fix build error w/o PM
ARM: tegra: fix ignored return value of regulator_enable
ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs
ARM: tegra: Fix unchecked return value
ARM: tegra: don't unlock MMIO access to DBGLAR
clk: tegra: No 7.1 super clk dividers on Tegra20
ARM: tegra: remove save/restore of CPU diag register
ARM: tegra: add CPU errata WARs to Tegra reset handler
ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The i.MX53 ahci platform support is unused in mainline. To demotivate
people using it just remove it from the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* A couple imx35 clock fixes for regressions caused by common clock
framework conversion. The admux and iomux get disabled by common
clock framework late initcall, and hence causes problems.
* Add missing twd clock lookup in device tree. This becomes required
since commit bd60345 (ARM: use device tree to get smp_twd clock)
forces all DT boot to find lookup from device tree.
* Fix imx6q ldb_di clock parents mismatch per reference manual.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRZAZBAAoJEFBXWFqHsHzOy60H/0RIxFO1TSQVVPTuJRtHr9qk
BtszcLOwiRbWipuG1OiosEKXMeOXjAPtOG8P9tReC/oJN4WL5CmGW3PrPQ/9DEbZ
OTYVPhgmGKDB/2n5BVvvTDISTovvlQRju4ht+70j1BnAlpbzGLbKMG4o6zHOROoh
d15dqg/Ny1ovsCvva2ODbwRtBkBaBqDC+RGqNPrhTN7WSk+nv6yITYZCREI1mjGH
RG7B62hn+1aD6tMdigFu9xS4vTkHXjFC0AVEixBEi3iWqofSz3Cb6Zq4MpRGNXGZ
o/tfc4/2q6uF/UEpTQJDhYbHjwesySsIwdu4vsvI2lh9EGqUgyC3YE+VbDwOeGE=
=tztW
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-3.9-5' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
From Shawn Guo <shawn.guo@linaro.org>:
The imx fixes for 3.9, take 5:
* A couple imx35 clock fixes for regressions caused by common clock
framework conversion. The admux and iomux get disabled by common
clock framework late initcall, and hence causes problems.
* Add missing twd clock lookup in device tree. This becomes required
since commit bd60345 (ARM: use device tree to get smp_twd clock)
forces all DT boot to find lookup from device tree.
* Fix imx6q ldb_di clock parents mismatch per reference manual.
* tag 'imx-fixes-3.9-5' of git://git.linaro.org/people/shawnguo/linux-2.6: (217 commits)
ARM i.MX6: Fix ldb_di clock selection
ARM: imx: provide twd clock lookup from device tree
ARM: imx35 Bugfix admux clock
ARM: clk-imx35: Bugfix iomux clock
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add SMSC ethernet support to the bockw board.
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-r8a7778-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-boards3-for-v3.10
The reason for merging with renesas-soc-r8a7778-for-v3.10 is
to provide pre-requisite SoC code to configure IRQ pins for the
SMSC ethernet.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXjzZAAoJENfPZGlqN0++PfsP+wXKEGnS47efqfh/wgNQTiJP
bc7ottBOfXkiLhz1NB3LMw1c9mNF+n57wetiED9l0BR8gwGi7X6Fespa024lIp32
Sw/FSHnAdUwB7MD+uQUrDeN2+UUplR+0aSY7vmcAQ7XHbuytB1BylQrA2sxQA1NY
O27J5s6IjZNWSX2FzUPmEygDhUcikkAPbC6IfmfEIJPoLJ9Li6NePsuPc2sXokby
kJkbqhnL20Ja9Vv8aKuSJO/4IYQHCkk0jAvaJRDctlWHMlPEBqsx7DXFRSmzTc7F
Wm4uySM1VrVpCoGDkQtd+zbatVJOOuKzq0kN5g0LDe73hpHrQx8pJyFdZtxPD9BA
ctm3E+p6Wx8Zna2WtQgsNRjkRPCz5kcwqCdmnCLykOTtxs8lwnRUn3nN3qL0R+uu
KeIRsxwgL9O67FyrZk4WW9On0Qob2vd66ktCF12FCTlX3vYIQR0vFAQ8VlF2OeZl
S2VJ6+FM8N5jUzDFoOzYTUOXcskomUxPop93HbRDho/bgLhOba9cD9tSep/4p7ZZ
s4oz20WSBUvszK7He8kGiTn8vwR/1mEwQPyP1eZh/hSxWGxdqdTQ5ZcT4IA0Hbe9
CFZ9qiRBzOjBhDEgYmKYo3BN9Yk7WVB9ILWa7xsD05yskcaA+ps/Om0/81i75iCx
n1PDVuc/A9H1F5REQaM7
=kjpJ
-----END PGP SIGNATURE-----
Merge tag 'renesas-boards-bockw-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2
From Simon Horman <horms+renesas@verge.net.au>:
Renesas ARM-based SoC bockw board updates for v3.10
Add SMSC ethernet support to the bockw board.
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-r8a7778-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-boards3-for-v3.10
The reason for merging with renesas-soc-r8a7778-for-v3.10 is
to provide pre-requisite SoC code to configure IRQ pins for the
SMSC ethernet.
* tag 'renesas-boards-bockw-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: bockw: enable network settings on bootargs
ARM: shmobile: bockw: add SMSC ethernet support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Update to the r8a7778 SoC:
* Add SH Ethernet support
* Add r8a7778_init_irq_extpin() to allow configuration of IRQ0 - IRQ3
- This is a requirement for SMSC ethernet support
* Cleanup: remove PLATFORM_INFO macro
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXj6zAAoJENfPZGlqN0++b5UP+gJlCY6SfXKCBvITT5vkTzG5
UIkxR8YrhxVGjZJ5vdpe1rbf9/mVtXMM+NOvIpLss0+qNDi5pnIl2ghifj2hYzB9
k2jwULUcvXcgiuaoSLDII/ClvYPatEy2Ld0FQmz3RKk3h9E2CdGepsYBpbQKRoYT
ZSDzBWq/pjGMI7kTacCtGyh81xKWB+hZCQkD4eiPG9vcnYU1Al6JqaNe506L5mBG
WjLPFZaAs9yXBbGEYZtdGD8s9qZQnKUoPjRLaBSWDtkc7CdvpP4GTCCFRgOKCQ3Z
WHexhxzde9lp85oOvk9X+PQ6Q65CNHBa9Rl+P71/viURNANLeO0cfQusJ6NmqnDa
1OYo9b7LGTvPTbKO/9A6GyCP8oX4ZJuDUMxSSUvdkWyM8TV23st4JneHS5bjWAj4
GRJ4Fevq1qMioAle0HUOGCZMgAbmjiXwfWvh7RVBa2RcJziKjZH2zJxQX+LdKUWV
xcnNkDFNK2YVn5l15JD+5xbKNiZx2YWTFcaLR5mSAjg10ppJonEWPtvPxq82PkGF
KQq3HF9Pykgpt3BT8BZQtvLqwHV6qac0dLTqvJUdtNj2cvABuFjQS79xu0pXkvy6
GDBmMyyLMiMECPHHzV7PDqSfrU+MYNbglIJ3U9HYs20rRvK4BgKXVuGVFjoVJtZE
ttIn1kNxwuKI7kJcPq2d
=ih3D
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-r8a7778-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
From Simon Horman <horms+renesas@verge.net.au>:
Renesas ARM r8a7778 SoC update for v3.10
Update to the r8a7778 SoC:
* Add SH Ethernet support
* Add r8a7778_init_irq_extpin() to allow configuration of IRQ0 - IRQ3
- This is a requirement for SMSC ethernet support
* Cleanup: remove PLATFORM_INFO macro
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
* tag 'renesas-soc-r8a7778-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R8A7778: add Ether support
ARM: shmobile: r8a7778: add r8a7778_init_irq_extpin()
ARM: shmobile: r8a7778: remove pointless PLATFORM_INFO()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Update to the r8a7779 SoC:
* Add SH Ethernet support
* Add comment describing clock ratios
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXjspAAoJENfPZGlqN0++hK8P/1IPQUnrKWrySDJmDjgMVd6P
yayOvZ5OAAHuhzvON+gkIk1VZ2Ic6fLcE0rPwTU+2WWjRfQ7Be7TRED73Ukl+/oN
AOsUkOuuxILit/XQ+6LnMqFJMCz18Y6ZIQc9qgselMUVplNcYsDeHC1sawS9mBdi
B13WPQU2mEEWhso7JLgNiIdLauf74N74hnzRDK6Xml7dOTgUBnH6QEOL7gud4jqP
ymaauSfdkI58/swZY4DtIbnnchiVmrg4doTa1tdpaCQORYACTD1ahJaEfBxuScjy
WK1O8XBDzYPVYhcVMXzu/PSKTkHtb+SJWVz81OthhNX4PFzk9bQuVXWqWz9kEiEY
PFFRuPM8SMLFajtjsDVfj2EWUhbRagoAAIHKfL+yaDUXFGWwwOrRuoHKHtegx53o
ArMwkYTDcD3UfHZhlVabtvG2Y/DabowYStamZjjtDP9pFERIvhXcZVaw8kcNZxpC
ysj6bsA4lazoIa2v0g68TJSjxPPhzCgjJB+VcTE8Coe+voyP27CQwbMelFzyDl/z
Grfi13UCly29MtqLH85txD3J4k40OCrKinnrblxk6RQBVRkHezMT5YLIVrdSu4FI
oub/dsZi2scCHRb/5vS4/4sQIcoknDhE/0s5d1V51N6cu2AxspBRI/kbziDhQa9j
X1jSjcp+/sbOkHq9y85H
=YyOX
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-r8a7779-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
From Simon Horman <horms+renesas@verge.net.au>:
Renesas ARM r8a7779 SoC update for v3.10
Update to the r8a7779 SoC:
* Add SH Ethernet support
* Add comment describing clock ratios
This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
* tag 'renesas-soc-r8a7779-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R8A7779: add Ether support
ARM: shmobile: r8a7779: add each clocks ratio on comment area
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Use the r8a7790 timer init function on Lager
to make sure the architected timer is started
regardless of boot loader setting.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Implement a SoC-specific timer init function for
r8a7790 that makes sure the architected timer
is started regardless of boot loader setting.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
An AT91 SoC that doesn't have a subtype is shown as "Unknown"
in the Linux log message which is not correct.
This was leading to confusion so, add a "none" qualifier to
the subtype property and set this one in the appropriate cases.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
much all non-critical fixes for platform device initialization
that will be needed until we can drop the board-*.c files and
move to DT based boot.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRY2tiAAoJEBvUPslcq6VzzHwQALjHkeE6SRWQ1SKn9tR83Hg0
UtJZHjF1Fuw8VSoAuZUd19bYMNVJ356KEowSvt3nJXGOveVD36Si8AuyPcU2z0Cl
aHOm70gt8VbfVO8oM0F8BoaDBd9+6p7RGrcOUI+7jRxm+Cgc02tsHbQXtINMgL1f
HmdOS4GtmacaLpbg2MtRIkxwqpas+s73MyUSP03vhzpcyBZZTwxDLt/EOXksBVzJ
jLocMhBGIVU1HET9ZVG1w7+kLwy+X6UKkfZ7Ju9n5dJkuoRFp+sngRvYQk86r0v3
pXAAkeleQulKKq2tKClrdPFS73pw/nq/OHDOggtXisKcBpHstwxWGglh9vnACAj1
XJNadOda05BkS2K0Ft4CdgXjbT78wKuFxYnavDCLXoniAo3S7F9rGxLeSW2BIbKh
FPourql3Om2kVvp2YjjsH2TU1gBL1d7t31hJRGfU2nypobvZUoMScy3O3kDB9exo
hGfoXesRsyAR9WFi4qdaMuCi55hScLvwFS8ZuGw+1KJvPmekI3Qew2eQ6zPhIogz
iNbW4nm4nBFcymIf6Dsu5mEqTyAlBcMbALouAFUDmyj+6MBGd7t9QbPe4nAZQlbA
CO34dxrvJ4QNMsTPRTTIzoA3gJJsEGdcCnrz8HNWRPcYmczNwuSv1mOG3O0HtYi7
PQMUN5YtmuOJeZJu43V2
=g9O/
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/boards
From Tony Lindgren <tony@atomide.com>:
Board related changes for v3.10 merge window. These are pretty
much all non-critical fixes for platform device initialization
that will be needed until we can drop the board-*.c files and
move to DT based boot.
* tag 'omap-for-v3.10/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: board-4430sdp: Provide regulator to pwm-backlight
ARM: OMAP: zoom: Use pwm stack for lcd and keyboard backlight
ARM: OMAP2+: omap2plus_defconfig: Add support for BMP085 pressure sensor
omap2+: Remove useless Makefile line
omap2+: Remove useless Makefile line
ARM: OMAP: RX-51: add missing regulator supply definitions for lis3lv02d
ARM: OMAP1: fix omap_udc registration
Includes an update to Linux 3.9-rc6
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This pull request enables CGROUPS in defconfig and also
cleans up mach-davinci to use IS_ENABLED() macro.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRXpcEAAoJEGFBu2jqvgRNzlwP/0hSxiwf4hWThIZZ8TFIbTEu
8utRWToiBZHYknw//kfrvxXShT4nZmKluRt89zdjfs+7zPilV16V+d7kNy57jDn9
81iOul655bkn0p5VJqlVWErA5Uz6KGCdFEYj4i4KFEictG3OhjQKLaQPi0//kX4s
NCO4OBY0+N9qdwrbiLowDsRt20Zm+FJ0udvjB6c/pNGG/3/hvIPqmSFQUVK1AvKr
oMbH+vewgq6Pqq4MisvoxXogZVctRAPq0U7ju54GHVp9NadJjMjleADeT6WAERUR
Qstz4d/lr9ArtEY5tgIda6VLAaoulUZK8aYcpce5cb93f+vr7mPSwqbCVKHruJGy
S+YQ4c6ZPbxKgaazTGsNMYXO0XPD2Y7QNw4molDFFkOLmFzvaI1ACCaTRk9avL9I
+Ye8mBPQoW6nebC7wIqsJ/iWNmDB5+uoy/seAGLAqhdmMsTSlPa9NMej53Nzxi8f
mf+4p/1XcNhQTg53TtrpIEipPZExLyBoXPS5NIMDagmIJZQKhoBUrQJ3MzPVDDaR
LKe1MXVBcu+PL05r19iXmTV8vlCG54tjtNeg+iEHO4YjvZod9QlTQElghtlEqx6y
KEoq9OjtKqTveOT6SwaV1UBijDNZGZ8ZfrPfKkLCmfL1izWzDePhxyYdUZiHOnnx
nUxk5qW5ZoilRmzOvvoZ
=JE9w
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v3.10/board' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/boards
From Sekhar Nori <nsekhar@ti.com>:
v3.10 board updates for DaVinci
This pull request enables CGROUPS in defconfig and also
cleans up mach-davinci to use IS_ENABLED() macro.
* tag 'davinci-for-v3.10/board' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: use is IS_ENABLED macro
ARM: davinci: defconfig: enable CGROUPS
Includes an update to v3.9-rc3
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
clock is named 'pll3_usb_otg', select this instead of the 540M clock.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver. However, the commit
bd60345 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree. It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.
smp_twd: clock not found -2
...
Calibrating local timer... 396.13MHz.
Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The admux clock seems to be the audmux clock as tests show. audmux does
not work without this clock enabled. Currently imx35 does not register a
clock device for audmux. This patch adds this registration. imx-audmux
driver already handles a clock device, so no changes are necessary
there.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch enables iomuxc_gate clock. It is necessary to be able to
reconfigure iomux pads. Without this clock enabled, the
clk_disable_unused function will disable this clock and the iomux pads
are not configurable anymore. This happens at every boot. After a reboot
(watchdog system reset) the clock is not enabled again, so all iomux pad
reconfigurations in boot code are without effect.
The iomux pads should be always configurable, so this patch always
enables it.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The pull request adds support for MMC/SD and regulator on DA850 EVM.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRXo/nAAoJEGFBu2jqvgRNfZwQAIOLsozvHuxHM6l3sv2YDwuV
8l65WiDq2UgXaobseX59U1+LfrGDaxO03kmIorViGuNKlx534Veuxhm6pOr+phjp
sf82BQLLDzJem6F04Cx3GxV9yx2kvvfRF/4mP+in1i08t7sQNmh/mVTpdTxETEQZ
dBEg7ev23ZEDPDBtF/HE1QdIae/HsZWyZATA3WH0tUWfER9BZdkSihP7rjSb7Rq5
qJAJ33xJSlIRfW4qImK0fsoMQKhOKpUnAYHpjo89JD4UBXgahyMz4fvfxoVp6Xqa
Qrl2ZenllrSbOmPxjH+IB6VecjdV3sHGt2aI3IOFTUomfe7gR9vfjPztal/Al/S8
HRCTRDZjcMc4KHATIKlU3jjpV48XZV5wHbdjgIK9LocneTkxYvp+wQxQZ9/0mfu+
1FlRYqXqNezdZoVaZaLAGe7/FNN8ws1f3k/O4K5tM5FwZWFDUJY5DXyBY7Y6f0XZ
FCAJLWYZm7rwemEeWFNyfFr+rN19hcAmbFmZcUV1oDIqwKZnQFvxl6omVREqKQKm
3freTqlHJudDnj7xiub9zYMJpq7TVcDoRVZPnwpcLP1RtCMS6Q0sbcA5zH/VUyKR
2TJpS3y22p0FpJ7/O+855CPzZhU4UmYrUEMYMpW2dVMk36ug+uYsbIb2vbSR+4iA
/On32FUq+k1GCypzjp7d
=OjvJ
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v3.10/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
From Sekhar Nori <nsekhar@ti.com>:
v3.10 DT updates for DaVinci
The pull request adds support for MMC/SD and regulator on DA850 EVM.
* tag 'davinci-for-v3.10/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: da850: override mmc DT node device name
ARM: davinci: da850: add mmc DT entries
mmc: davinci_mmc: add DT support
ARM: davinci: da850: add tps6507x regulator DT data
ARM: regulator: add tps6507x device tree data
Merged into soc branch rather than DT branch to avoid circular dependencies.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
a) adds support for eHRPWM clocks
b) Fix the way MMC/SD IP versions are communicated to driver
in preparation for DT support
c) Minor cleanup in debug-macro.S
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRXo7QAAoJEGFBu2jqvgRNUBkP/j+KK++y1bqg9NXWP/iESJfB
H1Hu15zPVkHxLl7xVUTVFI69+XX8o1+rNF/QV9o6yeOJKY33Te/1JLFZO1LVDiCb
xnruNai8ymEiezMFYEwrNfGd5slcSJYOkRl1rCNjp2wp3Da40SToVHKdtVBosQAd
uBYndQOTutLFhmqHmuKovG5DNu2UJ3ZZ4u+/ejoqaqqJiwhdbkonwKiZPl6xiyMt
QsKxVXhchwIbg8NdmbpQcICbxqEgtdtXfFv5Vw4ZvhRWrPNCu9GI/vYpKQd318NZ
bs3BNlml5JB2H7UcuvghcVHqHw2lz8llSCknUZ5LAk5msK2s9/S8gvKZyjkbtiBX
REq741XxFYu5e7eh4m6Yn7+R30Th/lNfqeOG0T8k9vhCenfno8rOhPQhVu8M3bL7
6BrkK+1rBryBCEiduUL3rcDWHeIFLbbejikPOrmUFbd5zykfttID6SW2kSxdxVzr
nk5FiJOdbbQDDhE+90lahiHJ+SL29y4xsrpo57NK3+W8ZGhDK4OlTKf0B7dVpisB
5KuDaHgHNmhcuJVYIkVuY3aqsrLRlyRaMxS5QJoE6cWqwURw4RQGmvk4NngMKvGD
VKzn7c8dxo7y8W3NAgHIwfbYdGqsIrwnextjEwTUbWfIFQfvyfeEuZ37jhvxNVNn
fTcypX9bNcvjW9NfhDYV
=ABW/
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v3.10/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
From Sekhar Nori <nsekhar@ti.com>:
v3.10 SoC updates for DaVinci
a) adds support for eHRPWM clocks
b) Fix the way MMC/SD IP versions are communicated to driver
in preparation for DT support
c) Minor cleanup in debug-macro.S
* tag 'davinci-for-v3.10/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: remove test for undefined Kconfig macro
ARM: davinci: mmc: derive version information from device name
ARM: davinci: da850: add ECAP & EHRPWM clock nodes
ARM: davinci: clk framework support for enable/disable functionality
Includes an update to Linux 3.9-rc5
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
In order to convert the Tegra MMC driver to using mmc_of_parse(), some
bugs in the Tegra device-tree content need to be fixed first; it's
currently wrong but unused, and mmc_of_parse() causes that data to be
used for the first time.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRPkD/AAoJEMzrak5tbycxoFAQAJMd6F58+cCTt7V6d57sfaiT
E4kun2nLI5qpFErLb2ehhoWkFJJ/6WQ3ytoqFBQY4UKVwp0gFhuC5od9gKgTcVuu
8OeH0nPr0RDasHZ4yYm8eFM1GwrMYRda5Xfs9OuLBSi/twNcHNplhjptCJgZ6iGD
i2MBheIY9K3sYsRCxcOF8doUFrjHhxUS9fyfipHZ+zfoWeqcQ2LTy1j1ATjT+C5u
QhpBptOqRvYHTWfTY8wLZ49h+OHHMMU1NDlEPVXfg83CyhfU+A1qqfqbvArltVag
svnq9xIlzjzQB+HGYQSWROhmOWpFeV+jzm0cUXJ/E81IilVXVcE3++aVuH4x4AbL
vqFMjs7Ht14BD6bXVbrLFUcVGE5R5iucgkzkLfcKSOfMUlGD0pavRWV5vqhXG/rw
4QPjJx04C5jEWJm8ymwQusWeNhOnkYlBxs/muFeyN/mYYeQHTDKRgqFkArL8fmFp
dSGkuumo6/GqI1AM5KHGcFfO3Os/CDc0g5KQYqUmYtkNsYJq9BJ5mABWiNuU7wBi
pA2znJG4HbWWAS0/qgrcr6rQFMraRXbmZtiHFukCAUsuCtsCJ/DVKyfMLiadlqCg
KUtNchgcFmCBYugnVzQJDdYqOZc20t9X8lNWtvftnmBFbTDjGGQnCkKneY4xiooQ
sELgRCyRmL/udJgYMlht
=G8rC
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-fixes-for-mmc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: DT-related fixes needed by the MMC tree
In order to convert the Tegra MMC driver to using mmc_of_parse(), some
bugs in the Tegra device-tree content need to be fixed first; it's
currently wrong but unused, and mmc_of_parse() causes that data to be
used for the first time.
* tag 'tegra-for-3.10-fixes-for-mmc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
have an Ethernet interface.
Little fixes mainly related to at91sam9x5 DT, IIO ADC bindings,
pinctrl for at91sam9260/g20 DT and the RTC addition.
Addition of the Acme Systems Aria G25 board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRXawWAAoJEAf03oE53VmQCgsH/R35if9zpMPsmWsRI8/DDIfb
t+7LIUwHsLaRLyfiQXaY5Rp1m9/a88+yKmiUseWm5QJWff9LuVpAc3zBYus75eGA
XEK9ugMmALionEukjzThOsnVeoxhsDzGjGBU43FSMovHwW6MWWChGegi9hfved+n
kZv8GgLjvIrDSsh7+jCN1qxtaf34s1PhT5+TIcPqvIGn4y4kqKRB6ZyTk781NA0n
+QJCaWyjPz21+b0r7+j70gMJ6FIfxfRzsmL24VB1KMq9Ly4+k6bGJIIMG2N9FIni
DGPoKPR2bpPVgZhRR/jSGx8qUS2+GJGuANGhpf2/yeuom1JLg9Ft0wZsDHDqClY=
=EC9a
-----END PGP SIGNATURE-----
Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre <nicolas.ferre@atmel.com>:
One macb DT node move for 9x5 family: 9g15 doesn't
have an Ethernet interface.
Little fixes mainly related to at91sam9x5 DT, IIO ADC bindings,
pinctrl for at91sam9260/g20 DT and the RTC addition.
Addition of the Acme Systems Aria G25 board.
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/at91sam9260.dtsi: fix u(s)art pinctrl encoding
ARM: at91: dts: add adc resolution stuff
ARM: at91: add Acme Systems Aria G25 board
ARM: at91/dt: fix macb node declaration
ARM: at91: remove partial parameter in bootargs for at91sam9x5ek.dtsi
ARM: at91/trivial: fix model name for SAM9G15-EK
ARM: at91/trivial: typos in compatible property
ARM: at91/at91sam9x5: add RTC node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch (patch) converts BCM2835 to support being built into a
multi-platform single zImage. This mostly entails a few small Kconfig
tweaks, move the earlyprintk implementation to the standard multi-
platform location, and deleting some unnecessary files.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXiVWAAoJEJuNpwkmVCGc0IcP/2d37uaMyrIRqw7WnQbi0hfw
UHIbNCTqQ7ki1qbcQlCn650ApvLZ+dU6zHBLQZ7x19RBKiW/71Zdey2/PXthFf0H
McV25PzDmxQ7pBhUMBJ1Hmf+0HCccON2ztzNtAMDlxZ5R8Cu1MDIPBWcMxKvbD22
/1Ut2H7X4E/nyUlavv9i++1+npU2t2ln0kgVNU9V4j+MZ0OYtOEfHnc0s9ahLYhv
r21A6bHHpVJBbnKq+IMdm6ww94ZJaIajMOIPh9OBrXAz37BISBiIDUtV1yCgQony
3EDmROpU9kMSayKX+djVLHsdRA9yjV7CTRevRqoBQmvd0esGoVVP2Yr5DVt6Ofyb
OleoNXk60JqNHe1MY/wxv6Z1vOPGUpBSfDeZd7U/pI3a0yd5cveUr4blOadFIyrV
IMt0lxTfeoaSvV0QG6Z2Rmt+mrrI/lRtADhnYAtQBB+/ulh0KWei71qa2mOsNqLJ
K7UOpSTxt09cSKW481PhlGsofTotj1L2wCDNIy9Ajg3lFXhM2e7rls0Rbmx8/w59
UsCtuQbiosUpKkCinwPQGw+NhyjKRSU1QFmQh/rA7af3e5cd61Rw8zyZrNjt0Uz2
oM01RVjK5IMtBHaFYcWM5P6ao8xSjCmbTuOWwu+fDW8DN95grRaZOYvy142xwpUH
8sVE7NEsmydvanYm5os1
=qoMR
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/multiplatform
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: bcm2835: convert to multi-platform
This branch (patch) converts BCM2835 to support being built into a
multi-platform single zImage. This mostly entails a few small Kconfig
tweaks, move the earlyprintk implementation to the standard multi-
platform location, and deleting some unnecessary files.
* tag 'bcm2835-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: convert to multi-platform
Conflicts:
arch/arm/Kconfig
arch/arm/Kconfig.debug
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the GPIO I/O memory range to the r8a7790 PFC device.
This extra I/O memory range is needed when using the PFC
tables to drive both pin functions (using PINCTRL or
function GPIO for old code) and actual GPIO. The goal is
however to use a separate GPIO driver in the long run
and when that happens this extra I/O memory range can
be removed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Twelve Kconfig symbols, all related to WM8350, WM8351, and WM8352, are
unused. Commit 19d57ed5a3 ("mfd: Remove
custom wm8350 cache implementation") removed all their (actual) users.
Remove these symbols too.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
- Fix 'function-mask' referring to TRM (Omap 36xx) Section 13.4.4:
"Pad Functional Multiplexing and Configuration".
- Fix 'omap3_pmx_wkup' referring to TRM Table 13-6:
"Wkup Control Module Pad Configuration Register Fields".
Note that these fixes are not critical currently as we
are not yet using the missing range of pinmux registers
at this point.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
[tony@atomide.com: updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This enables the fixes for the below erratas
applicable for OMAP4 Socs.
754322: Faulty MMU translations following ASID switch
775420: A data cache maintenance operation which aborts,
followed by an ISB, without any DSB in-between,
might lead to deadlock
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In some situations it is useful for userspace to
know some SoC-specific information. For example,
this may be used for deciding what kernel module to
use or how to better configure some settings etc.
This patch exports OMAP SoC information to userspace
using existing in Linux kernel SoC infrastructure.
This information can be read under
/sys/devices/socX directory
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
[tony@atomide.com: updated for multiplatform changes]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This is a long story where for each new generation of
OMAP we used different approaches for creating
strings for SoCs names and revisions that this patch
fixes. It makes future exporting of this information
to SoC infrastructure easier.
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add device-tree node for the 128MB NOR on the OMAP3430-SDP board.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add device-tree node for the 64MB NOR on the OMAP2420-H4 board.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The GPMC timing properties for device-tree have been updated by adding
a "-ns" or "-ps" suffix to indicate the units of time the property
represents (as suggested by Rob Herring). Therefore, update the timing
property names for the OMAP3430 SDP NAND and ONENAND devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the "ti,gpio-always-on" property to the appropriate GPIO banks to
indicate which banks are always powered and will never lose logic state.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Currently the DMTIMER errata flags are not being populated when using
device-tree. Add static platform data to populate errata flags when
using device-tree.
Please note that DMTIMER erratum i767 is applicable to OMAP3-5 devices
as well as AM335x devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Update the DMTIMER compatibility property to reflect the register level
compatibilty between devices and update the various OMAP/AM timer
bindings with the appropriate compatibility string.
By doing this we can add platform specific data applicable to specific
timer versions to the driver. For example, errata flags can be populated
for the timer versions that are impacted.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add a function so that OMAP dmtimers can be requested by device-tree
node. This allows for devices, such as the internal DSP, or drivers,
such as PWM, to reference a specific dmtimer node via the device-tree.
Given that there are several APIs available for requesting dmtimers
(by ID, by capability or by node) consolidate the code for all these
functions into a single helper function that can be used by these
request functions.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
When booting with device-tree the function pointer for detecting context
loss is not populated. Ideally, the pm_runtime framework should be
enhanced to allow a means for reporting context/state loss and we could
avoid populating such function pointers altogether. In the interim until
a generic non-device specific solution is in place, force a restore of
the dmtimer when enabling the timer.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The context loss handling in dmtimer appears to assume that
omap_dm_timer_set_load_start() or omap_dm_timer_start() and
omap_dm_timer_stop() bracket all interactions. Only the first two
restore the context and the last updates the context loss counter.
However omap_dm_timer_set_load() or omap_dm_timer_set_match() can
reasonably be called outside this bracketing, and the fact that they
call omap_dm_timer_enable() / omap_dm_timer_disable() suggest that
is expected.
So if, after a transition into and out of off-mode which would cause
the dm timer to loose all state, omap_dm_timer_set_match() is called
before omap_dm_timer_start(), the value read from OMAP_TIMER_CTRL_REG
will be 'wrong' and this wrong value will be stored context.tclr so
a subsequent omap_dm_timer_start() can fail (As the control register
is wrong).
Simplify this be doing the restore-from-context in
omap_dm_timer_enable() so that whenever the timer is enabled, the
context is correct. Also update the ctx_loss_count at the same time as
we notice it is wrong - these is no value in delaying this until the
omap_dm_timer_disable() as it cannot change while the timer is enabled.
Signed-off-by: NeilBrown <neilb@suse.de>
[jon-hunter@ti.com: minor update to subject and changed variable name]
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
DT field of "interrupts" was mentioned wrongly as "interrupt" in SPI
node. This went unnoticed as spi-omap2 driver not making use of
interrupt. Fixes the typo.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP4460 family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp4xxx_data.c
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp4xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
PandaBoard, PandaBoard-A4 revisions use OMAP4430.
PandaBoard-ES version of the board uses OMAP4460.
Move the original panda dts file into a common dtsi used by all panda
variants. This allows us to introduce SoC variation for PandaBoard ES
without impacting other PandaBoard versions that are supported.
As part of this change, since OMAP4460 adds on to OMAP4430, add
omap4.dtsi to omap4460.dtsi.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP443x family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp4xxx_data.c
Since the omap4460 OPP tables would be different from OMAP443x,
introduce an new omap443x.dtsi for 443x specific entries and use
existing omap4.dtsi as the common dtsi file for all OMAP4 platforms.
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp4xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Define VDD1 regulator in twl4030 DT and mark it as the supply for the
various OMAP34xx/35xx/36xx/37xx platforms (all use TWL4030 variants with
VDD1 supplying the CPU).
NOTE: This currently will use I2C1 bus communication path to set the
voltage in device tree boot. In the legacy non device tree boot, we
continue to use twl-common.c which bypasses I2C1 bus communication path
and uses I2C4 bus path using OMAP voltage libraries. We should
eventually be able to use I2C4 path once we have voltage regulator for
OMAP which is capable of using the voltage controller/voltage processor
IP blocks.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP36xx/37xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp3xxx_data.c
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp3xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP34xx/35xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp3xxx_data.c
Since the omap36xx OPP tables would be different from OMAP34xx/35xx,
introduce an new omap34xx.dtsi for 34xx/35xx specific entries and use
existing omap3.dtsi as the common dtsi file for all OMAP3 platforms.
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp3xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
OMAP hwmod layer does the reset of the IPs in early code so that
we have SOC in sane state. To do the soft-reset, it needs to ioremap()
the IP address space to be able to write to sysconfig registers.
But there are few hwmod which doesn't have sysconfig registers and hence
no need to ioremap() them in early init code.
Prevent calling the _init_mpu_rt_base() conditional based on sysc
availability.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Patch adds the code for extracting the module ocp address space
from device tree blob in case the hwmod address space look up fails.
The idea is to remove the address space data from hwmod and extract
it from DT blob.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add l3-noc node for OMAP4 and OMAP5 devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[jon-hunter@ti.com: Fix the problem caused by adding 32 to the interrupt
number for the L3 interrupts to account for per processor interrupts (PPI)
and software generated interrupts (SGI) which typically are mapped to the
first 32 interrupts in the ARM GIC. This is not necessary because the first
parameter of the ARM GIC interrupt property specifies the GIC interrupt
type (ie. SGI, PPI, etc). Hence, fix the interrupt number for the L3
interrupts by substracting 32]
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
To be able to run kernel in HYP mode, virtual timer
and GIC node information needs to be populated.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
GIC is not part of OCP space so move the gic DT node
out of ocp DT address space.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Specify both secure as well as nonsecure PPI IRQ for arch
timer. This fixes the following errors seen on DT OMAP5 boot..
[ 0.000000] arch_timer: No interrupt available, giving up
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
It has been decided to not duplicate banked modules dt nodes and that is
how the current arch timer dt extraction code is.
Update the OMAP5 DT file accordingly.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap.
Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB
memory.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the needed sections to enable audio support on
Devkit8000 when booted with DT blob.
Signed-off-by: Anil Kumar <anilk4.v@gmail.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
DevKit8000 is a beagle board clone from Timll, sold by
armkits.com. The DevKit8000 has RS232 serial port, LCD, DVI-D,
S-Video, Ethernet, SD/MMC, keyboard, camera, SPI, I2C, USB and
JTAG interface.
Add the basic DT support for devkit8000. It includes:
- twl4030 (PMIC)
- MMC1
- I2C1
- leds
Signed-off-by: Anil Kumar <anilk4.v@gmail.com>
Tested-by: Thomas Weber <thomas@tomweber.eu>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Adds basic device-tree support for OMAP3430 SDP board which has 256MB
of RAM, 128MB ONENAND flash, 256MB NAND flash and uses the TWL4030
power management IC.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The OMAP3 gpio bindings are currently missing the reg and interrupt
properties and so add these properties.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The OMAP gpio binding documention [1] states that the #interrupts-cells
property for gpio controllers should be 2. Currently, for OMAP3+ devices
the #interrupt-cells is set to 1. By setting this property to 2, it
allows clients to pass a 2nd parameter indicating the sensitivity (level
or edge) and polarity (high or low) of the interrupt. The OMAP gpio
controllers support these options and so update the #interrupt-cells
property for OMAP3+ devices to 2.
[1] Documentation/devicetree/bindings/gpio/gpio-omap.txt
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the device-tree node for GPMC on OMAP2, OMAP4 and OMAP5 devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add SDMA controller binding for OMAP2+ devices and populate DMA client
information for SPI and MMC peripheral on OMAP3+ devices. Please note
that OMAP24xx devices do not have SPI and MMC bindings available yet and
so DMA client information is not populated.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add PMU nodes for OMAP2, OMAP3 and OMAP4460 devices.
Please note that the node for OMAP4460 has been placed in a separate
header file for OMAP4460, because the node is not compatible with
OMAP4430. The node for OMAP4430 is not included because PMU is not
currently supported on OMAP4430 due to the absence of a cross-trigger
interface driver.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
If device-tree is present, then do not create the PMU device from within
the OMAP specific PMU code. This is required to allow device-tree to
create the PMU device from the PMU device-tree node.
PMU is not currently supported for OMAP4430 (due to a dependency on
having a cross-trigger interface driver) and so ensure that this
indicated on boot with or without device-tree.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add dwc3 omap glue data to the omap5 dt data file.
The information about the dt node added here is available @
Documentation/devicetree/bindings/usb/omap-usb.txt.
Also added dwc3 core dt data as a subnode to dwc3 omap glue
data in omap5 dt data file.
The information for the entered data node is available @
Documentation/devicetree/bindings/usb/dwc3.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap-usb3 and omap-usb2 data node in OMAP5 device tree file.
The information for the node added here is available @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add ocp2scp data node in omap5 device tree file.
The information for the node added here can be found @
Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in OMAP5 device tree file.
This will have the register address of registers to
power on the USB2 PHY and USB3 PHY.
The information for the node added here is available in
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add usb otg data node in omap4/omap3 device tree file. Also update
the node with board specific setting in omapx-<board>.dts file.
The dt data specifies among others the interface type (ULPI or UTMI),
mode which is mostly OTG, power that specifies the amount of power
this can supply when in host mode.
The information about usb otg node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap-usb2 data node in omap4 device tree file. Since omap-usb2
is connected to ocp2scp, omap-usb2 dt data is added as a child node
of ocp2scp. The information about this data node is availabe @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in omap4 device tree file. This will have the
register address of registers to power on the PHY and to write to
mailbox. The information about this data node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Currently the OMAP General-Purpose Memory Controller (GPMC) device
node maps 16 MB of address space for its hardware registers.
This is because the OMAP Technical Reference Manual says that the
GPMC module register address space size is 16 MB. But in practice
the maximum address offset used by a GPMC register is 0x02d0.
So, there is no need to map such a big address space for GPMC regs.
This change was suggested by Jon Hunter [1].
[1]: https://patchwork.kernel.org/patch/2057111/
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add device-tree support for the GPMC controller on the OMAP3.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap4 panda results in the following error
[ 0.444427] omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 0.445770] omap_i2c 48070000.i2c: bus 0 rev0.11 at 400 kHz
[ 0.473937] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 0.474670] omap_i2c 48072000.i2c: bus 1 rev0.11 at 400 kHz
[ 0.474822] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 0.476379] omap_i2c 48060000.i2c: bus 2 rev0.11 at 100 kHz
[ 0.477294] omap_i2c 48350000.i2c: did not get pins for i2c error: -19
[ 0.477996] omap_i2c 48350000.i2c: bus 3 rev0.11 at 400 kHz
[ 0.483398] Switching to clocksource 32k_counter
This happens because omap4 panda dts file is not adapted to use i2c through
pinctrl framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4460 panda with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Luciano Coelho <coelho@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 5430evm results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap5 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap5430 evm with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the needed sections to enable audio support on Overo.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 4430sdp results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap4 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4430 sdp with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Convert the on-board LED connected to the TWL4030 (LEDB) to use
pwm-leds.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Section to describe the backlight for the LCD panels.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Sections to describe the pwm-leds in the system.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
We have proper driver stack to handle the pmu_stat LED which is connected
PWMB of twl4030.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Enable support for the PWMs and LED as PWM drivers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Enable support for the PWMs and LEDs as PWM drivers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add a new address space/memory resource to d_can device tree node. D_CAN
RAM initialization is achieved through RAMINIT register which is part of
AM33XX control module address space. D_CAN RAM init or de-init should be
done by writing instance corresponding value to control module register.
Till we have a separate control module driver to write to control module,
d_can driver will handle the register writes to control module by itself.
So a new address space to represent this control module register is added
to d_can driver.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add d_can instances to aliases node to get the D_CAN instance number
from the driver. To initialize D_CAN message RAM, corresponding instance
number is required.
To initialize instance 0 message RAM then 0x1 should be written and for
instance 1 message RAM, 0x2 should be written to control module register.
With device-tree framework ip instance number is "-1" by default for all
instances. To get device id/instance number then modules should be added
to DT "aliases" node. of_alias_get_id() gives the device id number based
on number of alias nodes present in "aliases node".
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
This is a follow-up to Javier Martinez effort adding initial
device tree support to IGEP technology devices [1].
It adds uart1 and uart2 bindings to the generic dtsi for the IGEP boards.
[1] http://www.spinics.net/lists/linux-omap/msg83409.html
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
ISEE IGEP COM Module is an TI OMAP3 SoC computer on module.
This patch adds an initial device tree support to boot an
IGEP COM Module from the MMC/SD.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
[b-cousson@ti.com: Update the Makefile for 3.8-rc2]
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
ISEE IGEPv2 is an TI OMAP3 SoC based embedded board.
This patch adds an initial device tree support to boot
an IGEPv2 from the MMC/SD.
Currently is working everything that is supported by DT
on OMAP3 SoCs (MMC/SD, GPIO LEDs, EEPROM, TWL4030 audio).
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
[benoit.cousson@linaro.org: Update the Makefile for 3.8-rc2]
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add a generic .dtsi device tree source file for the
common characteristics across IGEP Technology devices.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Rename I2C and GPIO nodes according to AM33XX TRM. According to
AM33XX TRM device instances are starting from "0" like i2c0, i2c1
and i2c3.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
[panto@antoniou-consulting.com: initial patch by pantelis's]
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The pwm-backlight driver now takes a mandatory regulator that is gotten
during driver probe. Initialize a dummy regulator to satisfy this
requirement.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated fixed regulator id to avoid errors]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use pwm_leds driver for the keyboard light and pwm-backlight for the lcd
backlight control (instead of implementing the PWM driver part in the board
file).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch enables BMP085 pressure sensor that can be
found on OMAP4 Blaze Tablet development platform
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Merge commit 952414505f ("Merge branch
'next/cleanup' of git://git.linaro.org/people/arnd/arm-soc") added
references to CONFIG_MACH_PCM049 and board-omap4pcm049.o to this
Makefile. But there's no Kconfig symbol MACH_PCM049 and there's no file
board-omap4pcm049.c. This line can safely be removed.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit f41caddbe7 ("omap2+: Use Kconfig
symbol in Makefile instead of obj-y") reorganized this Makefile. But,
for some reason, it also added references to CONFIG_MACH_ENCORE and
board-omap3encore.o. But there's no Kconfig symbol MACH_ENCORE and
there's no file board-omap3encore.c. This line can safely be removed.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
omap_udc platform device is not registered properly anymore:
CONFIG_USB_GADGET_OMAP was deleted by 193ab2a6 (usb: gadget: allow
multiple gadgets to be built) already in v3.1.
Fix by using CONFIG_USB_OMAP instead. Tested on Nokia 770 by checking
that omap_udc is probed & working properly when built as a module.
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The TIME_VALID flag is specified for the different states but
the time residency computation is not done, no tk flag, no time
computation in the idle function.
Set the en_core_tk_irqen flag to activate it.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The davinci_enter_idle is called from the cpuidle with the
cpuidle_wrap_enter function. This one does the time compution
for entering and exiting the idle function and then we call
again cpuidle_wrap_enter for cpu_do_idle. This is wrong, we
are calling recursively cpuidle_wrap_enter for nothing and
furthermore reenabling the local irq.
Remove this and replace it by the cpu_do_idle function.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
dev->state_count is initialized automatically by
cpuidle_register_device().
When drv->state_count is equal to dev->state_count, no need to init
this field, so removing it.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Initialize the idle states directly in the driver structure.
That prevents extra structure declaration and memcpy at init time.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Remove the shmobile_enter_wfi function which is the same as the
common WFI enter function from the arm cpuidle driver defined
with the ARM_CPUIDLE_WFI_STATE macro.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Add the __init section for the functions which are called
at init time.
Signed-off-by: Daniel Lezcano <daniel.linaro.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
In the early days, the A10 and A13 shared quite some code. Nowadays it
shares less and less code, the A31 diverging even more, so it doesn't
make much sense to continue to maintain this structure, just use one
DTSI for every SoC, and that's it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner sun6i (A31) has a slightly different watchdog, that
doesn't allow to use the already existing restart code.
Rework a bit the restart code to allow to plug in more easily different
restart handlers depending on the device tree.
In the past, we were also meaning sunxi as a generic name covering all
Allwinner SoCs. This won't be true anymore with the A31 (sun6i) that
differs pretty much from sun4i and sun5i, and we will end up having
sunxi, for sun4i and sun5i, and sun6i, which is neither consistent nor
convenient. So, while we're at it, also change sunxi to sun4i.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This allows to remove some boilerplate code. At the same time, call the
set_handle_irq function in the initialization function of the irqchip,
so that we can remove it from the machine declaration.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.
It was ok at the time of the support of only the A10 and A13 that
looks pretty much the same, but it's beginning to be troublesome with
the future addition of the Allwinner A31 (sun6i) that is quite
different, and would introduce some weird logic, where sunxi would
actually mean in some case sun4i and sun5i but without sun6i...
Moreover, it makes the compatible strings naming scheme not consistent
with other architectures, where usually for this kind of compability, we
just use the oldest SoC name that has this IP, so let's do just this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Using CLKSRC_OF allows to remove the SoC specific sunxi_timer.h header,
and instead of using a custom init function in the machine definition
use the standard clocksource_of_init function.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Rename the clock compatible introduced in the first pull request for 3.10
- Complete the UART support for A13 and A10
- Adds clock gates support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXwBbAAoJEBx+YmzsjxAgDf8P/A3i6dGQe2DMnLRzJ8fwAsvj
VXqoC6YKEszelVSeQuqDE/pytoUfb1+1xEklkj95sHS4ds7fV6qVLM2Lp3TrBBEk
oGdwC6cS97BeNZxnnkTXUNWHlXdlFbkI7D0bd/GC4LLjrpUzu299BPdQ3zoXUEqf
xlm32aydivW87MX/1BfwdQPqA05x6/ZvOcxkWK6qQvXNl/iBoksJRjjQQdrCDxqz
fe34XbflblgQv3cmiONpi7BCFWzKVZcvDD1pHdgdNXiahpZjNMnFH7DEUhc24tTX
DHGwMwhvGDvjD/gp6h6xvCswYxMyLmFUZp2TKJ4ffd04/jncvPIUuSYzkeyUOGav
ZVBBik41Pxk+aKOX75vYffhHSb+AtmQqaORHLXidIOVC1UlnlHOj6RMODs2Z+JzG
kLhdy0fmLSaf6rKDvFAyqjR16apiaeRwxd581jKoFDn10P/c1Fg+R2FvrE8DA2fP
tiKDPrdO3U1CUq8PVYJFuN2D7SfkOSRz72tcMaFuBFnk7E0pmcgwzkvD7VqFexA4
Qf55VjSITMpVBX4L+TLCMgckp4OjcBQtwEgYQjwTNjtVRpr5BQUwBTHKCgRZt7jo
WaO8P4FLg4rka9aV52hNCka+O7qTeLOkfC08mZZGUkkfQ0gb4U8EAhdPRNsSiOHj
qtiLCwLX7X+WEIWs8vfo
=ErkU
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux into next/dt
From Maxime Ripard <maxime.ripard@free-electrons.com>:
ARM: sunxi: dt additions for 3.10, take 2
- Rename the clock compatible introduced in the first pull request for 3.10
- Complete the UART support for A13 and A10
- Adds clock gates support
* tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux:
arm: sunxi: Add clock to pinctrl node
arm: sunxi: use the right clock phandles for UARTs
arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
ARM: sunxi: cubieboard: Add UART muxing
ARM: sunxi: hackberry: Add UART muxing
ARM: sunxi: dt: Add A10 UARTs to the dtsi.
ARM: sunxi: dt: Add uart3 dt node
ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi
ARM: sunxi: Rename uart nodes to serial
ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs
arm: sunxi: rename clock compatible strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
An update to the defconfig for the bockw board to enable SMSC ethernet.
This is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards3-for-v3.10
The reason for using that base is that the bockw defconfig was added
in the boards branch instead of the defconfig branch, which was not ideal.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXjpQAAoJENfPZGlqN0++0OsQAJaxsIgSWmlOmHCOAnUnPPPj
kl2DPaPCLGlu17G0UmgqkMrZKtB1j9IwVm6e+/YgCorbvFiqZ/cyOB/TqCnO4YPi
4y6fmR0YJKWaI2onhJd/AHplAu+Z0ILr3kcZOMy3pl3Qt2b97TdFYUl/kQ9JYWi9
Upmb7ErGEjdfYa3Gt+/QT4MBmoHaWik60Hs8SqA8QtBEYfxBsDJK07Lf3MtRX7p9
Kc0U6s+Vz5vKOZAlr3U2XMSBU3oPJvAC1kvNfEFdVIO0WhrfB6Htn1Esrz5ZoR2P
F9kc9O/4nwr/Oj0+YIoFnByJc7fj0gc9I2jPIa0t0SzkPVQwpD+qj2OYmsbjUftj
rCHjrdzofNXIUGCA1XWxTKsynafbgW1MQUbKmpi4SL9GUtc7h89VzxlHxG9w6jjO
wUqx2dQX1cG9m3bxtHCfa2/HN+qN0jtt/dh1R3w0fda8lvB1pavvpgNPO/vhVHDD
cKQsMbwie6uuH6WUIrzVSa5Htb4ku18bRI2T+0X5j8tjw4jM2tViGnKKWE5Gk5I4
OS59wLLN0OZg4CuMkipsiSutOZy2kpFb8XNaLqpjJPEEmIugooh3aiB/alYgQIyT
wXXT6ZEPg+WdX7iiHYak6QScG51HYt00qvNJ6spJ+pW62XK/KxxdceR0Am/Ezj93
uxc1D6q97/RfU2JRgQkE
=RzhQ
-----END PGP SIGNATURE-----
Merge tag 'renesas-defconfig-bockw-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2
From Simon Horman <horms+renesas@verge.net.au>:
Renesas ARM based SoC bockw defconfig updates for v3.10
An update to the defconfig for the bockw board to enable SMSC ethernet.
This is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards3-for-v3.10
The reason for using that base is that the bockw defconfig was added
in the boards branch instead of the defconfig branch, which was not ideal.
* tag 'renesas-defconfig-bockw-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: bockw: enable SMSC ethernet on defconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch (patch) updates bcm2835_defconfig to enable new features that
were added this kernel cycle. Namely, the SPI controller and HW random
number generator.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXiW6AAoJEJuNpwkmVCGc9aoP/3kQaWFz3viv1XiwyH2EqVFL
K9UhJi2ZalrUPNyyaOyW20EFRYOM6vA8ud8oBhEVbxxXV2Z/QOnJRCfi60xutEr2
9WE3g80bArbrc7dSiUWlY6+cWz5BFplrcP5jV5lbEemfGIF0Bf3837YNSn6DUSIx
Z6Sli8iogsvMcDp9Ke1fMCxkljIIubpmp++Oi/tYDQ0F9MTpd9Jo3FaNhRzQ17RZ
M64Zrx3vI6j9SC83Oq3XbvY808J/vrPnOXcknnTX1bIQJlJ4o2c8Vogoca7p6hIw
2BYJpHw/VTLc/9k3zfT8vM2x4j+XFZASgOSLDoJkgHV2dk4+LKiFJH6eqeWWp4Ya
d2LefxNuF1b9avaWWY0HkOTr8KRDwkuSYw8eHtIYHP8jHMNI5NEgKX59PYM2dIOn
SbOGBmGA8CD/dUO/e+wpKg68puGYefIF4z2GZ6bZKRf/niZQbhEf5A0yDtBTya0d
1gsdEmSDrcBYwSeZm8y+oQnqJJcRMRpy+rKD8mA6EI2qKyDmPeOsOXOl7LK9ntyk
kNNZQMwHwwdIBnBqSnfloaEOTLDhc/IvYvrwfmi3FMnOImqKO0SogpnvescCfH61
QE6l6ZonUpXgUO1p//1au6dqZcml7+GhUOOBucfE2y7wVWqr+TrygiSrJEV/c/+L
nFa7/Ujg/1JHXoibPwRF
=GaCF
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-for-3.10-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/soc
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: bcm2835: defconfig updates
This branch (patch) updates bcm2835_defconfig to enable new features that
were added this kernel cycle. Namely, the SPI controller and HW random
number generator.
* tag 'bcm2835-for-3.10-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: defconfig updates
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch adds two devices to the BCM2835 SoC device tree: the SPI
controller and the HW random number generator.
The SPI controller isn't actually instantiated in the Raspberry Pi
device tree, since there are no on-board SPI devices; it's up to the
end-user to modify their own device-tree to describe whatever they
have attached.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXiScAAoJEJuNpwkmVCGckMkP/RFLV7a4QQORyO9HhZkqaMGD
iwHtHFiFgbFmrc76oe/DxJrnJieSWdreVSWXc5NpAv6uZqMx7Lc11dGV399R+v0C
IaB7z7lMHBOk2IOmjIwVby8vrrHX5Ui7vweYxjk9k117U7ZN/syAcaPQsj32W6Lr
wKn+CpmyIzU0iB0kyydLfS18znW7gd17WFOu8tYB3qqf+avJNzcOfNHaIlafG0s6
+qn/gBWPRNg/ceyV94kPyjsPoLqv1q3YJER1P9Tvyb9MQecwpBd/ZmZjWr14hMf0
SvjsHD2uLV8UO0Wq/R5+VnC1YybsrOAvbgZz06Ai+SDa33diHXp4/uXqJ0soWTT8
hG4a2V965LfCUNVHFmAGL8ZcZk/HaL4FLucKceDavcorFuN7rtK+q6rAoYk0cR8j
bYi0xIIPctd28Mkpx1ArifeAa9+jeAxwC79H3jn9xzdYBdVJkV6SgSBZPQFbQviP
eFJu+Rh2QOA2Icm2dLOr6aZXdGWFO8DBF9LSLzXaX5yOaUYsGNKLBl7JOY+0MA47
P6TMokbHRULKqSfgUJxf+jCcXKl8hOB/obSw3SX1sTVxaAmi2IL39salwIQXloIz
/1Wjgbv2eVxtSbM9XResvpsTxE6RdZuz0uE5BKgXIvI6fwdZ9uQaAWvxphn0MvXt
Qz0aMbTD0wEIANE6j/u4
=4Sjv
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/dt
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: bcm2835: device tree updates
This branch adds two devices to the BCM2835 SoC device tree: the SPI
controller and the HW random number generator.
The SPI controller isn't actually instantiated in the Raspberry Pi
device tree, since there are no on-board SPI devices; it's up to the
end-user to modify their own device-tree to describe whatever they
have attached.
* tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: add Broadcom BCM2835 RNG to the device tree
ARM: bcm2835: add SPI device to DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Adds GPMC (General Purpose Memory Controller) DT support for
NOR flash and Ethernet and includes various GPMC cleans-up
and fixes.
This series is dependent on commit 7185684 (ARM: OMAP: use
consistent error checking) from RMK's clean-up branch and commit
31d9adc (ARM: OMAP2+: Fix broken gpmc support).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXcsJAAoJEBvUPslcq6VzwKYQANHrnD6R0sv5kTcxT6wqIOv/
GXaN5aOI7xvplSwORTUuw4wGt9M0kTf/nDKcu+THSYzVsrIXD/zIXoOzH0q8FBPG
2qmVYJah5LiKCT0M53/DityXD4teCOfK/Ld3w6JqepbAH63ZrNyFI1Zo+JcEvJEW
qVM16UzEU9k4dk6ENq3PV1HYGnk/cvreG0TkRFnIYHR/+JsUNiderx4ucYYO7oNT
3Ft4LYMx2p6pOO1K1FqqikN8m+C1Z2Q+1uouo/b9Yvi3phFW+f2e32NEKdtXMQjV
Eqbz9q0O0mWx9tBq2C+y4nlI+QwjoEcZ5WsU9PNAwyUqu+dZiac28uJo6eIdmlOr
sw1zwni5XdxnnnjAjG9o9WZAJPpRv6sMLpEaVu2rm4tRi27l1oh6OTfmHsyEv+CR
mp6cXi9HaDw0ErBxE6kkDiBUkyK0ayyx+v58NJUT363Mc48felKi1ZMoyFLPtbBb
BnQ91uEp2Kjkx1ebVvKO+8AsrNF6e6rTSVUHfPCef6zJH/v/+6XXxLerQGD5jNDB
HWFsIwQj+76hOpp4rpUU46HFKgHWyp4qvFBx0y/U2txv8ruD26XemowUhch/ONK6
3niZzOcXhesjM41bZRmUhzSuW685ZHKN0lBO5U4i+IEL0YHEnpkYbp34hHLzp1ll
4PaIxx6CZz1QV+IIO91z
=sfId
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
GPMC updates from Jon Hunter <jon-hunter@ti.com>:
Adds GPMC (General Purpose Memory Controller) DT support for
NOR flash and Ethernet and includes various GPMC cleans-up
and fixes.
This series is dependent on commit 7185684 (ARM: OMAP: use
consistent error checking) from RMK's clean-up branch and commit
31d9adc (ARM: OMAP2+: Fix broken gpmc support).
* tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (29 commits)
ARM: OMAP2+: Add GPMC DT support for Ethernet child nodes
ARM: OMAP2+: rename gpmc_probe_nor_child() to gpmc_probe_generic_child()
ARM: OMAP2+: return -ENODEV if GPMC child device creation fails
ARM: OMAP2+: Allow GPMC probe to complete even if CS mapping fails
ARM: OMAP2+: Remove unnecesssary GPMC definitions and variable
ARM: OMAP2+: Detect incorrectly aligned GPMC base address
ARM: OMAP2+: Convert ONENAND to retrieve GPMC settings from DT
ARM: OMAP2+: Convert NAND to retrieve GPMC settings from DT
ARM: OMAP2+: Add device-tree support for NOR flash
ARM: OMAP2+: Add additional GPMC timing parameters
ARM: OMAP2+: Add function to read GPMC settings from device-tree
ARM: OMAP2+: Don't configure of chip-select options in gpmc_cs_configure()
ARM: OMAP2+: Convert TUSB to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert SMC91x to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert NAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert ONENAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Add function for configuring GPMC settings
ARM: OMAP2+: Add structure for storing GPMC settings
ARM: OMAP2+: Add variable to store number of GPMC waitpins
ARM: OMAP2+: Simplify code configuring ONENAND devices
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on 7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and 960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of 7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXGvCAAoJEBvUPslcq6VzKRQQAIedi+lXSAQk/0t2wythB+Es
94oGmo5g2In+A7FE3gt7IOkSn/k334AwgizcCVRJewvJYii+8vvttVzBqlnyxGAG
VVu0lJ5rwpCd8R4bmcl+dg5jnKreC3doE51D9M0NtU+GW4gln5m3dCq22cbz3sET
GzGPSBJeWpHin2xHmIGR9210KdY8LT2yP6nIcwFLK6EiQNS/XFj1akaehgnnGjMB
9qqi06iRpBszJTEHXfEUfD6UMA4Tml7HQUuqjEt+oMod+Ucu98XhgfpCJr+WN67g
xHxoR8bitVVhReU6WmWNLuSl3CX/fBG81RTxagA7SSVCg93NEd0lPX1K+U8jy5hR
V+/wcgb0t0W0us+yuBwPvmlJ+E2t64NjUBXr7rDEwQGk/QSmd3kzQlSpLwnamDx4
hqnpXPpt5tbCUl6Ubqn4hLnsqz2VJAFw6QWZl+UhkvQMd0RNOg3faJSxjUdzo5n9
2IKx0ZWAXXNIKKp8eBh7w3z4qlWiK0Xfsq/GuSfHx49ybFRGkX38FI34I9eUYbH8
14vAfQkb0Tv+X0U3O03rNY6cpOz7nXG3FACBxOp+upYQKN+rFfM3DP+jPrWaLeJg
KFfJT1kVEuOi09X2jAFmuj7E2pFamGujFqm7eZ7Vj9NT0NXGI5s87nlpobrOXL2V
blRJmn0JBqFE+R6udU5+
=5kiA
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>:
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on 7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and 960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of 7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
* tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Fix sparse warning in system timers
ARM: OMAP2+: Store ID of system timers in timer structure
ARM: OMAP3: Update clocksource timer selection
ARM: OMAP2+: Simplify system timers definitions
ARM: OMAP2+: Simplify system timer clock definitions
ARM: OMAP2+: Remove hard-coded test on timer ID
ARM: OMAP2+: Display correct system timer name
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
These are needed for the USB PHY support, and are based on
commit 1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRWxNHAAoJEBvUPslcq6VzFVEP/2Lr3RULnqiQbGx03SGySeXB
bS/CuVYjiWEK7bJC4glx2BzQYF612N0cx60TYtrErbiU99pyFmhHNp9VWBjgmHBl
GGuLWcwUgp4skzgk18SFDqSC/80VP/eGnuD3UBPfNRSL43qvutHg32OPrunvEVRQ
ojRZ8o8Dw9Tn2lcfev0dXu7/nYKrlREKGfU0nMrUBbBMKfwc9o4t1y4KdFIq9agx
FBJ8LsKKIQh5UsmE6jOApobVkiuUfSVqHS5x3SYdiPvX5FMP3TX5xTIGBeeXWgsx
/fp46X0h3PXNrruF/+KO8FlZ00EZBsZ8/FCKYyiTjHI/bHE9SLh/3Udi3MvUyI2S
xUN9G5vZFIzD9c7MIWVriml8luN1PsTK2R+FVJ0bXKXQixPylVrQRHIFKj2nby7m
gHog6KNBvWNKW7MGPOq3YG3bhBCNCj1pC/IHpChB9cBRcPNTdwXVRB6sZ+KkHlYK
N0myjweYLwxk/spm2IzmAFHje0T0039KD/ouGnnt3HO6a1V1TZfZBbn6ZUJqAZ/+
bHwEimvc1lU8FscvFqEHwd2IT6yQTfq2l6W8Su4oxpwiWkNiwbqwpbOGdYnMUmgI
YcNlGtw4ivjbCqu+O/8o1I/YUnv3z7NtCvjZGAUUccjbadJ3744b7BNWqmwOdflD
eARubcN0jNnnBO5wyaPi
=TU3y
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
EHCI platform data related changes for v3.10 merge window.
These are needed for the USB PHY support, and are based on
commit 1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
* tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-beagle: Add USB Host support
ARM: dts: OMAP3: Add HS USB Host IP nodes
ARM: dts: OMAP4: Add HS USB Host IP nodes
ARM: OMAP: zoom: Adapt to ehci-omap changes
ARM: OMAP3: overo: Adapt to ehci-omap changes
ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes
ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes
ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes
ARM: OMAP3: omap3evm: Adapt to ehci-omap changes
ARM: OMAP3: igep0020: Adapt to ehci-omap changes
ARM: OMAP: devkit8000: Adapt to ehci-omap changes
ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes
ARM: OMAP3: cm-t35: Adapt to ehci-omap changes
ARM: OMAP: AM3517evm: Adapt to ehci-omap changes
ARM: OMAP: AM3517crane: Adapt to ehci-omap changes
ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes
ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes
ARM: OMAP3: Beagle: Adapt to ehci-omap changes
ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes
ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys()
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Both zynq and shmobile have conflicts against the gic cleanup
series, resolved here.
Conflicts:
arch/arm/mach-shmobile/smp-emev2.c
arch/arm/mach-shmobile/smp-r8a7779.c
arch/arm/mach-shmobile/smp-sh73a0.c
arch/arm/mach-zynq/platsmp.c
drivers/gpio/gpio-pl061.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Boards using secure firmware must use different CPU boot registers and
call secure firmware to boot the CPU.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
On TrustZone-enabled boards the non-secure SYSRAM is used for secondary
CPU bring-up, so add a mapping for it.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Some Exynos-based boards contain secure firmware and must use firmware
operations to set up some hardware.
This patch adds firmware operations for Exynos secure firmware and a way
for board code and device tree to specify that they must be used.
Example of use:
In board code:
...MACHINE_START(...)
/* ... */
.init_early = exynos_firmware_init,
/* ... */
MACHINE_END
In device tree:
/ {
/* ... */
firmware@0203F000 {
compatible = "samsung,secure-firmware";
reg = <0x0203F000 0x1000>;
};
/* ... */
};
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Some boards use secure monitor calls to communicate with secure
firmware.
This patch adds exynos_smc function which uses smc assembly instruction
to do secure monitor calls.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Some boards are running with secure firmware running in TrustZone secure
world, which changes the way some things have to be initialized.
This patch adds an interface for platforms to specify available firmware
operations and call them.
A wrapper macro, call_firmware_op(), checks if the operation is provided
and calls it if so, otherwise returns -ENOSYS to allow fallback to
legacy operation..
By default no operations are provided.
Example of use:
In code using firmware ops:
__raw_writel(virt_to_phys(exynos4_secondary_startup),
CPU1_BOOT_REG);
/* Call Exynos specific smc call */
if (call_firmware_op(cpu_boot, cpu) == -ENOSYS)
cpu_boot_legacy(...); /* Try legacy way */
gic_raise_softirq(cpumask_of(cpu), 1);
In board-/platform-specific code:
static int platformX_do_idle(void)
{
/* tell platformX firmware to enter idle */
return 0;
}
static int platformX_cpu_boot(int i)
{
/* tell platformX firmware to boot CPU i */
return 0;
}
static const struct firmware_ops platformX_firmware_ops = {
.do_idle = exynos_do_idle,
.cpu_boot = exynos_cpu_boot,
/* other operations not available on platformX */
};
static void __init board_init_early(void)
{
register_firmware_ops(&platformX_firmware_ops);
}
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds a arm-pmu node to bind device tree for exynos4210.
The exynos4210 and 4212 have two cpus which includes a pmu. In contrast, the
exynos4412 has 4 cpus and pmus. We need to define two more pmus for this type
board. However, supporting arm-pmu for the exynos4412 will handle it later
because there is no dts support for 4412 based board.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch defines irq numbers of ARM performance monitoring unit for exynos4.
Firs of all, we need to fix IRQ_PMU correctly and to split pmu initialization
of exynos from plat-samsung for easily defining it.
The number of CPU cores and PMU irq numbers are vary according to soc types.
So, we need to identify each soc type using soc_is_xxx function and to define
the pmu irqs dynamically. For example, the exynos4412 has 4 cpu cores and pmus.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch corrects combined IRQs for exynos4 series platform. The exynos4412
has four extra combined irq group and the exynos4212 has two more combined
irqs
than exynos4210. Each irq is mapped to IRQ_SPI(xx). Unfortunately, extra 4
combined IRQs isn't sequential. So, we need to map the irqs manually.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: changes moved into drivers/irqchip/]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Jason Cooper