There is a common pattern that registers individual peripheral clocks
from an initialization table. Add a common implementation to remove the
duplication from various call sites.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The recent conversion of proper const usage was only partial and didn't
include Tegra20 and Tegra30 support. Fix that up.
Signed-off-by: Thierry Reding <treding@nvidia.com>
checkpatch now warns for const ** and expects const * const * to be used
instead. This means we have to update the prototypes and function
declarations to handle this change.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The peripheral clock registers are defined in static tables. These
tables never need to be modified at runtime, so they can reside in
read-only memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
tegra_clk_periph_no_gate_ops is a local symbol.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
entirely of new platform/driver support. There are some conversions of
existing drivers to the common-clock Device Tree binding, and a few
non-critical fixes to the framework.
Due to an entirely unnecessary cyclical dependency with the arm-soc tree
this pull request is broken into two pieces. The second piece will be
sent out after arm-soc sends you the pull request that merged in core
support for the HiSilicon 3620 platform. That same pull request from
arm-soc depends on this pull request to merge in those HiSilicon bits
without causing build failures.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJS4WZPAAoJEDqPOy9afJhJVz4QAL63xispjEVuABUjgskR1fyo
7QljpqUJCOViqiVqNi1sPtM0irvfrApNwTpK3mGm20/kbNIBSdqGc/fI5CbWxXAU
scRqplTTLY6F7nXJXGgiM/e5b31Tb+KmY9Su5chq1Yv6py4/yb6SzoohcBlQJ5in
JKIxgLqe1VqUkCY2EFlqLwYqUtgr/Zm6ZJDt4LTwxc43apwgG7USMAS8ppx7nTgd
oGgcsU4dNur1L4+ahvwqC+ntfoZNmVKJm+eY+JrHXJ2sga4PLaJcorgK2NXFpgln
nwZQzRfbZLg7vNg/ODIDvP94mhc266xq2TCWzD/kMOBwmhsM0lySpzI/IM8qv1U2
Tdy9EHAj2iHoU+s1yPEUtNRV4h2+BGUUy54690XO30+VCLVEJUCC2KopDAk0G3ua
qxSCb1mJto8EEq3jCJwKZSOUI7gcizDjHAaqfLlnDytMlsFJR7AJVj5IcRdgC/9s
Vg975Xklkn33fWEuYQzdQdcmJ8ZCnydo92R2S0CaMgxMZqp2eoYZXJWvgCAvfQYC
HjAtnBpHxNsZQeASvclb9bQrEisAUjIrxvuzLenQhg88WhBuyUDgBdretCzHFhP4
i62QGAhSYiNJJQzs+U9EndG6fRr/p98Pmw2pBAAn8UYOT2wWMj8wpR+IVT50Bmdi
j6LsDpvc7CE2a4f+KoCa
=Hh66
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework changes from Mike Turquette:
"The first half of the clk framework pull request is made up almost
entirely of new platform/driver support. There are some conversions
of existing drivers to the common-clock Device Tree binding, and a few
non-critical fixes to the framework.
Due to an entirely unnecessary cyclical dependency with the arm-soc
tree this pull request is broken into two pieces. The second piece
will be sent out after arm-soc sends you the pull request that merged
in core support for the HiSilicon 3620 platform. That same pull
request from arm-soc depends on this pull request to merge in those
HiSilicon bits without causing build failures"
[ Just did the ARM SoC merges, so getting ready for the second clk tree
pull request - Linus ]
* tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits)
devicetree: bindings: Document qcom,mmcc
devicetree: bindings: Document qcom,gcc
clk: qcom: Add support for MSM8660's global clock controller (GCC)
clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)
clk: qcom: Add support for MSM8974's global clock controller (GCC)
clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)
clk: qcom: Add support for MSM8960's global clock controller (GCC)
clk: qcom: Add reset controller support
clk: qcom: Add support for branches/gate clocks
clk: qcom: Add support for root clock generators (RCGs)
clk: qcom: Add support for phase locked loops (PLLs)
clk: qcom: Add a regmap type clock struct
clk: Add set_rate_and_parent() op
reset: Silence warning in reset-controller.h
clk: sirf: re-arch to make the codes support both prima2 and atlas6
clk: composite: pass mux_hw into determine_rate
clk: shmobile: Fix MSTP clock array initialization
clk: shmobile: Fix MSTP clock index
ARM: dts: Add clock provider specific properties to max77686 node
clk: max77686: Register OF clock provider
...
tegra_clk_periph_nodiv_ops is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Now that no code uses the custom Tegra module reset API, we can remove
its implementation.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The tegra_periph_reset_assert() and tegra_periph_reset_deassert()
functions can be used by drivers to reset peripherals. In order to allow
such drivers to be built as modules, export the functions.
Note that this restores the status quo as the functions were exported
before the move to the drivers/clk tree.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding