Commit Graph

843451 Commits

Author SHA1 Message Date
Andrey Grodzovsky b5507c7e06 drm/amdgpu: Fix GPU reset crash regression.
amdgpu_ip_block.status.hw for GMC wasn't set to
false on suspend during GPU reset and so on resume gmc_v9_0_resume
wasn't called.
Caused by 'drm/amdgpu: fix double ucode load by PSP(v3)'

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:53:19 -05:00
Evan Quan 8dd45504a7 drm/amd/powerplay: check before issuing messages for max sustainable clocks
Those messages are not supported on Arcturus and should not be
issued.

Affected ASIC: Arcturus

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:53:13 -05:00
Xiaojie Yuan b5c7385640 drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
common function nv_reg_base_init().

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:53:05 -05:00
tiancyin 35ef88fa11 drm/amdgpu/soc15: fix external_rev_id for navi14
fix the hard code external_rev_id.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:52:58 -05:00
Tao Zhou 2a3c7ff6e3 drm/amdgpu: update ras sysfs feature info
remove confused ras error type info

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:52:52 -05:00
Evan Quan 9234c587a8 drm/amd/powerplay: skip pcie params override on Arcturus V2
This is not supported on Arcturus.

Affected ASIC: Arcturus

V2: minor cosmetic fix

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:52:45 -05:00
xinhui pan 876923fb92 drm/amdgpu: Fix panic during gpu reset
Clear the flag after hw suspend, otherwise it skips the corresponding hw
resume.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:52:37 -05:00
Likun Gao 1f288afc2c drm/amdgpu: pin the csb buffer on hw init for gfx v8
Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Tested-by: Paul Gover <pmw.gover@yahoo.co.uk>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:52:31 -05:00
Nicholas Kazlauskas caff0e6654 drm/amd/display: Block immediate flips for non-fast updates
[Why]
Underflow can occur in the case where we change buffer pitch, DCC state,
rotation or mirroring for a plane while also performing an immediate
flip. It can also generate a p-state warning stack trace on DCN1 which
is typically observed during the cursor handler pipe locking because of
how frequent cursor updates can occur.

[How]
Store the update type on each CRTC - every plane will have access to
the CRTC state if it's flipping. If the update type is not
UPDATE_TYPE_FAST then the immediate flip should be disallowed.

No changes to the target vblank sequencing need to be done, we just
need to ensure that the surface registers do a double buffered update.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:52:24 -05:00
Nicholas Kazlauskas 2cc450ceaa drm/amd/display: Validate dc_plane_info and dc_plane_size in atomic check
[Why]
Pitch, DCC, rotation and mirroring can result in updates that are not
UPDATE_TYPE_FAST but UPDATE_TYPE_MED instead. DC needs dc_plane_info
and dc_plane_size to make this determination and we aren't currently
passing this into DC during atomic check.

Underflow (visible or non-visible) can occur if we don't validate this
correctly. This also will generally trigger p-state warnings, typically
via the cursor handler when locking.

[How]
Get the framebuffer tiling flags and generate the required structures
for DC in dm_determine_update_type_for_commit.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06 13:52:05 -05:00
shaoyunl 3cf7bf2e48 drm/amdgpu: enable Navi12 kfd support for amdgpu
Navi12 has the same interface as Navi10

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Roman Li fbd2afe536 drm/amd/display: Add missing NV12 asic IDs
Add missing navi12 asic ids.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Leo Li 078655d982 drm/amdgpu: Add nv12 DC ip block
Load DC and amdgpu display manager

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Leo Li 36bbb634b7 drm/amd/display: Add ASICREV_IS_NAVI macros
They are used by DC to determine ASIC revs.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Boyuan Zhang 400e9c5ea6 drm/amdgpu: enable DPG mode for Navi12
Enable Dynamic Power Gating VCN for Navi12.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Boyuan Zhang 1fbed280a2 drm/amdgpu: add VCN ip block for Navi12
Add VCN2 ip block for Navi12

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Boyuan Zhang a3219816c4 drm/amdgpu: add Navi12 VCN firmware support
Add Navi12 to VCN family

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Xiaojie Yuan 6b66ae2e55 drm/amdgpu: add psp ip block for navi12
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Xiaojie Yuan 7f47efeb9e drm/amdgpu: add smu ip block for navi12
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Xiaojie Yuan e60cc94b26 drm/amdgpu: start autoload till RLCG fw for navi12
rlc save restore list is not ready yet for navi12

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Xiaojie Yuan 739cdbd6a2 drm/amdgpu/psp11: add psp support for navi12
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Xiaojie Yuan 9ea8da75ba drm/amdgpu/smu11: add smu support for navi12
Same as other Navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Jack Xiao 02938eed74 drm/amdgpu: correct smu rlc handshake enablement bit
Correct the enablement bit of SMU RLC handshake.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:41 -05:00
Xiaojie Yuan 87190edcf3 drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header
gc 10.1.2 introduced this new register

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan c726fbf0fb drm/amdgpu/sdma5: add golden settings for navi12 (v2)
common golden settings are put in golden_settings_sdma_5 array

v2: update settings (Alex)

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan f8984cb9e3 drm/amdgpu/gfx10: add golden settings for navi12 (v2)
Add initial golden settings for navi12 gfx.

v2: update settings

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 7990202903 drm/amdgpu: enable virtual display for navi12
Virtual display is a sw display interface for
bring up and virtualization or for cards without
display hardware.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 71745cf474 drm/amdgpu/gfx10: set tcp harvest for navi12
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 44e9e7c96c drm/amdgpu: add ip blocks for navi12
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 4a0e815fb3 drm/amdgpu/gmc10: set gart size and vm size for navi12
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan f2d6731d77 drm/amdgpu/sdma5: add placeholder for navi12 golden settings
None yet.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 6f523fd7b3 drm/amdgpu/sdma5: declare sdma firmwares for navi12
Declare the firmwares and load the proper ones for navi12.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 4cdfc4a2be drm/amdgpu/gfx10: set rlc funcs for navi12
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 9ff3dba6d6 drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 716e9bb099 drm/amdgpu/gfx10: add placeholder for navi12 golden settings
Not used yet.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 92c123aec1 drm/amdgpu/gfx10: declare cp/rlc firmwares for navi12
Set the name properly to load the right ucode.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 6983469c1a drm/amdgpu/gfx10: add gfx config for navi12
got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE

v2: squash all navi asics together because the
settings are the same.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 59ab8c292b drm/amdgpu/gfx10: set gfx cg for navi12
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 7e17e58bdd drm/amdgpu: set nbio/hdp cg for navi12
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 74b5e509a0 drm/amdgpu: initialize cg/pg flags and external rev id for navi12
don't enable any cg/pg features yet.

v2: calculate external revision id from revision id so that we can
    differentiate navi12 A0 from A1 directly.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan d4d838ba4e drm/amdgpu: use front door firmware loading for navi12
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:40 -05:00
Xiaojie Yuan 4808cf9c2a drm/amdgpu: set asic family and ip blocks for navi12
same with navi10

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
Xiaojie Yuan 42b325e5ec drm/amdgpu: add gpu_info firmware for navi12
gpu_info firmare store asic configuration details.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
Xiaojie Yuan 9802f5d78b drm/amdgpu: add navi12 asic type
Add asic type.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
Xiaojie Yuan 03d0a073cf drm/amdgpu: initialize reg base for navi12
Set up the register offset map for navi12.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
Xiaojie Yuan 6d62290328 drm/amdgpu: add ip offset header for navi12 (v2)
This adds the absolute offsets of each IP regiser block.

v2: Squash in MP1 update

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
John Clements 8c2ef8ca0e drm/amdgpu: update SDMA V4 microcode init
Removed loading duplicate instances of SDMA FW for Arcturus.
We use a single image for all instances.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
John Clements b86f8d8b2b drm/amdgpu: extend PSP FW loading support to 8 SDMA instances
Arcturus has 8 instances of SDMA.  Update host to PSP interface
to handle it.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
John Clements 8fda90e821 drm/amdgpu: disable MEC2 JT context init for Arcturus
We don't need to handle it like other asics.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00
John Clements 6c37bde9c6 drm/amdgpu: update PSP CMD fail response status print
Print the response in hex with the apprpriate mask.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 10:30:39 -05:00